UNIVERSITY OF TEXAS AT DALLAS

DEPARTMENT OF ELECTRICAL ENGINEERING

EEDG 6306 - APPLICATION SPECIFIC INTEGRATED CIRCUIT DESIGN

MIDTERM PROJECT

Submitted by:
Aditya Mittal (axm144430)
Varsha Vivek (vmv140130)

TECHNICAL SPECIFICATION FOR MSDAP

OVERVIEW:
The block diagram of the entire application is as shown below:

Figure 1: Block Diagram of the application

Functional Description:
The controller acts as a medium between the real world and the system. The
input audio signal to the system is converted to its digital format by an ADC and fed
into the controller.
The controller sends the digital audio samples to the MSDAP in a stereophonic
mode. In this mode, the audio sample is received in two channels. We will assume
that both the channels are sampled simultaneously.
The MSDAP acts as a filter and processes the data. The data is then sent back to
the controller. The maximum order of the filter is considered to be 256.
The controller transmits the data back to the real world through the DAC
converter.
The data transmitted between the ADC and the controller is organized into a 16bit frame format per sample.
Between the MSDAP and the control, the audio signals and the coefficients for
each channel are transmitted using the same pin so as to reduce the number of pins
required.

(1.1) SYSTEM SETTING AND SIGNAL AND DATA FORMAT

The major I/O signals required for the operation for the MSDAP, and their formats
are as follows:
1. InputL/R (Input)
This signal holds the input data sampled with respect to Dclk.
Input data could be the audio signal, Rj or coefficients
The format for each input data type is different.
The audio signal transmitted by the controller to the MSDAP is 16-bits wide.
Rj and the coefficients are 9-bits and 8-bits long respectively. There exists a
corresponding Rj and coefficient value for each sample of input data.
The audio signal and the coefficients are represented in its twos compliment
form and the MSB, which is the leftmost bit denotes the sign of the data.
The MSB of the coefficient data represents the sign bit and specifies the type of
operation to be performed on the data. . A 0 in the MSB signifies an addition
operation on data and a 1 signifies a subtraction operation on data. The remaining
8 bits of the LSB refers the address of the data field that would be processed
The unused MSB of Rj and coefficients are zero-padded to match the frame
format of the audio data.
The MSB is transmitted first, followed by 15 bits of LSB at every falling edge of
Dclk.
Input data is sampled at a clock frequency of 768KHz.

2. InReady
This is a status flag that is set by the MSDAP to indicate to the controller if it is
ready to receive data from the controller.
If InReady is high, the controller transmits data to the MSDAP.

3. Frame (Input)
This signal acts as a means of communication between the controller and the
MSDAP and signifies the beginning of a sample data both input and ouput.
When the first bit of the input data is sampled, Frame is set high for the first DClk
pulse.
The Frame lasts for 16 DClk cycles or 40 SClk clock cycles .
Output data is sampled at the falling edge of Frame after every 40 SClk cycles.

4. OutReady (Output)
This is a status flag that is set to LOW when the MSDAP is transmitting the
output.
It is set low at the falling edge of Frame for 40 Sclk clock cycle when the MSDAP
is transmitting output data.

5. OutputL/R (Output)
This field carries the output data generated by the MSDAP.
It is synchronized with the falling edge of SClk.
It is 40 bits long so as to maintain accuracy and account for overflow during the
calculations.
The MSB is the sign bit and is transmitted first, followed by the remaining 39 bits.

Thoughts:
Optimal number of signals are being used here that maintain the functionality and
accuracy of the system.
Rj and coefficient values are also transmitted to the MSDAP through the
InputuL/InputR field. This reduces the number of pins on the chip.
Status signals InReady and OutReady are necessary to communicate the status
of the MSDAP to the controller. Removal of the status signals will lead to incorrect
synchronization between the controller and the MSDAP.
The Frame is important is synchronizing Data Clock and the System Clock.
(1.2) THE OPERATION MODES
The figure2 depicts the FSM designed in order to achieve the desired MSDAP
application.

Figure 2: Finite State Machine for MSDAP

States:
State 0 (Initialization): The chip begins the initialization process when Start is high.
This process involves clearing all the memories and registers. When the initialization
process is completed, the chip enters State 1.
State 1 (Waiting for rj): In this state, InReady is set high. The MSDAP enters State 2
if Frame is detected to be high.
State 2 (Reading rj): In this state, the chip reads the rj values and InReady remains
high. Once all rj values have been loaded, the MSDAP enters State 3.
State 3 (Waiting for coefficients): In this state, InReady is set high. The MSDAP
enters State 4 if Frame is detected to be high.
State 4 (Reading coefficients): In this state, the chip reads the coefficients. InReady
remains high. Once all the coefficients have been loaded, the MSDAP enters State 5.

State 5 (Waiting for input x): In this state, InReady is set high. The MSDAP enters
State 6 if Frame is detected to be high, or State 7 if Reset_n is detected to be low.
State 6 (Working): In this state, the chip continually reads input samples, does the
convolution computation, and sends out the computed output data; InReady
remains high. If Reset_n is detected low, the chip enters State 7 or if the chip
detects 800 consecutive inputs samples as zero, it enters State 8.
State 7 (Clearing): In this state, InReady is set low. All input and output samples in
memories or registers except for rj and coefficients are cleared to zero. If Reset_n is
detected to be low again during this process, the chip will come back to the
beginning of this process. The chip will go back to State 5 when completed with the
task of reset.
State 8 (Sleeping): In this State, the chip goes into sleeping mode while setting
lnReady high. If any non-zero input sample on either left or right channel is
detected, the chip enters State 6. If Reset_n is detected low, the chip enters State 7.

Thoughts:
The waiting states seem to be redundant. They can be combined with the states
following them.
For example: State 1: Waiting for Rj can be merged with the next state, State 2:
Reading Rj. This could save some clock cycles eventually.

(1.3) PIN ASSIGNMENTS

The following figure shows the pin assignment for the I/O signals:
Figure 3: Pin Diagram
of MSDAP PIN
NUMBER

PIN NAME

PIN FUNCTION

1.

SCLK

System Clock
Frequency of
operation: 26.88MHz
This signal provides
timing for the output
signal to be
communicated
between the MSDAP
and the controller.

2.

DCLK

Data Clock
Frequency of

operation: 768KHz
This signal provides
timing for the input
data transmitted by
the controller to the
MSDAP.
3.

VDD

Also: 7,14,19
4.

Power
+1.8V DC

VSS

Ground

RESET

Input signal

Also: 8, 13, 18
5.

This signal resets the

MSDAP chip when it is
set to LOW.
6.

NC

No connection

9.

OUTPUTL

This pin transmits the

left channel of the
stereophonic output
signal. It is
synchronized with the
rising edge of SCLK
and the rising edge of
Frame. Transmits
simultaneously with
OUTPUTR.