Maniteja Yerra

8-1112/7, Shaikpet, Hyderabad-500008

vlsiteja@hotmail.com
Mobile :9032502000

Career Objective :
To obtain a challenging position in a high quality engineering environment where my resourceful
experience and academic skills will add value to organizational operations

Academic Details :

MS in VLSI [2013] with aggregate of 77 from VEDA IIT / JNTUH

B. Tech in ECE [2010] with aggregate of 62.5 from SVIT College/JNTUH University
Intermediate [2006] with aggregate of 90 from SAV & NVJR Junior College
SSC [2004] with aggregate of 84 from City school

Work Experience :

Working as Logic Design Engineer in SoCtronics Technologies Pvt Ltd from Jul 2012 to till date
Role :Verification Engineer

Project Details :
PROJECT : 1

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Thermal Sensor
Verification of IP in both IP level and Soc level. This IP senses the temperature of the
environment using analog block and converts the temperature into frequency which is fed to
digital block. This digital block functionality determines the temperature.
60 days
Verification Engineer
3

Objective

PROJECT : 2

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Description :

Duration
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PLL
Verification of Phase Locked Loop verilog model using the system verilog concepts. It is
verified both in IP level and SoC level. A phase-locked loop or phase lock loop (PLL) is a
control system that generates an output signal whosephase is related to the phase of an input
signal. It is easy to initially visualize as an electronic digital circuit consisting of a variable
frequency oscillator and a phase detector.
60 days
Verification Engineer
3

Objective

PROJECT : 3

Title
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Description :

Duration
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White Field Memory Wrapper

Creation of 28nm and 14nm technology, required size memory instances using, PERL script.
This script runs tool to generate possible memory by considering few internal conditions. This
tool generated memory instances are used to create required size memorys at different frequency
and different corners.
6 months
Scripting Engineer
15

Objective

PROJECT : 4

Title
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Description :
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Objective

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Standard Cells Design Automation

Standard Cells verilog models are created using the PERL script. Script only takes names of the
cells in a file as input to create cells for different technologies at different corners.
1 year.
Scripting Engineer
6

PROJECT : 5

Title
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AHB to AXI Bridge

verification of a bridge which converts AHB Protocols information to AXI protocol and vice
versa. Verification is done using UVM methodology of system verilog Language.
6 MONTHS
Verification Engineer
3

Objective

PROJECT : 6

Title
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Description :
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SATA Controller
Design and verification of "Transport and Link layers" in SATA controller using verilog and
system verilog Languages. This work is done as intern in Soctronics Technologies Pvt Ltd.
1year
Design and Verification engineer
15

Objective

PROJECT : 7

Title
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UVM Scripting
For all the UVM related verification projects there are many things in common and I am scripting
in perl code to reduce the time and risk required for the creation of common components of
bench
6 months
Scripting Engineer
2

Objective

PROJECT : 8

Title
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Description :
Duration
Role
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FILTERS VERIFICATION
Verification of FIR filter and sync filters using the system verilog files which are generated by
the perl code.
1 month
Scripting and verification engineer
1

Objective

PROJECT : 9

Title
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Description :
Duration
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ADAC and VDAC VERIFICATION.

Verifying video and audio DAC in system verilog. using the and I2S protocol interface for
communication . Using UVM methodology from system verilog for verification
2 months
Verification ENGINEER
6

Objective

Field of Interests :

(Exploring the IPs) Verification, RTL DESIGN, STA, LEC.

Skills :

Verilog, System verilog, UVM Methodology

PERL, TCL
AMBA Protocols(ASB, AHB, APB) AXI
I2C, SPI, I2S

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Achievments :

Chess Champion of the year 2015 in office

Cricket champions of the year 2012
Chess Champion of B. Tech college
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Strength & Hobbies :

Forgets time if involved in work is the weakness. Maintaining good relations with Co workers and
completing work in time is my strength
Playing chess, Cricket and volleyball

Watching biopics
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Reference :
Sreedhar Tenukuntla

Staff engineer
Qualcomm
sreedhar.tl@gmail.com
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Declaration :
I hereby declare that the above-mentioned information is correct up to my knowledge and I bear the
responsibility for the correctness of the above-mentioned particulars.
gbgb

Date : 12/2/2016
Place : Hyderabad
(Maniteja Yerra )