Converter for Single-Phase

to Single-Phase Applications

Three-Level Three-Leg

C. B. Jacobina, Y. C. Gomes,

I.

S. Freitas, E. R. C. da Silva

Departamento de Engenharia Eletrica

Universidade Federal de Campina Grande
Caixa Postal 10.105
58109-970 Campina Grande - PB - Brazil
E-mails: [j acobina,yuricgomes,isaacfreitas,edison] @ dee.ufcg.edu.br

Abstract- This paper investigates a three-level three-leg

dc-link converter for ac to ac single-phase to single-phase
conversion. PWM methods, which are based on per-phase
and space-vector approaches, extends the concept of local
and general apportioning factor. A control strategy for
applications in which the input and output frequency are
equal, in order to obtain the maximum utilization of the dclink voltage, is also presented. Experimental and simulated
results are presented.

v,.,

I. INTRODUCTION

The three-level voltage converter include an array of power

switch semiconductors and a capacitor bank at the dc-link, for
generating an output of multilevel voltages. Compared with
two-level converters, three-level converter support half of the
voltage stress on power switches, for the same dc-link voltage,
and generate lower harmonics at the same switching frequency
[1], [2], [3], [4]. It is also interesting to employ three-level
converter for low power applications [5].
In some applications, the input voltage source and the load
are both of single-phase type. Ac-ac single-phase to singlephase conversion can be obtained by using dc-link full-bridge
(four-leg) topology. Such topology require a relatively large
number of power switches, particularly when a three level
converter topology is used.
The usual alternative to reduce the number of power
switches is obtained with the half-bridge (two-leg) topology.
However, the half-bridge converter has half of the voltage
capability of the full-bridge converter, an extra ac current at
the capacitor and higher harmonic distortion.
A two-level three-leg converter [6], [7], [8], [9], [10], [11],
is an interesting approach since it uses less switches than the
four-leg topology and its performance is better than that of the
two-leg topology.
This paper investigates the three-level three-leg dc-link
converter shown in Fig. 1. Several relevant aspects of converter
are developed:

i) PWM methods based on per-phase and space-vector

approaches, extending the concept of local and general apportioning factor.
1-4244-0714-1/07/$20.00 C 2007 IEEE.

1 Grid

1 Load

Fig. 1. Three-level three-leg ac-ac dc-link converter.

ii) A control strategy for applications in which the input and

output frequencies are equal (e.g., UPS applications) in order
to obtain the maximum utilization of the dc-link voltage, based
on the synchronization between input and output converter

voltages.

II. CONVERTER VOLTAGES

The converter (Fig. 1) is connected to the grid by the

filtering reactance Xg. It comprises a power converter with
three three-level legs, a capacitor bank at the dc-link for
supplying, through the filter impedance Zf, a single-phase
load. The leg constituted by qs,, q2, qq,, and q,2 is shared
between the rectifier and inverter converters.
The grid converter voltage vg and the load converter voltage
v, can be expressed as a function of the converter pole voltages

1515

TABLE I

The voltage v* is calculated by taking into account the

general apportioning factor ,u, that is
1
(10)
v
Ep
-pv
+(p-

POLE VOLTAGES AND CONDUCTION STATES OF THE LEG AS A FUNCTION

OF THE CONDUCTION STATES OF THE POWER SWITCHES (X = g, 1, s).
Vxo

-E/2

1E/2

Sx
0
1
2

qxl

qx2

0
0
1

0
1

11

qxlI
1
1
0

1
0
0

2V

x2

vgo, Vio and v,o, that is,

Vg
Vi

= vgo -V
Vio -Vso.

(1)

(2)

Since vso contributes for both vg and v, it cannot be calculated

independently from (1) and (2).
The pole voltages are given by
Vxo

(Sx -1) 2

for x

g, 1, s

(3)

where sx = 0, 1, and 2 is the conduction state of the leg x

and E (= V,1 + VC2) is the dc-link voltage. Table I presents
the pole voltages and the value of sx as a function of the
conduction state of the switches.
III. PWM TECHNIQUES

Considering that vg and v* denote the desired reference

voltages, then the reference pole voltages can be expressed by
reformulating (1) and (2), as
V*

V*

+ V*

(4)

V*0 =
v*O =

Vi + V1

(5)

v.

(6)

The problem to be solved is how to determine vgo, v10 and

v50 from (4)-(6) since the desired voltages vg and v* have
been specified. Two approaches can be proposed to solve this
problem.
A. Per-phase PWM techniques
Method 0
An independent control of vgO and v10 can be obtained by
specifying that v*o = v1 = 0. In this case, from (4)-(5) it
follows that

where vU, = max 0 and v*

= min 0 where 0 =
{v*. O}. Expression (10) was derived by using the same
approach as used to obtain the equivalent one for the threephase PWM modulator [12], [13].
The factor ,u (O < p < 1) is given by
VGjn + E/2
(1 1)
p E + (vo,
vi )
= max Oo and v
where v,
= min o for 00
{fV V10, v*0}. The factor ,u indicates the distribution of maximum and minimum pole voltages.
In this case, the proposed algorithm is:
Step 1. Choose the general apportioning factor ,u and calculate
v from (10).
Step 2. Determine vg0, v10 and v*0 from (5).
Step 3. Generate the gating signals by comparing modulating
signals vg0, v10 and v*0 with two high frequency triangular
carrier signal, as done for the usual three-level converters [3].
Method B: Local apportioning factor
In this case the voltage v11 is calculated from the local
apportioning factor ,up, that is,
=

VX =

E(,ux- )-,xv*

(px - I)v m, (12)

maxUg and v*
= minUg if x
g or
=
x
if
and
v*
with
min
=
1,
Ug
Ul
maxUl
{vg,}O and Ul {v= , ,}.
The local apportioning factor ,ux is given by

where vxm

vxm

lix

VOx m + E/2

E + (vox m -VOxrn )

= max Uox and vo*x

{vgO, vso} with x g or Uox

(13)

min Uox for Uox

{v1, v*0} with
x = 1. The factor fix indicates the distribution of the local
maximum and minimum pole voltages.
Besides (12), the voltage V/ must also obey the other
converter side. Then, from (5) and (4) limits of v*,x for x g
and x = 1, can be calculated, respectively, as

where vo*
Uog

V/-x Ml

E/2 -v1

Uol

(if x =g)

(14)

-E/2- v
(15)
x
E/2 -vg
(8)
(16)
(if = 1)
V*
-Vg.
-E/2
(17)
m
mtx
Consequently, the phase voltages vg* and v* will be effectively
controlled if the following inequalities are valid:
In this case the apportioning factor can be changed as a
function
of the modulation index (im) to modify the THD
Vg*| < E/2 and lv1* < E/2.
(9)
(total harmonic distortion) of rectifier (x g) or inverter (x
In this case the converter has the same voltage rating as 1) voltages. The algorithm is:
obtained for the two-leg configuration. The gating signals can Step 1. Choose the local apportioning factor lix so that G or
be generated by comparing modulating signals vg*O, v* and L converters are optimized and calculate V/,X from (12).
v*O with two high frequency triangular carrier signal, as done Step 2. Determine v/,X limits, v11xm and vjx , from (14)
for the usual three-level converters [3].
and (15) or (16) and (17). Limit V/,X to Vjixrn if V/,X >
Vjxrn and v/,X to Vux,
if Vuux < Vjix
Method A: General apportioning factor
vgo
v*0

vg
V*

(7)

1516

V/x m

Step 3. Determine vgO* v*0, and v*0 from (5) using v*

Step 4. Use Step 3 of Method A.

v*

B. Space vector PWM

The voltages supplied by the power converter can be displayed in the g x I space vector plane. This vector plane is
defined such that voltages vg and vl coincide with the real
axis (Re) and the imaginary axis (Im), respectively. A voltage
vector in this plane can be represented by vi = vg + jvi
with i = 1, 2, ..., 27 as shown in Fig. 2. There are 27 voltage
vectors, where 18 are different (vo to v$ ) and twenty four
sectors k (1 to 24). The two-level three-leg converter creates
only 8 vectors, where 7 are different (vo, vg, v, , VI, V4,
v>$, and v$ ) and defines six sectors (1-9-10-11, 2-12-13-14,315-16-17, 4-18-19-20, 5-21-22-23, 6-7-8-24)
Let v* = vg + J represents the reference voltage to
be synthesized by the inverter within one switching cycle of
length T. According to the space vector technique [14], [15],
the reference vector located in sector k must be synthesized
by using three different vectors that define the vertices of the
sector where the reference vector is found.
Let v* = vg + Jv1 represent the reference voltage to be
synthesized by the inverter within one switching cycle of
length T located in a sector in which there are four vectors,
named Va, Vb, v, and v', where v, = v'. According to the
space vector technique, the reference vector located in sector
k must be synthesized by using
V*V

Va ~ta
vbtb + vcTtc +v' T
T +Vb
VaT
T +VT +VT

t
+ Vb tb
a- ta
VaT
T

+ Vc

tc T+tlc

18
(18)

19
(19)

with the time weights for vectors Va, Vb, vc, and v' being,
respectively, ta, tb, tc and tl restricted to T = ta + tb + tc + t.
It can defined a ratio kt = tcl(tc + tl ) that can be used to
modify the THD of the voltage generated.
IV. VOLTAGE ANALYSIS
The three-leg converter allows to share the voltage capability between the rectifier and the inverter, i.e., Vg < (1 -n)E
and V1 < nE, where Vg and V, denote the amplitude of
the grid and load converter voltages, respectively and the
parameter n is restricted to 0 < n < 1. Table II presents
the dc-link voltages required for the three-leg converter, normalized to the dc-link voltage of four-leg converter, for three
different applications conditions: case a, Vg = V = V,; case
b, Vg = 2Vn, V1 = V,; and case c, Vg = Vn, V1 = 2Vn, where
Vg denote the amplitude of the grid voltage, V1 the amplitude

of the load voltage and

Fig. 2. Space vectors generated by the converter, sectors and the reference
vector in gl plane.

TABLE II
NORMALIZED DC-LINK VOLTAGES REQUIRED FOR THE THREE-LEG
CONVERTER.

case a
case b
case c

the voltage capability for three-leg converter to the same

capability of the four-leg converter.
V. SYNCHRONIZATION TECHNIQUE
Input and output voltage synchronization can be used to
increase the voltage capability of the three-leg converter. The

synchronization technique is used when the grid and load

frequencies are equal.
From (1) and (2) we can derive
|Vg
Vvgi

vg - vj

respectively.
In some applications, the load and grid frequencies can be
equal (applications in which the grid current and the load
voltage amplitude must be controlled, e.g., UPS). In this case,
it is possible to define a synchronization technique to increase

<
<
<

(20)
(21)
(22)

E
E
E.

When v, and vg are unrelated, (22) defines the maximum grid

and load voltages for a given dc-link voltage.
Lets consider that vg = Vg Cos (wt), V/ = Ccos (wt -),
i.e., vg synchronized to v, with a phase angle E. The amplitude
of the voltage vg- vl (Vgl) in (22), is given by

V, the rated reference value. Thus for

cases a or b and c it is need to increase the dc-link voltage

of 100% or 50% of dc-link voltage of the four-leg converter,

F =2
F =1.5
F =1.5

Vgi

V2+

E).

(23)

For KE1< 180 this amplitude is smaller than Vg + V1, so the

reduction can lead to a value of dc-link that is smaller than
that calculated without synchronization.
Fig. 3 shows the dc-link voltage for full-bridge four-leg
configuration (4L) and three-leg configuration (3L) at different
operating conditions i.e., E = fv, (Vg) given V = Vr (Vr is

1517

6F

V1 =Vr

43

3L (4)
_,

00)

4L

vg /Vr

3L (I- 82)
2

Fig. 3. Dc-link voltage for Configurations 4L and 3L

Vg variable and V1 = V,

3
0
t(s)

(3L1g or 3L2g) for

TABLE III
NORMALIZED DC-LINK VOLTAGE OF THE THREE-LEG CONVERTER WITH

Fig. 4. Relation ID

Ig as a function of XI for case a.

factor. The maximum value of igl is given by

SYNCHRONIZATION AND HARMONIC IN THE VOLTAGES.

case a
1 if Vh < 0.0 Vn
O.9 VnA-Vh if Vh > O. Vn
I

V + Vh,

cases b or c
1 if Vh < 0.G Vn
F =l2( V+-V h if Vh > OG 2VV

Igi

2(Vn+Vh)I

where

k,

sin(Og).

= El, 2, 3, E4, where

a nominal reference value) and 1I
E1 = 0, E2 = 60, E3 = 90, E4 = 120. The equivalent
characteristics for E = fvg (Vi) given Vg = Vr are identical.
< 60, the dc-link voltage value
It can be noted that for KE
required by the three-leg converter is equal to that of four-leg
converter.
It is important to consider the case when only part of the
output voltage can be synchronized with the input voltage. For
example, this occurs when there are low frequency harmonic
voltage components in both side of the converter. As an
example Table III presents the dc-link voltage, normalized by
the dc-link voltage of four-leg converter, required for the threeleg converter for cases a, b and c for l = 60 and harmonic
voltage of amplitude Vh present in the grid and load converter
voltages. It can be noticed that for case a with Vh < 0.49V,
and cases b and c with Vh < 0.76Vn, the three-leg converter
requires the same dc-link of the four-leg converter. Then, even
with high value of harmonic voltages present, it is possible to
maintain the dc-link voltage of the three-leg converter equal
to that of the four-leg converter.

VI. SHARED-LEG CURRENTS

The currents flowing through shared leg depends on igl

ig + il. When the synchronization is used and the input power
factor is unitary, vg and vl are related and then ig and ii are
also related. Neglecting the converter losses, VgIg cos(Og) =
Vill cosQ(1), where Ig and II are the amplitude of the grid
and load current, respectively, and cos(Ql) is the load power

ksin (a)

Cos(a) ]2 +[k2
k20 [1 kv Cos
(q51)

Ig
=

Vg/Vi,

/ + E, klo

COS

(X1)

(24)

cos(Og) and k2O

Fig. 4 shows the ratio Igl/Ig as a function of /1 (71 < 0

implies in inductive load and 71 > 0 implies in capacitive
load) for case a (i.e., Vg = V = Vr). It can be noted that
there is a wide range of /1 in which 'gl is not larger than Ig
(note that Ig < II). For case b (i.e., Vg = 2Vr, Vl = Vr) and
c (i.e., Vg = Vr, V = 2Vr) there is also a wide range of 1 in
which Igi < Ig. The case E = Og is analyzed because vl can
also be synchronized with eg (see Section VIII). Then switches
of the shared-leg can operate without current restrictions.
VII. POWER RATINGS

By using the synchronization technique, the dc-link voltage

of the three-leg configuration is equal to that of the four-leg
configuration. Also, the current rating of the switches of the
three-leg and four-leg configurations is close to each other.
Consequently, the power ratings of the three-leg and four-leg
converters are also compatible.
VIII. CONTROL SYSTEM

Fig. 5 presents the converter control block diagram. The

capacitor dc-link voltage v, (v, = E) is adjusted to a reference
value by using the controller R,. This controller provides the
amplitude of the reference current, Ig*. To have power factor
control, the instantaneous reference current ig is synchronized
with voltage eg. This is obtained via blocks SYN-g and
GEN-g. The output angle 6g of block SYN-g indicates the
instantaneous phase of voltage eg. The synchronization is
obtained from the detection of eg zero crossing associated
with a PLL scheme. From the synchronization angle and the

1518

6g

eg

----

Fig. 5.

Control block diagram.

200

1 50

,'0

100

> 0 'V

,5X
0

'

-100

-150 -,
.
-200
-200

-150

-100

L
-50

'

-40
-60

,
50

0
Volts

1111111

-20

100

150

80

200

t[seg]

(b)

(a)

(c)

-0.3

0,4L

0.02

0.04

0.06

0.08

t[seg]

0.1

0.12

0.14

-0.40
0.02
0.04
0.06
0.08
0.1
0.12

t[seg]

0.14

(e)

(d)

Fig. 6. Variables of the system for vg = Vg 0 wt) and v, = V1 i wt). (a) Voltage vector locus. (b) Grid voltage (method 0). (c) Grid and load currents
(method 0). (d) Grid and load currents (method A). (e) Grid and load currents (method B).

amplitude Ig, the current i* is generated from block GEN-g.

The current controller defines the input reference voltage vg.
rthe operation
Either the regulation of rthe load voltage
in open loop is chosen by connection of switch k1 to points
a or b; i.e., for an open loop, k1 is connected to point a,
for closed loop, k1 is connected to point b. When the output
or

voltage does not need to be regulated the output reference

voltage v* is defined directly from the reference load voltage
e1
For closed loop voltage the controller Rei defines v* PWM
control is implemented by using one of the methods introduced
before.
The output reference voltage can be obtained without syn-

1519

200 r-

200 r-

1 50

150

100
50

-50

>-5

-100

-100

-1 50

-150

-200
-200

-200

-150

-100

-50

0
Volts

50

100

150

200

I'
-0.61
0

0.02

0.04

0.06

(a)
Fig. 7.

t[seg]

0.08

0.1

0.12

0.14

0.02

0.04

Voltage vector locus (a), the grid voltage (b) and the grid and load currents for vg

Wi.

IX. SIMULATED RESULTS

Figs. 6 show the voltage vector locus (a), the grid voltage
(b) and the grid and load currents for vg = Vg cos(wt) and
vi = Vi sin(wt) with Vg = Vi = 0.9E/2 and E = 160V. Fig.
6(a)-(c), Fig. 6(d) and Fig. 6(e) are obtained with Methods
0, A and B, respectively. The voltage locus are equal for all
three methods and the grid voltage presents the same shape in
each method. It can be noted that, i) the vector locus is inside
of the inner square, ii) the voltage has three level and iii) the
highest current ripple is found with the Method 0.
Fig. 7 shows the same variables for vg = Vg cos(wt) and
vi = V1 cos(t -7/3) with Vg = Vf = 0.9E and E = 160V
with Methods A. It can be noted that the vector locus is
closed to the voltage limits allowed and the voltage has five
level. This case illustrates the operation where vg and v, are
synchronized with KE1< 600 and the converter can generate
grid and load voltage amplitude higher than E/2.
X. EXPERIMENTAL RESULTS
Selected experimental results of the three-leg converter are
given in Fig. 8 supplying a RL load with Method 0. The
three parts in each figure are: (a) grid voltages and currents,
(b) dc-link voltage, and (c) load voltage and current.

XI. CONCLUSIONS
This paper investigates a three-level three-leg dc-link converter for ac to ac single-phase to single-phase conversion.
It was presented the PWM methods based on per-phase and

t[seg]

0.08

0.1

0.12

(c)

(b)

chronization (switch k2 is connect to the point b) or with

synchronization (switch k2 is connected to the point a). For
the case without synchronization the instantaneous phase of
the output voltage is generated independently by integrating
the reference load frequency w1. When the synchronization
mode is used, e1 (that becomes v* when the load filter Zf
is not used) is synchronized with v*. The synchronization is
achieved by using the block SYN-l. The block GEN-l is
similar to block GEN-g. The block SYN-l is also similar
to block SYN-g, but with a limitation in the load frequency
where Awij,m is the
variation, i.e., w1 = WiN Aw01m
maximum variation chosen for

0.06

Vg 0

wt) and vl

Vl 0

wt

-w
-

(c).

space-vector approaches. A control strategy for applications

in which the input and output frequency are equal was also
presented, in order to obtain the maximum utilization of
the dc-link voltage. Experimental and simulated results were
presented.

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1520

200F

100I

IDU

1,.Im, 1,

1.i

I.

I.

II

.1

I-

.,

II. IL

kll.il, 1A
9

I IC fA

100

50

-0o

0.05

0.1
t(s)

0.15

OL_

0.2

0.05

(a)

0.1
t(s)

0.15

(b)

100r

-5

0.0

I
(H0.005

0.005

0.01
t(s)

0
0.015

0.02

(c)
Fig. 8. Experimental results. (a) grid voltages and currents, (b) dc-link voltage, and (c) load voltage and current.

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1521

0.2