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RACHIT CHHAJER

1567, MARKET STREET #1: SANTA CLARA, CA 95050 : rachit160186@gmail.com : (408) 221-5921

Objective: To obtain an entry level position in VLSI methodology.


Education:
 SANTA CLARA UNIVERSITY 3.7/4.0 01/2009 - 12/2010 Santa Clara, CA
Master of Science, Electrical Engineering
 JAWAHARLAL NEHRU UNIVERSITY 3.4/4.0 10/2004 – 06/2008 INDIA
Bachelors, Electronics and Communication Engineering

Experience:
Reliance Infocomm 01/2008 – 05.2008 Hyderabad, India
Telemetry System Intern
 Designed a Telemetry System for Utility Metering Application through a GSM Network using
AT89C51 Micro-controller, for auto-bill generation at the customer end and power-theft prevention.

Santa Clara University 09/2009 – 06/2010 Santa Clara, CA


Graduate Teaching Assistant - Electronic Circuits
 Mentoring the students to perform lab experiments using National Instruments’ ELVIS III Design
Board using MultiSIM 11.1, LabView and Mentor Graphics’ PSpice simulators.

Relevant Work Experience:

 Single cycle Pipelined datapath for a MIPS microprocessor


 Implemented in Verilog, a Single cycle pipelined datapath for a MIPS microprocessor using
Synopsys’ VCS and Xilinx’s ISE simulators.

 Implemented in Verilog, a 32-bit Cyclic Redundancy Check (CRC) and Dishwasher Microcontroller
using ModelSim, Synopsys-VCS and Xilinx’s ISE.

 Design and Layout of a 4 bit Manchester Carry Chain Adder using Mentor Graphics EDA tool.

 Wrote a research paper on Hybrid 3D SRAM-MRAM Architecture for L2-Cache Memories.

 Multi-Cycle DSP MIPS Processor:


 RTL Implementation (Simulation and Synthesis) in Verilog.
 Formal Verification using Synopsys’ “Formality” Verification tool for RTL-Gate Level and Gate
Level-Gate Level verification of LSI 10K and tsmc_90nm libraries.
 Performed Timing Analysis, Timing Closure and Power Analysis using Synopsys’s Prime Time.

 Compiled, Synthesized and performed floor-planning, placement and routing to optimize for area and
performance, a Cellular Automata Pseudo-random number generator on a Virtex-4 FPGA system.

 Currently working on Power Characterization of a 16KB SRAM.


 The goal is to design a 16KB SRAM and characterize the power consumed in different modes of
operation (READ, WRITE, IDLE).

Skills:
 Programming and Scripting Languages: C, Verilog, Perl, MATLAB, MIPS Assembly language.
 Operating Systems: Windows 98, XP, Vista and 7, Linux, Unix.
 Design and Simulator Tools: Mentor Graphics PSpice and Layout Suite, Synopsys Formality
Verification Tool, VCS and Prime Time, ModelSim, Xilinx’s ISE, LabView, MultiSim.
 Character: Responsible, Strong Interpersonal Skills and Passion for the Engineering World.
 Additional: Enjoy travelling, reading and writing poetry, playing soccer and percussion.

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