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1567, MARKET STREET #1: SANTA CLARA, CA 95050 : rachit160186@gmail.com : (408) 221-5921
Experience:
Reliance Infocomm 01/2008 – 05.2008 Hyderabad, India
Telemetry System Intern
Designed a Telemetry System for Utility Metering Application through a GSM Network using
AT89C51 Micro-controller, for auto-bill generation at the customer end and power-theft prevention.
Implemented in Verilog, a 32-bit Cyclic Redundancy Check (CRC) and Dishwasher Microcontroller
using ModelSim, Synopsys-VCS and Xilinx’s ISE.
Design and Layout of a 4 bit Manchester Carry Chain Adder using Mentor Graphics EDA tool.
Compiled, Synthesized and performed floor-planning, placement and routing to optimize for area and
performance, a Cellular Automata Pseudo-random number generator on a Virtex-4 FPGA system.
Skills:
Programming and Scripting Languages: C, Verilog, Perl, MATLAB, MIPS Assembly language.
Operating Systems: Windows 98, XP, Vista and 7, Linux, Unix.
Design and Simulator Tools: Mentor Graphics PSpice and Layout Suite, Synopsys Formality
Verification Tool, VCS and Prime Time, ModelSim, Xilinx’s ISE, LabView, MultiSim.
Character: Responsible, Strong Interpersonal Skills and Passion for the Engineering World.
Additional: Enjoy travelling, reading and writing poetry, playing soccer and percussion.