MOHAN S

TULIP Apartment,
Flat No F2, CLC Colony,
2nd Main Road, Masthan Sheriff Nagar,
Chrompet,
Chennai,
Tamil Nadu-Pin: 600 044.
E-MAIL: smohan_me@yahoo.com Mobile: +91 99401 74143

OBJECTIVE:
Intend to build a career with leading corporate of hi-tech environment with committed
people, which will help me to explore myself fully and work for the mutual benefit of organization
and myself.

ACADEMIC DETAILS:

EXAMINATION YEAR OF CGPA/ % OF

COURSE INSTITUTION
AUTHORITY PASSING MARKS
M.E College of Engineering, (Main
Anna University Apr 7.583
(Applied Campus), Anna University,
(Tamil Nadu) 2009 CGPA
Electronics) Chennai.

B.E Dhanalakshmi Srinivasan Engg. Anna University Apr

79.00%
(ECE) College, Perambalur. (Tamil Nadu) 2006

Kurinji Hr.Sec.School. State Board Mar

H.S.C 83.42%
Namakkal. (Tamil Nadu) 2002

Govt.High School, State Board Mar

S.S.L.C 79.40%
Sobanapuram, Trichy. (Tamil Nadu) 2000

SOFTWARE SKILLS:

S.NO DOMAIN EXPERTS TOOLS

1 C Language Turbo C++
2 Embedded C Raisonance Kit 6.1(RIDE)
3 Verilog HDL Xilinx 9.1i, Modelsim 6.0
4 Digital Signal Processing Simulink (MATLAB 7.0)
AREA OF INTEREST:

 C Language
 Digital Electronics
 Microprocessor
 VLSI Design and Signal
Processing

ACADEMIC ACHIEVEMENTS:

 First Class with Distinction in

Bachelor of Engineering.
 Attended Second National Conference on NCVESCOM’09 during 8-9 April 2009 and
Proceedings published with ISBN 93-80043-17-1
 Attended two days National Level Workshop on VLSI & EMBEDDED SYSTEMS in
SRM University on 8-9th October 2009.

EXPERIENCE:

 Working in Aarupadai Veedu Institute of Technology as Lecturer in the department of

ECE for Five months

PROJECT DETAILS:

A Novel ΔΣ Control System Processor and Its FPGA Implementation

Title (IEEE –MAR’2008)

Duration From May’2008

A novel delta sigma control system processor is a new technology and
Description architecture for digital control system. It is used to shape either analogue or
multi-bit digital signals into one bit format at very high sampling frequencies.
It contains all the useful information and it is possible to perform digital signal
processing directly control to any physical device. A simple conditional-
negate-and-add unit is instead used for operations in control law
implementation. For this reason, the proposed processor has a very small area
and very high sampling rates implemented in VLSI system.

RESPONSIBILITIES UNDERTAKEN:

 Class Representative in Master

of Engineering.
  Class Representative in
Bachelor of Engineering.
 CADANZA’05 Scrutiny
Member.

LINGUISTIC PROFICIENCY:

 To speak : English, Tamil

 To write : English, Tamil
 To Read : English, Tamil

HOBBIES:

 Listening Music
 Internet Surfing

EXTRA CURRICULAR ACTIVITIES:

ACTIVITIES LEVEL OF
YEAR ACHIEVEMENTS
PARTICIPATED PARTICIPATION
Carom Feb-2004 Intra College First Prize

Mime Jan-2005 Inter College Second Prize

PERSONAL INFORMATION:

 Date of Birth : 05-06-

1983.
 Father’s Name: Mr. P.
Seerangan.
 Father’s Occupation : Farmer
 Mother Tongue : Tamil
 Nationality : Indian
 Gender : Male
 Marital Status : Single
 Permanent Address : #5/198,
Ossirapalli (Village),
Sobanapuram (P.O),
Thuraiyur (T.k),
Trichy (D.t),
Tamil Nadu-Pin: 621 018.
Ph: 04327-252897.
DECLARATION:
I do hereby declare that the particulars of information and facts stated herein above are true,
correct and complete to the best of my knowledge and belief.

Place : Signature :

Date : Name : MOHAN.S

(IN BLOCK LETTERS)