Digital Design

Chapter 8:
Programmable Processors
Slides to accompany the textbook Digital Design, First Edition,
by Frank Vahid, John Wiley and Sons Publishers, 2007.
http://www.ddvahid.com

Copyright 2007 Frank Vahid

Instructors of courses requiring Vahid's Digital Design textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities,
subject to keeping
this copyright
notice in place and unmodified. These slides may be posted as unanimated pdf versions on publicly-accessible course websites.. PowerPoint source (or pdf
Digital
Design
with animations) may not be posted to publicly-accessible websites, but may be posted for students on internal protected sites or distributed directly to students by other electronic means.
Copyright 2006
1
Instructors may make printouts of the slides available to students for a reasonable photocopying charge, without incurring royalties. Any other use requires explicit permission. Instructors
Franksource
Vahid
may obtain PowerPoint
or obtain special use permissions from Wiley see http://www.ddvahid.com for information.

8.1

Introduction
Programmable (general-purpose) processor

Mass-produced, then programmed to implement different processing tasks

Well-known common programmable processors: Pentium, Sparc, PowerPC
Lesser-known but still common: ARM, MIPS, 8051, PIC
Low-cost embedded processors found in cell phones, blinking shoes, etc.

Instructive to design a very simple programmable processor

Real processors can be much more complex

Seatbelt
3-tap FIR filter
warning light
program
program

Other
programs

3
2

p
ta

i
s

1
0
2x4

Instruction
memory I
r

Data memory D

x(t)

x(t-1)

x(t-2)

xt0

c0

xt1

c1

xt2

c2

PC

Seatbelt warning
light single-purpose
processor

reg

3-tap FIR filter

single-purpose processor

Register file
RF
Controller

ALU
Control unit

Digital Design
Copyright 2006
Frank Vahid

n-bit
2x1

IR

Datapat
h

General-purpose processor
2

Note: Slides with animation are denoted with a small red "a" near the animated items

8.2

Basic Architecture
Processing generally consists of:
Loading some data
Transforming that data
Storing that data

Data memory D

Basic datapath: Useful circuit in a

programmable processor

somehow
connected
to the
outside
world

n-bit
2x1
a

p
ta

Can read/write data memory, where main

data exists
Has register file to hold data locally
Has ALU to transform local data

i
s

Register file RF
r

ALU
g

Datapath
Digital Design
Copyright 2006
Frank Vahid

Basic Datapath Operations

Load operation: Load data from data memory to RF
ALU operation: Transforms data by passing one or two RF register values through
ALU, performing operation (ADD, SUB, AND, OR, etc.), and writing back into RF.

Store operation: Stores RF register value back into data memory

Each operation can be done in one clock cycle
Data memory D

Data memory D

Data memory D

n-bit
2x1

n-bit
2x1

n-bit
2x1
a

Digital Design
Copyright 2006
Frank Vahid

Register file RF

Register file RF

Register file RF

ALU

ALU

ALU

ALU operation

Store operation

Load operation

Basic Datapath Operations

Q: Which are valid single-cycle operations for given datapath?
Move D[1] to RF[1] (i.e., RF[1] = D[1])
A: YES That's a load operation

Store RF[1] to D[9] and store RF[2] to D[10]

A: NO Requires two separate store operations

Add D[0] plus D[1], store result in D[9]

A: NO ALU operation (ADD) only works with RF. Requires two load operations
(e.g., RF[0]=D[0]; RF[1]=D[1], an ALU operation (e.g., RF[2]=RF[0]+RF[1]), and
a store operation (e.g., D[9]=RF[2])

Digital Design
Copyright 2006
Frank Vahid

Data memory D

Data memory D

Data memory D

n-bit
2x1

n-bit
2x1

n-bit
2x1

Register file RF

Register file RF

Register file RF

ALU

ALU

ALU

ALU operation

Store operation

Load operation

Basic Architecture Control Unit

D[9] = D[0] + D[1] requires a

sequence of four datapath operations:
0: RF[0] = D[0]
1: RF[1] = D[1]
2: RF[2] = RF[0] + RF[1]
3: D[9] = RF[2]

Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

Data memory D

Each operation is an instruction

Sequence of instructions program

Looks cumbersome, but that's the world
of programmable processors
Decomposing desired computations into
processor-supported operations
Store program in Instruction memory
Control unit reads each instruction and
executes it on the datapath

PC: Program counter address of

current instruction
IR: Instruction register current
instruction

Digital Design
Copyright 2006
Frank Vahid

n-bit
2x1
PC

IR
Register file RF

Controller
ALU
s g
i n a sl

Control unit

t o

c o n t r o l t h e

d a t a p a t h

Datapath

Basic Architecture Control Unit

To carry out each instruction, the control unit must:

Fetch Read instruction from inst. mem.

Decode Determine the operation and operands of the instruction
Execute Carry out the instruction's operation using the datapath
Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

PC
0>1

Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

IR
RF[0]=D[0]
PC

IR
RF[0]=D[0]

PC
1

Controller
s g
i n a sl

t o

c o n t r o l t h e

s g
i n a sl

t o

c o n t r o l t h e

d a t a p a t h

Register file RF
R[0]: ?? 99

"load"
s g
i n a sl

(a)

n-bit
2x1
IR
RF[0]=D[0]

Controller

d a t a p a t h

Control unit

Data memory D
D[0]: 99

t o

c o n t r o l t h e

Controller

d a t a p a t h

Control unit

Fetch

ALU
s g
i n a sl

t o

c o n t r o l t h e

d a t a p a t h

(b)

Digital Design
Copyright 2006
Frank Vahid

Datapath

Control unit

Decode

Execute

(c)

Basic Architecture Control Unit

To carry out each instruction, the control unit must:

Fetch Read instruction from inst. mem.

Decode Determine the operation and operands of the instruction
Execute Carry out the instruction's operation using the datapath
Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

PC
1>2

Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

IR
RF[1]=D[1}
PC

IR
RF[1]=D[1]

PC
2

Controller
s g
i n a sl

t o

c o n t r o l t h e

d a t a p a t h

Digital Design
Copyright 2006
Frank Vahid

s g
i n a sl

t o

c o n t r o l t h e

d a t a p a t h

Register file RF
R[1]: ?? 102

"load"
s g
i n a sl

Fetch

n-bit
2x1
IR
RF[1]=D[1]

Controller

Control unit
(a)

Data memory D
D[1]: 102

t o

c o n t r o l t h e

d a t a p a t h

Controller

Control unit

ALU
s g
i n a sl

t o

c o n t r o l t h e

d a t a p a t h

(b)

Decode

Datapath

Control unit

Execute

(c)

Basic Architecture Control Unit

To carry out each instruction, the control unit must:

Fetch Read instruction from inst. mem.

Decode Determine the operation and operands of the instruction
Execute Carry out the instruction's operation using the datapath
Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

PC
2>3

Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

IR
RF[2]=RF[0]+RF[1]
PC

IR
RF[2]=RF[0]+RF[1]

PC
3

Controller
s g
i n a sl

t o

c o n t r o l t h e

s g
i n a sl

t o

c o n t r o l t h e

d a t a p a t h

Register file RF
R[2]: ?? 201
99

"ALU (add)"
s g
i n a sl

(a)

n-bit
2x1
IR
RF[2]=RF[0]+RF[1]

Controller

d a t a p a t h

Control unit

Data memory D

t o

c o n t r o l t h e

Controller

d a t a p a t h

Fetch

102
201

Control unit

ALU
s g
i n a sl

t o

c o n t r o l t h e

d a t a p a t h

(b)

Digital Design
Copyright 2006
Frank Vahid

Datapath

Control unit

Decode

Execute

(c)

Basic Architecture Control Unit

To carry out each instruction, the control unit must:

Fetch Read instruction from inst. mem.

Decode Determine the operation and operands of the instruction
Execute Carry out the instruction's operation using the datapath
Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

PC
3>4

Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

IR
D[9]=RF[2]
PC

IR
D[9]=RF[2]

PC
4

Controller
s g
i n a sl

t o

c o n t r o l t h e

d a t a p a t h

Digital Design
Copyright 2006
Frank Vahid

s g
i n a sl

t o

c o n t r o l t h e

d a t a p a t h

Register file RF
R[2]: 201

"store"
s g
i n a sl

Fetch

n-bit
2x1
IR
D[9]=RF[2]

Controller

Control unit
(a)

Data memory D
D[9]=?? 201

t o

c o n t r o l t h e

d a t a p a t h

Controller

Control unit

ALU
s g
i n a sl

t o

c o n t r o l t h e

d a t a p a t h

(b)

Decode

Datapath

Control unit

Execute

(c)

10

Basic Architecture Control Unit

Init
Fetch

PC=0

IR=I[PC]
PC=PC+1

Decode

Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

Execute

Data memory D

s g
i n a sl

t o

c o n t r o l t h e

d a t a p a t h

n-bit
2x1

Controller
s g
i n a sl

t o

c o n t r o l t h e

d a t a p a t h

PC

IR
s g
i n a sl

t o

c o n t r o l t h e

Register file RF

d a t a p a t h

s g
i n a sl

t o

c o n t r o l t h e

d a t a p a t h

Controller

Digital Design
Copyright 2006
Frank Vahid

ALU

11

Datapath

Control unit

Creating a Sequence of Instructions

Q: Create sequence of instructions to compute D[3] = D[0]+D[1]+D[2]

on earlier-introduced processor
A1: One possible sequence
A2: Alternative sequence
First load data memory
First load D[0] and D[1] and
locations into register file
add them
R[3] = D[0]
R[4] = D[1]
R[2] = D[2]
(Note arbitrary register locations)

Next, perform the additions

D[3] = R[1]

Digital Design
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Frank Vahid

R[1] = D[0]
R[2] = D[1]
R[1] = R[1] + R[2]
a

Next, load D[2] and add

R[1] = R[3] + R[4]

R[1] = R[1] + R[2]

Finally, store result

R[2] = D[2]
R[1] = R[1] + R[2]

Finally, store result

D[3] = R[1]
12

Number of Cycles

Q: How many cycles are needed to execute six instructions using the
earlier-described processor?

A: Each instruction requires 3

cycles 1 to fetch, 1 to decode,
and 1 to execute
Thus, 6 instr * 3 cycles/instr =
18 cycles

Digital Design
Copyright 2006
Frank Vahid

13

Three-Instruction Programmable Processor

8.3

Instruction Set List of allowable instructions and their

representation in memory, e.g.,
Load instruction0000 r3r2r1r0 d7d6d5d4d3d2d1d0
Store instruction0001 r3r2r1r0 d7d6d5d4d3d2d1d0
Add instruction0010 ra3ra2ra1ra0 rb3rb2rb1rb0 rc3rc2rc1rc0

Desired program
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2}
a

Instruction memory
0: 0000 0000 00000000
1: 0000 0001 00000001
2: 0010 0010 0000 0001
3: 0001 0010 00001001
Digital Design
Copyright 2006
Frank Vahid

opcode operands

Instructions in 0s and 1s
machine code
14

Program for Three-Instruction Processor

Desired program
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2}
Instruction memoryI
0: 0000 0000 00000000
1: 0000 0001 00000001
2: 0010 0010 0000 0001
3: 0001 0010 00001001

Computes
D[9]=D[0]+D[1]
Data memory D

n-bit
2 1
PC

IR
Register file RF

Controller
ALU
s g
i n a sl

Control unit

t o

c o n t r o l t h e

d a t a p a t h

Datapath

Digital Design
Copyright 2006
Frank Vahid

15

Program for Three-Instruction Processor

Another example program in machine code
Compute D[5] = D[5] + D[6] + D[7]

0: 0000 0000 00000101 // RF[0] = D[5]

1: 0000 0001 00000110 // RF[1] = D[6]
2: 0000 0010 00000111 // RF[2] = D[7]
3: 0010 0000 0000 0001 // RF[0] = RF[0] + RF[1]
// which is D[5]+D[6]
4: 0010 0000 0000 0010 // RF[0] = RF[0] + RF[2]
// now D[5]+D[6]+D[7]
5: 0001 0000 00000101 // D[5] = RF[0]

Load instruction0000 r3r2r1r0 d7d6d5d4d3d2d1d0

Store instruction0001 r3r2r1r0 d7d6d5d4d3d2d1d0
Add instruction0010 ra3ra2ra1ra0 rb3rb2rb1rb0
rc3rc2rc1rc0
s g
i n a sl

Digital Design
Copyright 2006
Frank Vahid

t o

c o n t r o l t h e

d a t a p a t h

16

Assembly Code
Machine code (0s and 1s) hard to work with
Assembly code Uses mnemonics
Load instructionMOV Ra, d
specifies the operation RF[a]=D[d]. a must be 0,1, ..., or 15so R0
means RF[0], R1 means RF[1], etc. d must be 0, 1, ..., 255

Store instructionMOV d, Ra
specifies the operation D[d]=RF[a]

Add instructionADD Ra, Rb, Rc

specifies the operation RF[a]=RF[b]+RF[c]
Desired program
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]

0: 0000 0000 00000000

1: 0000 0001 00000001
2: 0010 0010 0000 0001
3: 0001 0010 00001001

machine code

Digital Design
Copyright 2006
Frank Vahid

0: MOV R0, 0
1: MOV R1, 1
2: ADD R2, R0, R1
3: MOV 9, R2
assembly code
17

Control-Unit and Datapath for Three-Instruction

Processor
To design the processor, we can begin with a high-level state machine
description of the processor's behavior
Init
PC=0

Fetch

IR=I[PC]
PC=PC+1

Decode
op=0000

Load
RF[ra]=D[d]

Digital Design
Copyright 2006
Frank Vahid

op=0001 op=0010

Store
D[d]=RF[ra]

Add
RF[ra] =
RF[rb]+
RF[rc]
18

Control-Unit and Datapath for Three-Instruction

Processor
Create detailed connections among components
D_addr 8
addr

rd

data

D_rd
D_wr

16
16
PC
clr up
Init

Id

_ r d

R_ d
l

RF_s

P C _ c rl

P C_ n
i c

1
0
16-bit
2x1
16

Decode
op=0000

Load

op=0001

Controller

Add

D[d]=RF[ra]

RF[ra]=D[d]

RF_W_addr
RF_W_wr
RF_Rp_addr
RF_Rp_rd
RF_Rq_addr
RF_Rq_rd

op=0010

Store

RF[ra] =
RF[rb]+
RF[rc]

W_data
W_addr
W_wr
Rp_addr
16x16
Rp_rd
RF
Rq_addr
Rq_rd

4
4
4

16 Rp_data
alu_s0

Control unit

Rq_data
16

16
A

s0

Digital Design
Copyright 2006
Frank Vahid

16

16

IR=I[PC]
PC=PC+1

Fetch

PC=0

IR

addr
rd
256x16
wr
W_data R_data

ALU

B
16

Datapath

19

Control-Unit and Datapath for Three-Instruction

Processor

Convert high-level state machine

description of entire processor to FSM
description of controller that uses
datapath and other components to
achieve same behavior
Init
Init

Fetch
Fetch

PC=0
PC_ clr=1

addr

rd data
16

16
PC
clr up

IR
Id
16

IR=I[PC]PC=PC+1
IR=I[PC]
PC=PC+1
PC_inc=1
I_rd=1
IR_ld=1

D_addr 8
addr
D_rd
rd
256x16
D_wr
wr
W_dataR_data

16
RF_s

_ r d

R_ d
l

P C _ c rl

P C_ n
i c

Decode
Decode
op=0000
op=0000 op=0001
op=0001 op=0010
op=0010

Controller
Load
Load

Store
Store

Add
Add
=
RF[ra]RF[ra]
= RF[rb]+

RF_W_addr 4
RF_W_wr
RF_Rp_addr 4
RF_Rp_rd
RF_Rq_addr 4
RF_Rq_rd

1
0
16-bit
2x1
16

W_data
W_addr
W_wr
Rp_addr
16x16
Rp_rd
RF
Rq_addr
Rq_rd

s t a t e s

E x e c u t e

RF[ra]=D[d]
RF[ra]=D[d]
D_addr=d

D[d]=RF[ra]
D[d]=RF[ra]
D_addr=d

D_rd=1
RF_s=1

D_wr=1
RF_s=X

RF_W_addr=ra
RF_W_wr=1

RF_Rp_addr=ra
RF_Rp_rd=1

Digital Design
Copyright 2006
Frank Vahid

16 Rp_data Rq_data

RF[rc]
RF[rb]+
RF_Rp_addr=rb
RF[rc]
RF_Rp_rd=1

RF_s=0
RF_Rq_addr=rc
RF_Rq _rd=1

alu_s0

16
s0

Control unit

Datapath

16

B
ALU
16

RF_W_addr=ra
RF_W_wr=1
alu_s0=1

20

10

8.4

A Six-Instruction Programmable Processor

Let's add three more instructions:
Load-constant instruction0011 r3r2r1r0 c7c6c5c4c3c2c1c0
MOV Ra, #cspecifies the operation RF[a]=c

Subtract instruction0100 ra3ra2ra1ra0 rb3rb2rb1rb0 rc3rc2rc1rc0

SUB Ra, Rb, Rcspecifies the operation RF[a]=RF[b] RF[c]

Jump-if-zero instruction0101 ra3ra2ra1ra0 o7o6o5o4o3o2o1o0

JMPZ Ra, offsetspecifies the operation PC = PC + offset if RF[a] is 0

Digital Design
Copyright 2006
Frank Vahid

21

Extending the Control-Unit and Datapath

P C_ d
l

P C _ c rl

2: The subtract instruction requires that we

use an ALU capable of subtraction, so we
add another ALU control signal.
3: The jump-if-zero instruction requires that
we be able to detect if a register is zero,
and that we be able to add IR[7..0] to the
PC.
3a: We insert a datapath component to
detect if the register files Rp read port is all
zeros (that component would just be a
NOR gate).
3b: We also upgrade the PC register so it
can be loaded with PC plus IR[7..0]. The
adder used
for this
also subtracts 1 from
Digital
Design
the sum, to
compensate
Copyright
2006 for the fact that the
Fetch state
already
Frank
Vahid added 1 to the PC.

addr

3b
a+b-1

D_addr 8
addr
D_rd
rd
256x16
D_wr
wr
W_data R_data

IR
Id
16

1
8
RF_W_data
1
RF_s1

IR_ld

PC_inc

PC_clr

+
P C_ n
i c

rd data
16

16
PC
ld clr up

_ r d

PC_ld

1: The load constant instruction requires

that the register file be able to load data
from IR[7..0], in addition to data from data
memory or the ALU output. Thus, we widen
the register files multiplexer from 2x1 to
3x1, add another mux control signal, and
also create a new signal coming from the
controller labeled RF_W_data, which will
connect with IR[7..0].

16
2
1
0
s1 16-bit
s0 3x1

I R_ d
l

IR[7..0]
RF_s0

16

Controller

RF_W_addr

RF_Rp_addr

RF_Rq_addr

RF_Rp_zero

3a
=0

alu_s1
alu_s0
2

Control unit
s1
0
0
1

s0
0
1
0

W_data
W_addr
W_wr
Rp_addr
16x16
Rp_rd
RF
Rq_addr
Rq_rd
16 Rp_data

s1
s0
Datapath

ALU operation
pass A through
A+B
A-B

Rq_data

16
A

16

ALU

B
16

22

11

Controller FSM for the Six-Instruction Processor

I_rd=1
PC_inc=1
IR_ld=1

Init
Fetch

PC_clr=1

Decode
op=0010

op=0011

op=0100

Load-

Load

Store

Add

D_addr=d
D_rd=1
RF_s1=0
RF_s0=1
RF_W_addr=ra
RF_W_wr=1

D_addr=d
D_wr=1
RF_s1=X
RF_s0=X
RF_Rp_addr=ra
RF_Rp_rd=1

RF_Rp_addr=rb
RF_Rp_rd=1
RF_s1=0
RF_s0=0
RF_Rq_add=rc
RF_Rq_rd=1
RF_W_addr_ra
RF_W_wr=1
alu_s1=0
alu_s0=1

Subtract

constant

RF_s1=1
RF_s0=0
RF_W_addr=ra
RF_W_wr=1

op=0101

RF_Rp_addr=rb
RF_Rp_rd=1
RF_s1=0
RF_s0=0
RF_Rq_addr=rc
RF_Rq_rd=1
RF_W_addr=ra
RF_W_wr=1
alu_s1=1
alu_s0=0

Jump-if-zero

RF_Rp_addr=ra
RF_Rp_rd=1

RF _ Rp _ z e r o

Jump-ifzero-jmp

PC_ld=1

RF_Rp_zero'

op=0001

RF_Rp_zero

op=0000

RF _ Rp _ z e r o

Digital Design
Copyright 2006
Frank Vahid

23

Program for the Six-Instruction Processor

Example program Count number of non-zero words in D[4] and D[5]
Result will be either 0, 1, or 2
Put result in D[9]
_ r d

MOV R0, #0; // initialize result to 0

MOV R1, #1; // constant 1 for incrementing result
MOV R2, 4; // get data memory location 4
JMPZ R2, lab1; // if zero, skip next instruction
P C_ d
l

P C _ c rl

P C_ n
i c

I R_ d
l

0011 0000 00000000

0011 0001 00000001
0000 0010 00000100
0101 0010 00000010

ADD R0, R0, R1; // not zero, so increment result

lab1:MOV R2, 5; // get data memory location 5
JMPZ R2, lab2; // if zero, skip next instruction
ADD R0, R0, R1; //not zero, so increment result
lab2:MOV 9, R0; // store result in data memory location 9

0010 0000 0000 0001

0000 0010 00000101
0101 0010 00000010
0010 0000 0000 0001
0001 0000 00001001

(a)

(b)

Digital Design
Copyright 2006
Frank Vahid

24

12

Further Extensions to the Programmable

Processor

8.5

Typical processor instruction set will

contain dozens of data movement
(e.g., loads, stores), ALU (e.g., add,
sub), and flow-of-control (e.g., jump)
instructions
Extending the control-unit/datapath follows
similarly to previously-shown extensions

Input/output extensions

256x16 D
addr
rd
wr

Certain memory locations may actually be

external pins

0:
1:
2:
239:
240:

e.g, D[240] may represent 8-bit input I0,

D[255] may represent 8-bit output P7

00..0
00..0

241:

I0
I1

248:

P0

255:

P7

W_data R_data

Digital Design
Copyright 2006
Frank Vahid

25

Program using I/O Extensions Recall Chpt 1

C-Program Example
Programmed Custom designed

Desired motion-at-night detector microprocessor

digital circuit

Microprocessors a
common choice to
implement a digital
system

Easy to program
Cheap (as low as
$1)
Available now

p
o

Digital Design
Copyright 2006
Frank Vahid

I0
I1
I2
I3
I4
I5
I6
I7

P0
P1
P2
P3
P4
P5
P6
P7

void main()
1
a
{
0
while (1) {
1
b
P0 = I0 && !I1;
0
// F = a and !b,
1
F
}
0
}
6:00

7:057:06

9:009:01

time

26

13

Program Using Input/Output Extensions

Underlying assembly code for C expression I0 && !I1.
0: MOV R0, 240 // move D[240], which is the value at pin I0, into R0
1: MOV R1, 241 // move D[241], which is that value at pin I1, into R1
2: NOT R1, R1 // compute !I1, assuming existence of a complement
instruction
3: AND R0, R0, R1 // compute I0 && !I1, assuming an AND instruction
4: MOV 248, R0 // move result to D[248], which is pin P0
256x16 D
addr
rd
wr

void main()
{
while (1) {
P0 = I0 && !I1;
// F = a and !b,
}
}

0:
1:
2:
239:
240:
241:

00..0
00..0

I0
I1

248:

P0

255:

P7

W_data R_data

Digital Design
Copyright 2006
Frank Vahid

27

Chapter Summary
Programmable processors are widely used
Easy availability, short design time

Basic architecture

Datapath with register file and ALU

Control unit with PC, IR, and controller
Memories for instructions and data
Control unit fetches, decodes, and executes

Three-instruction processor with machine-level programs

Extended to six instructions

Real processors have dozens or hundreds of instructions
Extended to access external pins
Modern processors are far more sophisticated

Instructive to see how one general circuit (programmable processor)

can execute variety of behaviors just by programming 0s and 1s into
an instruction memory
Digital Design
Copyright 2006
Frank Vahid

28

14