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Chapter 8:
Programmable Processors
Slides to accompany the textbook Digital Design, First Edition,
by Frank Vahid, John Wiley and Sons Publishers, 2007.
http://www.ddvahid.com
8.1
Introduction
Programmable (general-purpose) processor
Seatbelt
3-tap FIR filter
warning light
program
program
Other
programs
3
2
p
ta
i
s
1
0
2x4
Instruction
memory I
r
Data memory D
x(t)
x(t-1)
x(t-2)
xt0
c0
xt1
c1
xt2
c2
PC
Seatbelt warning
light single-purpose
processor
reg
Register file
RF
Controller
ALU
Control unit
Digital Design
Copyright 2006
Frank Vahid
n-bit
2x1
IR
Datapat
h
General-purpose processor
2
Note: Slides with animation are denoted with a small red "a" near the animated items
8.2
Basic Architecture
Processing generally consists of:
Loading some data
Transforming that data
Storing that data
Data memory D
somehow
connected
to the
outside
world
n-bit
2x1
a
p
ta
i
s
Register file RF
r
ALU
g
Datapath
Digital Design
Copyright 2006
Frank Vahid
Data memory D
Data memory D
n-bit
2x1
n-bit
2x1
n-bit
2x1
a
Digital Design
Copyright 2006
Frank Vahid
Register file RF
Register file RF
Register file RF
ALU
ALU
ALU
ALU operation
Store operation
Load operation
Digital Design
Copyright 2006
Frank Vahid
Data memory D
Data memory D
Data memory D
n-bit
2x1
n-bit
2x1
n-bit
2x1
Register file RF
Register file RF
Register file RF
ALU
ALU
ALU
ALU operation
Store operation
Load operation
Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]
Data memory D
Digital Design
Copyright 2006
Frank Vahid
n-bit
2x1
PC
IR
Register file RF
Controller
ALU
s g
i n a sl
Control unit
t o
c o n t r o l t h e
d a t a p a t h
Datapath
PC
0>1
Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]
Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]
IR
RF[0]=D[0]
PC
IR
RF[0]=D[0]
PC
1
Controller
s g
i n a sl
t o
c o n t r o l t h e
s g
i n a sl
t o
c o n t r o l t h e
d a t a p a t h
Register file RF
R[0]: ?? 99
"load"
s g
i n a sl
(a)
n-bit
2x1
IR
RF[0]=D[0]
Controller
d a t a p a t h
Control unit
Data memory D
D[0]: 99
t o
c o n t r o l t h e
Controller
d a t a p a t h
Control unit
Fetch
ALU
s g
i n a sl
t o
c o n t r o l t h e
d a t a p a t h
(b)
Digital Design
Copyright 2006
Frank Vahid
Datapath
Control unit
Decode
Execute
(c)
PC
1>2
Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]
Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]
IR
RF[1]=D[1}
PC
IR
RF[1]=D[1]
PC
2
Controller
s g
i n a sl
t o
c o n t r o l t h e
d a t a p a t h
Digital Design
Copyright 2006
Frank Vahid
s g
i n a sl
t o
c o n t r o l t h e
d a t a p a t h
Register file RF
R[1]: ?? 102
"load"
s g
i n a sl
Fetch
n-bit
2x1
IR
RF[1]=D[1]
Controller
Control unit
(a)
Data memory D
D[1]: 102
t o
c o n t r o l t h e
d a t a p a t h
Controller
Control unit
ALU
s g
i n a sl
t o
c o n t r o l t h e
d a t a p a t h
(b)
Decode
Datapath
Control unit
Execute
(c)
PC
2>3
Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]
Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]
IR
RF[2]=RF[0]+RF[1]
PC
IR
RF[2]=RF[0]+RF[1]
PC
3
Controller
s g
i n a sl
t o
c o n t r o l t h e
s g
i n a sl
t o
c o n t r o l t h e
d a t a p a t h
Register file RF
R[2]: ?? 201
99
"ALU (add)"
s g
i n a sl
(a)
n-bit
2x1
IR
RF[2]=RF[0]+RF[1]
Controller
d a t a p a t h
Control unit
Data memory D
t o
c o n t r o l t h e
Controller
d a t a p a t h
Fetch
102
201
Control unit
ALU
s g
i n a sl
t o
c o n t r o l t h e
d a t a p a t h
(b)
Digital Design
Copyright 2006
Frank Vahid
Datapath
Control unit
Decode
Execute
(c)
PC
3>4
Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]
Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]
IR
D[9]=RF[2]
PC
IR
D[9]=RF[2]
PC
4
Controller
s g
i n a sl
t o
c o n t r o l t h e
d a t a p a t h
Digital Design
Copyright 2006
Frank Vahid
s g
i n a sl
t o
c o n t r o l t h e
d a t a p a t h
Register file RF
R[2]: 201
"store"
s g
i n a sl
Fetch
n-bit
2x1
IR
D[9]=RF[2]
Controller
Control unit
(a)
Data memory D
D[9]=?? 201
t o
c o n t r o l t h e
d a t a p a t h
Controller
Control unit
ALU
s g
i n a sl
t o
c o n t r o l t h e
d a t a p a t h
(b)
Decode
Datapath
Control unit
Execute
(c)
10
Init
Fetch
PC=0
IR=I[PC]
PC=PC+1
Decode
Instruction memory I
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2]
Execute
Data memory D
s g
i n a sl
t o
c o n t r o l t h e
d a t a p a t h
n-bit
2x1
Controller
s g
i n a sl
t o
c o n t r o l t h e
d a t a p a t h
PC
IR
s g
i n a sl
t o
c o n t r o l t h e
Register file RF
d a t a p a t h
s g
i n a sl
t o
c o n t r o l t h e
d a t a p a t h
Controller
Digital Design
Copyright 2006
Frank Vahid
ALU
11
Datapath
Control unit
D[3] = R[1]
Digital Design
Copyright 2006
Frank Vahid
R[1] = D[0]
R[2] = D[1]
R[1] = R[1] + R[2]
a
R[2] = D[2]
R[1] = R[1] + R[2]
D[3] = R[1]
12
Number of Cycles
Q: How many cycles are needed to execute six instructions using the
earlier-described processor?
Digital Design
Copyright 2006
Frank Vahid
13
8.3
Desired program
0: RF[0]=D[0]
1: RF[1]=D[1]
2: RF[2]=RF[0]+RF[1]
3: D[9]=RF[2}
a
Instruction memory
0: 0000 0000 00000000
1: 0000 0001 00000001
2: 0010 0010 0000 0001
3: 0001 0010 00001001
Digital Design
Copyright 2006
Frank Vahid
opcode operands
Instructions in 0s and 1s
machine code
14
Computes
D[9]=D[0]+D[1]
Data memory D
n-bit
2 1
PC
IR
Register file RF
Controller
ALU
s g
i n a sl
Control unit
t o
c o n t r o l t h e
d a t a p a t h
Datapath
Digital Design
Copyright 2006
Frank Vahid
15
Digital Design
Copyright 2006
Frank Vahid
t o
c o n t r o l t h e
d a t a p a t h
16
Assembly Code
Machine code (0s and 1s) hard to work with
Assembly code Uses mnemonics
Load instructionMOV Ra, d
specifies the operation RF[a]=D[d]. a must be 0,1, ..., or 15so R0
means RF[0], R1 means RF[1], etc. d must be 0, 1, ..., 255
Store instructionMOV d, Ra
specifies the operation D[d]=RF[a]
machine code
Digital Design
Copyright 2006
Frank Vahid
0: MOV R0, 0
1: MOV R1, 1
2: ADD R2, R0, R1
3: MOV 9, R2
assembly code
17
Fetch
IR=I[PC]
PC=PC+1
Decode
op=0000
Load
RF[ra]=D[d]
Digital Design
Copyright 2006
Frank Vahid
op=0001 op=0010
Store
D[d]=RF[ra]
Add
RF[ra] =
RF[rb]+
RF[rc]
18
rd
data
D_rd
D_wr
16
16
PC
clr up
Init
Id
_ r d
R_ d
l
RF_s
P C _ c rl
P C_ n
i c
1
0
16-bit
2x1
16
Decode
op=0000
Load
op=0001
Controller
Add
D[d]=RF[ra]
RF[ra]=D[d]
RF_W_addr
RF_W_wr
RF_Rp_addr
RF_Rp_rd
RF_Rq_addr
RF_Rq_rd
op=0010
Store
RF[ra] =
RF[rb]+
RF[rc]
W_data
W_addr
W_wr
Rp_addr
16x16
Rp_rd
RF
Rq_addr
Rq_rd
4
4
4
16 Rp_data
alu_s0
Control unit
Rq_data
16
16
A
s0
Digital Design
Copyright 2006
Frank Vahid
16
16
IR=I[PC]
PC=PC+1
Fetch
PC=0
IR
addr
rd
256x16
wr
W_data R_data
ALU
B
16
Datapath
19
Fetch
Fetch
PC=0
PC_ clr=1
addr
rd data
16
16
PC
clr up
IR
Id
16
IR=I[PC]PC=PC+1
IR=I[PC]
PC=PC+1
PC_inc=1
I_rd=1
IR_ld=1
D_addr 8
addr
D_rd
rd
256x16
D_wr
wr
W_dataR_data
16
RF_s
_ r d
R_ d
l
P C _ c rl
P C_ n
i c
Decode
Decode
op=0000
op=0000 op=0001
op=0001 op=0010
op=0010
Controller
Load
Load
Store
Store
Add
Add
=
RF[ra]RF[ra]
= RF[rb]+
RF_W_addr 4
RF_W_wr
RF_Rp_addr 4
RF_Rp_rd
RF_Rq_addr 4
RF_Rq_rd
1
0
16-bit
2x1
16
W_data
W_addr
W_wr
Rp_addr
16x16
Rp_rd
RF
Rq_addr
Rq_rd
s t a t e s
E x e c u t e
RF[ra]=D[d]
RF[ra]=D[d]
D_addr=d
D[d]=RF[ra]
D[d]=RF[ra]
D_addr=d
D_rd=1
RF_s=1
D_wr=1
RF_s=X
RF_W_addr=ra
RF_W_wr=1
RF_Rp_addr=ra
RF_Rp_rd=1
Digital Design
Copyright 2006
Frank Vahid
16 Rp_data Rq_data
RF[rc]
RF[rb]+
RF_Rp_addr=rb
RF[rc]
RF_Rp_rd=1
RF_s=0
RF_Rq_addr=rc
RF_Rq _rd=1
alu_s0
16
s0
Control unit
Datapath
16
B
ALU
16
RF_W_addr=ra
RF_W_wr=1
alu_s0=1
20
10
8.4
Digital Design
Copyright 2006
Frank Vahid
21
P C_ d
l
P C _ c rl
addr
3b
a+b-1
D_addr 8
addr
D_rd
rd
256x16
D_wr
wr
W_data R_data
IR
Id
16
1
8
RF_W_data
1
RF_s1
IR_ld
PC_inc
PC_clr
+
P C_ n
i c
rd data
16
16
PC
ld clr up
_ r d
PC_ld
16
2
1
0
s1 16-bit
s0 3x1
I R_ d
l
IR[7..0]
RF_s0
16
Controller
RF_W_addr
RF_Rp_addr
RF_Rq_addr
RF_Rp_zero
3a
=0
alu_s1
alu_s0
2
Control unit
s1
0
0
1
s0
0
1
0
W_data
W_addr
W_wr
Rp_addr
16x16
Rp_rd
RF
Rq_addr
Rq_rd
16 Rp_data
s1
s0
Datapath
ALU operation
pass A through
A+B
A-B
Rq_data
16
A
16
ALU
B
16
22
11
Init
Fetch
PC_clr=1
Decode
op=0010
op=0011
op=0100
Load-
Load
Store
Add
D_addr=d
D_rd=1
RF_s1=0
RF_s0=1
RF_W_addr=ra
RF_W_wr=1
D_addr=d
D_wr=1
RF_s1=X
RF_s0=X
RF_Rp_addr=ra
RF_Rp_rd=1
RF_Rp_addr=rb
RF_Rp_rd=1
RF_s1=0
RF_s0=0
RF_Rq_add=rc
RF_Rq_rd=1
RF_W_addr_ra
RF_W_wr=1
alu_s1=0
alu_s0=1
Subtract
constant
RF_s1=1
RF_s0=0
RF_W_addr=ra
RF_W_wr=1
op=0101
RF_Rp_addr=rb
RF_Rp_rd=1
RF_s1=0
RF_s0=0
RF_Rq_addr=rc
RF_Rq_rd=1
RF_W_addr=ra
RF_W_wr=1
alu_s1=1
alu_s0=0
Jump-if-zero
RF_Rp_addr=ra
RF_Rp_rd=1
RF _ Rp _ z e r o
Jump-ifzero-jmp
PC_ld=1
RF_Rp_zero'
op=0001
RF_Rp_zero
op=0000
RF _ Rp _ z e r o
Digital Design
Copyright 2006
Frank Vahid
23
P C _ c rl
P C_ n
i c
I R_ d
l
(a)
(b)
Digital Design
Copyright 2006
Frank Vahid
24
12
8.5
Input/output extensions
256x16 D
addr
rd
wr
0:
1:
2:
239:
240:
00..0
00..0
241:
I0
I1
248:
P0
255:
P7
W_data R_data
Digital Design
Copyright 2006
Frank Vahid
25
Microprocessors a
common choice to
implement a digital
system
Easy to program
Cheap (as low as
$1)
Available now
p
o
Digital Design
Copyright 2006
Frank Vahid
I0
I1
I2
I3
I4
I5
I6
I7
P0
P1
P2
P3
P4
P5
P6
P7
void main()
1
a
{
0
while (1) {
1
b
P0 = I0 && !I1;
0
// F = a and !b,
1
F
}
0
}
6:00
7:057:06
9:009:01
time
26
13
void main()
{
while (1) {
P0 = I0 && !I1;
// F = a and !b,
}
}
0:
1:
2:
239:
240:
241:
00..0
00..0
I0
I1
248:
P0
255:
P7
W_data R_data
Digital Design
Copyright 2006
Frank Vahid
27
Chapter Summary
Programmable processors are widely used
Easy availability, short design time
Basic architecture
28
14