Tanner EDA Tools

TANNER ('$TOOLS

Tanner EDA Tools

Tanner EDA Tools

INDEX
S.No.

TITLE

Page No.

1.

Integrated Circuit Layout

2.

Integrated Circuit Design

3.

Tanner IC Work Flow

4.

S-EDIT

11

5.

T-SPICE

23

6.

W-EDIT

25

7.

L-EDIT

28

8.

LVS (Layout Vs Schematic)

43

Tanner EDA Tools

Tanner EDA Tools

Integrated Circuit Layout

Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands
of transistor-based circuits into a single chip. VLSI began in the 1970s when complex semiconductor and
communication technologies were being developed. The microprocessor is a VLSI device. The term is no
longer as common as it once was, as chips have increased in complexity into the hundreds of millions of
transistors.

Integrated circuit layout, also known IC layout, IC mask layout, or mask design, is the representation of
an integrated circuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, or
semiconductor layers that make up the components of the integrated circuit.
When using a standard process - where the interaction of the many chemical, thermal, and photographic
variables are known and carefully controlled - the behavior of the final integrated circuit depends largely on
the positions and interconnections of the geometric shapes. A layout engineer's job is to place and connect
all the components that make up a chip so that they meet all criteria. Typical goals are performance, size,
and manufacturability.
The layout must pass a series of checks in a process known as verification. The two most common checks in
the verification process are Design Rule Checking (DRC), and Layout Versus Schematic (LVS). When all
verification is complete the data is translated into an industry standard format, typically GDSII, and sent to a
semiconductor foundry. The process of sending this data to the foundry is called tapeout due to the fact the
data used to be shipped out on a magnetic tape. The foundry converts the data into another format and uses
it to generate the photomasks used in a photolithographic process of semiconductor device fabrication.
In the earlier, simpler, days of IC design, layout was done by hand using opaque tapes and films, much like
the early days of PCB design. Modern IC Layout is done with the aid of IC layout editor software, or even
automatically using EDA tools, including place and route tools or schematic driven layout tools. The
manual operation of choosing and positioning the geometric shapes is informally known as "polygon
pushing".

Tanner EDA Tools

Tanner EDA Tools

Integrated circuit design

Integrated circuit design, or IC design, is a subset of electrical engineering, encompassing the particular
logic and circuit design techniques required to design integrated circuits, or ICs. ICs consist of miniaturized
electronic components built into an electrical network on a monolithic semiconductor substrate by
photolithography.
IC design can be divided into the broad categories of digital and analog IC design. Digital IC design is used
to produce components such as microprocessors, FPGAs, memories (RAM, ROM, and flash) and digital
ASICs. Digital design focuses on logical correctness, maximizing circuit density, and placing circuits so
that clock and timing signals are routed efficiently. Analog IC design also has specializations in power IC
design and RF IC design. Analog IC design is used in the design of op-amps, linear regulators, phase locked
loops, oscillators and active filters. Analog design is more concerned with the physics of the semiconductor
devices such as gain, matching, power dissipation, and resistance. Fidelity of analog signal amplification
and filtering is usually critical and as a result, analog ICs use larger area active devices than digital designs
and are usually less dense in circuitry.
Modern ICs are enormously complicated. A large chip, as of 2006, may well have more transistors than
there are people on Earth. The rules for what can and cannot be manufactured are also extremely complex.
An IC process as of 2006 may well have more than 600 rules. Furthermore, since the manufacturing process
itself is not completely predictable, designers must account for its statistical nature. The complexity of
modern IC design, as well as market pressure to produce designs rapidly, has led to the extensive use of
automated design tools in the IC design process. In short, the design of an IC using EDA software is the
design, test, and verification of the instructions that the IC is to carry out.

Fundamentals
Integrated circuit design involves the creation of electronic components, such as transistors, resistors,
capacitors and the metallic interconnect of these components onto a piece of semiconductor, typically
silicon. A method to isolate the individual components formed in the substrate is necessary since the
substrate silicon is conductive and often forms an active region of the individual components. The two
common methods are p-n junction isolation and dielectric isolation. Attention must be given to power
dissipation of transistors and interconnect resistances and current density of the interconnect, contacts and
vias since ICs contain very tiny devices compared to discrete components, where such concerns are less of
an issue. Electromigration in metallic interconnect and ESD damage to the tiny components are also of
concern. Finally, the physical layout of certain circuit subblocks is typically critical, in order to achieve the
desired speed of operation, to segregate noisy portions of an IC from quiet portions, to balance the effects of
heat generation across the IC, or to facilitate the placement of connections to circuitry outside the IC.

Design steps
A typical IC design cycle involves several steps:
1.
2.
3.
4.
5.

Feasibility study and die size estimate

Functional verification
Circuit/RTL design
Circuit/RTL simulation Logic simulation
Floorplanning
4

Tanner EDA Tools

Tanner EDA Tools

5
6. Design review
7. Layout
8. Layout verification
9. Static timing analysis
10. Layout review
11. Design For Test and Automatic test pattern generation
12. Design for manufacturability (IC)
13. Mask data preparation
14. Wafer fabrication
15. Die test
16. Packaging
17. Post silicon validation
18. Device characterization
19. Tweak (if necessary)
20. Datasheet generation Portable Document Format
21. Ramp up
22. Production
23. Yield Analysis / Warranty Analysis Reliability (semiconductor)
24. Failure analysis on any returns
25. plan for next generation chip using production information if possible

Digital design
Roughly speaking, digital IC design can be divided into three parts

ESL design: This step creates the user functional specification. The user may use a variety of
languages and tools to create this description. Examples include a C/C++ model, SystemC,
SystemVerilog Transaction Level Models.
RTL design: This step converts the user specification (what the user wants the chip to do) into a
register transfer level (RTL) description. The RTL describes the exact behavior of the digital circuits
on the chip, as well as the interconnections to inputs and outputs.
Physical design: This step takes the RTL, and a library of available logic gates, and creates a chip
design. This involves figuring out which gates to use, defining places for them, and wiring them
together.

Note that the second step, RTL design, is responsible for the chip doing the right thing. The third step,
physical design, does not affect the functionality at all (if done correctly) but determines how fast the chip
operates and how much it costs.

RTL design
This is the hardest part, and the domain of functional verification. The spec may have some terse
description, such as encodes in the MP3 format or implements IEEE floating-point arithmetic. Each of these
innocent looking statements expands to hundreds of pages of text, and thousands of lines of computer code.
It is extremely difficult to verify that the RTL will do the right thing in all the possible cases that the user
may throw at it. Many techniques are used, none of them perfect but all of them useful extensive logic
simulation, formal methods, hardware emulation, lint-like code checking, and so on.

Tanner EDA Tools

Tanner EDA Tools

A tiny error here can make the whole chip useless, or worse. The famous Pentium FDIV bug caused the
results of a division to be wrong by at most 61 parts per million, in cases that occurred very infrequently. No
one even noticed it until the chip had been in production for months. Yet Intel was forced to offer to replace,
for free, every chip sold until they could fix the bug, at a cost of $475 million (US).

Physical design
Here are the main steps of physical design. In practice there is not a straightforward progression considerable iteration is required to ensure all objectives are met simultaneously. This is a difficult problem
in its own right, called design closure.

Floorplanning: The RTL of the chip is assigned to gross regions of the chip, input/output (I/O) pins
are assigned and large objects (arrays, cores, etc.) are placed.
Logic synthesis: The RTL is mapped into a gate-level netlist in the target technology of the chip.
Placement: The gates in the netlist are assigned to nonoverlapping locations on the die area.
Logic/placement refinement: Iterative logical and placement transformations to close performance
and power constraints.
Clock insertion: Balanced buffered clock trees are introduced into the design.
Routing: The wires that connect the gates in the netlist are added.
Postwiring optimization: Remaining performance (Timing Closure), noise (Signal Integrity), and
yield (Design for Manufacturability) violations are removed.
Design for manufacturability: The design is modified, where possible, to make it as easy and
efficient as possible to produce. This is achieved by adding extra vias or adding dummy
metal/diffusion/poly layers wherever possible while complying to the design rules set by the
foundry.
Final checking: Since errors are expensive, time consuming and hard to spot, extensive error
checking is the rule, making sure the mapping to logic was done correctly, and checking that the
manufacturing rules were followed faithfully.
Tapeout and mask generation: the design data is turned into photomasks in mask data preparation.

Tanner EDA Tools

Tanner EDA Tools

Process corners
Process corners provide digital designers the ability to simulate the circuit while accounting for variations in
the technology process.

A simple CMOS Operational Amplifier Layout

Analog design
Before the advent of the microprocessor and software based design tools, analog ICs were designed using
hand calculations. These ICs were basic circuits, op-amps are one example, usually involving no more than
ten transistors and few connections. An iterative trial-and-error process and "overengineering" of device
size was often necessary to achieve a manufacturable IC. Reuse of proven designs allowed progressively
more complicated ICs to be built upon prior knowledge. When inexpensive computer processing became
available in the 1970s, computer programs were written to simulate circuit designs with greater accuracy
than practical by hand calculation. The first circuit simulator for analog ICs was called SPICE (Simulation
Program with Integrated Circuits Emphasis). Computerized circuit simulation tools enable greater IC design
complexity than hand calculations can achieve, making the design of analog ASICs practical. The
computerized circuit simulators also enable mistakes to be found early in the design cycle before a physical
device is fabricated. Additionally, a computerized circuit simulator can implement more sophisticated
device models and circuit analysis too tedious for hand calculations, permitting Monte Carlo analysis and
process sensitivity analysis to be practical. The effects of parameters such as temperature variation, doping
concentration variation and statistical process variations can be simulated easily to determine if an IC design
is manufacturable. Overall, computerized circuit simulation enables a higher degree of confidence that the
circuit will work as expected upon manufacture.

Tanner EDA Tools

Tanner EDA Tools

Coping with variability

A challenge most critical to analog IC design involves the variability of the individual devices built on the
semiconductor chip. Unlike board-level circuit design which permits the designer to select devices that have
each been tested and binned according to value, the device values on an IC can vary widely which are
uncontrollable by the designer. For example, some IC resistors can vary 20% and of an integrated BJT
can vary from 20 to 100. To add to the design challenge, device properties often vary between each
processed semiconductor wafer. Device properties can even vary significantly across each individual IC due
to doping gradients. The underlying cause of this variability is that many semiconductor devices are highly
sensitive to uncontrollable random variances in the process. Slight changes to the amount of diffusion time,
uneven doping levels, etc. can have large effects on device properties.
The design techniques necessary to reduce the effects of the device variation are:

Using the ratios of resistors, which do match closely, rather than absolute resistor value.
Using devices with matched geometrical shapes so they have matched variations.
Making devices large so that statistical variations becomes an insignificant fraction of the overall
device property.
Segmenting large devices, such as resistors, into parts and interweaving them to cancel variations.
Using common centroid device layout to cancel variations in devices which must match closely
(such as the transistor differential pair of an op amp).

Fortunately for IC design, the absolute values of the devices are less critical than the identical matching of
device performance. However, this fabrication variability forces certain design techniques and prevents the
use of other design techniques familiar to the board-level designer.

Tanner EDA Tools

Tanner EDA Tools

Tanner IC Work Flow

Tanner Tools are fully-integrated solutions consisting of tools for schematic entry, circuit simulation,
waveform probing, full-custom layout editing, placement and routing, netlist extraction, LVS and design
rule checking (DRC) verification.

Tanner EDA Tools

Tanner EDA Tools

10

Introduction
This document gives a rough overview of how to design & simulate things with Tanner Tools. There are
four basic steps:
1.
2.
3.
4.

Design the schematic in S-EDIT.

Simulate the schematic to make sure it behaves as you expect using T-SPICE.
Layout the schematic in L-EDIT.
Perform an LVS (Layout VS Schematic) to make sure your layout is functionally the same as the
schematic you designed in S-EDIT.
5. Simulate the layout using T-SPICE with a high-level spice model, making sure L-EDIT generates
the parasitic capacitances so they are included in the simulation.

What follows is a brief overview of the steps.

10

Tanner EDA Tools

Tanner EDA Tools

11

S-EDIT
Simulating Schematics in S-EDIT
Run Tanner Tools S-Edit, Tanners schematic entry program.
File -> new design

Type the design name and locate it in a folder and click ok11

Tanner EDA Tools

Tanner EDA Tools

12

Add libraries from libraries toolbarAdd (all.tanner), it includes complete library components.
This all folder is located at:
My Documents\Tanner EDA\Tanner Tools v13.0\Libraries\All

12

Tanner EDA Tools

Tanner EDA Tools

13

Now we need to create a cell:

13

Tanner EDA Tools

Tanner EDA Tools

14
Give a name to cell0: (Inverter)

Scroll mouse for zoom in and zoom out14

Tanner EDA Tools

Tanner EDA Tools

15
Click on devices for CMOS Inverter designSelect pmos and click on Instance

With mouse device will attached, place it by single click, right click on workspace or done to go back

15

Tanner EDA Tools

Tanner EDA Tools

16
Similarly we can paste Nmos ->

Properties of devices can be changed from properties toolbar, it is customizable

Select misc from library toolbar, and paste Vdd and Gnd
16

Tanner EDA Tools

Tanner EDA Tools

17
Select SPICE_Elements then voltagesource, Type of voltage can be changed by instance cell, as follows

Paste one DC and one Pulse voltage source at workspace

Now connections can be made from wire selection

17

Tanner EDA Tools

Tanner EDA Tools

18

Just click on open node of device and wire the nodes accordingly

Now we need to add Input port and Output port

18

Tanner EDA Tools

Tanner EDA Tools

19

Now connect input, output port accordingly

19

Tanner EDA Tools

Tanner EDA Tools

20
Now include SPICE_commands (printvoltage) from library &
Connect this to input and output port to check waveform

We need to include model file (hp05.md) with SPICE_commands -> include

Hp05.md file location is inserted at value
C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.0\L-Edit and
LVS\LVS\SPR_Core\hp05.md

20

Tanner EDA Tools

Tanner EDA Tools

21
Paste this include command anywhere at workspace

To move a component anywhere at workspace, click on component, then by pressing scroll button, it can be
moved anywhere.
Now circuit is complete. Just save it.
For simulation of design go to Setup-> spice_simulation

Select Spice options (analysis) then define time parameter

21

Tanner EDA Tools

Tanner EDA Tools

22

Click OK, then Select Tools-> start simulation

22

Tanner EDA Tools

Tanner EDA Tools

23

T-SPICE
It will automatically invoke T-Spice software

Then simulation -> run simulation

A Netlist file will be open as follows

Spice commands can be inserted from Insert Command Button

23

Tanner EDA Tools

Tanner EDA Tools

24

24

Tanner EDA Tools

Tanner EDA Tools

25

W-EDIT
Waveform can be checked Using W-Edit; It will automatically invoked at the time of running T-spice
Waveform:

Input and outputs are overlapped in this waveform, we can separate it by Expand chart

25

Tanner EDA Tools

Tanner EDA Tools

26
Now check the waveform

After selecting output, FFT can be seen from FFT Button

26

Tanner EDA Tools

Tanner EDA Tools

27

27

Tanner EDA Tools

Tanner EDA Tools

28

L-EDIT
CMOS Inverter Structure: -

Double click on L-Edit;

File -> new

Now copy TDB (Tanner Data Base) file from browse

28

Tanner EDA Tools

Tanner EDA Tools

29
Path for TDB File
C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.0\L-Edit and
LVS\Tech\Mosis\morbn20.tdb
And Click OK

Goto cell -> new

Name the cell->

29

Tanner EDA Tools

Tanner EDA Tools

30

Grids spacing can be minimized or maximized using or + sign

To change the technology Goto setup-> Design

Select Lambda or microns accordingly and click ok

30

Tanner EDA Tools

Tanner EDA Tools

31
Before designing layout we need to remember following equations
N Diffusion = N select and Active (1)
P Diffusion = P select and Active - (2)
From layer palette, we can select layer then for drawing layer we need to switch at Drawing boxes as
follows

Now we can start layout designing

We are Taking Example of CMOS Layout design
Background of L-Edit is P-Substrate by default
We need to design PMOS, First draw active

31

Tanner EDA Tools

Tanner EDA Tools

32
Now draw P select over Active with keeping in mind Lambda based design rules

Now draw poly over it accordingly

Now draw metal1 to design Contact

Now draw Active Contact for Active region

32

Tanner EDA Tools

Tanner EDA Tools

33

We have designed source, gate and drain

Now we need to put this in N-Well

We can perform DRC (Design Rule Check) at every stage

33

Tanner EDA Tools

Tanner EDA Tools

34
If we are violating any Design rule then it will be shown in Error verification navigator

On pointing any error, it will be shown in corresponding layout, as follows

It is called lens, now we need to edit N-well

We can check DRC at every stage

34

Tanner EDA Tools

Tanner EDA Tools

35
Now we need to draw Body terminal, Gate contact

After designing Body terminal (n select+ active+metal1+active contact), we need to design Gate contact
In case of Poly Layer, we need to draw Poly contact

To define port, go to (A)

35

Tanner EDA Tools

Tanner EDA Tools

36

Type the name of port;

36

Tanner EDA Tools

Tanner EDA Tools

37

Similarly we can design N MOS; and after connecting these two, CMOS layout will look like as follows

Now we can extract netlist by doing some settings

37

Tanner EDA Tools

Tanner EDA Tools

38

38

Tanner EDA Tools

Tanner EDA Tools

39
Now select Extract standard rule set, and click on pencil

Now we need to include Extract file, and Spice output file at desired location
Location for .ext file is
C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.0\L-Edit and
LVS\Tech\Mosis\morbn20.ext

39

Tanner EDA Tools

Tanner EDA Tools

40
Define location for output files

In output, select Names (writing nodes)

40

Tanner EDA Tools

Tanner EDA Tools

41
Click ok, now go to extract button

Click on extract, An spice file will open as follows

We can open this spice file in T-Spice and can perform desired analysis
We need to include hp05.md file for analysis

41

Tanner EDA Tools

Tanner EDA Tools

42

We need to insert some spice commands to perform transient analysis :

VVoltageSource_1 Vdd Gnd DC 5
VVoltageSource_2 vin Gnd PULSE(0 5 0 5n 5n 95n 200n)
.PRINT TRAN V(vin)
.PRINT TRAN V(vout)
.tran 1ns 500ns

After saving spice file, we can simulate it, W-Edit will invoked and we can check the response:

42

Tanner EDA Tools

Tanner EDA Tools

43

LVS
(Layout Vs Schematic)
We got two output files (one from S-Edit and second from L-Edit), Now we can compare results by using
LVS
Double click on LVS, and file -> new &
Select file type-> LVS setup, then ok

We need to browse spice netlist files for layout netlist and Schematic netlist
43

Tanner EDA Tools

Tanner EDA Tools

44

After including these files, we need to run verification as follows &

Results can be checked from Verification Window.

Both netlists are equal.

44

Tanner EDA Tools