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1. General description
The HEF40098B is a hex inverting buffer with 3-state outputs. The 3-state outputs are
controlled by two active LOW enable inputs (1OE and 2OE). A HIGH on 1OE causes four
of the six active LOW buffer elements (1Y0 to 1Y3) to assume a high-impedance or
OFF-state regardless of the other input conditions and a HIGH on 2OE causes the outputs
of the remaining two buffer elements (2Y0 and 2Y1) to assume a high-impedance or
OFF-state regardless of the other input conditions.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
3. Ordering information
Table 1.
Ordering information
All types operate from 40 C to +85 C
Type number
HEF40098BT
Package
Name
Description
Version
SO16
SOT109-1
HEF40098B
NXP Semiconductors
4. Functional diagram
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Fig 1.
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Functional diagram
Fig 2.
2(
DDH
Logic diagram
5. Pinning information
5.1 Pinning
+()%
2(
9''
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Fig 3.
Pin configuration
HEF40098B
2 of 12
HEF40098B
NXP Semiconductors
Pin description
Symbol
Pin
Description
1OE
2, 4, 6, 10
buffer input
3, 5, 7, 9
VSS
supply voltage
2Y0, 2Y1
13, 11
2A0, 2A1
14, 12
buffer input
2OE
15
VDD
16
supply voltage
6. Functional description
Table 3.
Function table[1]
Inputs
Output
nAn
nOE
nYn
[1]
H = HIGH voltage level; L = LOW voltage level; X = dont care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
supply voltage
IIK
VI
input voltage
IOK
II/O
input/output current
Conditions
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
Min
Max
Unit
0.5
+18
V
mA
10
0.5
VDD + 0.5
10
mA
10
mA
IDD
supply current
50
mA
Tstg
storage temperature
65
+150
Tamb
ambient temperature
40
+85
Ptot
500
mW
100
mW
Tamb = 40 to +85 C
SO16 package
P
[1]
power dissipation
[1]
HEF40098B
3 of 12
HEF40098B
NXP Semiconductors
Symbol
Parameter
VDD
VI
Conditions
Min
Typ
Max
Unit
supply voltage
15
input voltage
VDD
Tamb
ambient temperature
in free air
40
+85
t/V
VDD = 5 V
3.75
ns/V
VDD = 10 V
0.5
ns/V
VDD = 15 V
0.08
ns/V
9. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Symbol Parameter
VIH
VIL
VOH
VOL
IOH
IOL
Conditions
VDD
IO < 1 A
Max
Min
Max
Min
Max
5V
3.5
3.5
3.5
10 V
7.0
7.0
7.0
15 V
11.0
11.0
11.0
5V
1.5
1.5
1.5
10 V
3.0
3.0
3.0
15 V
4.0
4.0
4.0
5V
4.95
4.95
4.95
10 V
9.95
9.95
9.95
15 V
14.95
14.95
14.95
5V
0.05
0.05
0.05
10 V
0.05
0.05
0.05
15 V
0.05
0.05
0.05
5V
3.8
3.2
2.5
mA
VO = 4.6 V
5V
1.2
1.0
0.8
mA
VO = 9.5 V
10 V
3.8
3.2
2.5
mA
VO = 13.5 V
15 V
12.0
10.0
8.0
mA
VO = 0.4 V;
4.75 V
3.5
2.9
2.3
mA
VO = 0.5 V;
10 V
12.0
10.0
8.0
mA
IO < 1 A
IO < 1 A
VO = 1.5 V;
15 V
24.0
20.0
16.0
mA
II
VI = 0 V or 15 V
15 V
0.3
0.3
1.0
IDD
supply current
IO = 0 A
5V
30
10 V
60
15 V
16
16
120
15 V
1.6
1.6
12.0
7.5
pF
IOZ
CI
input capacitance
HEF40098B
4 of 12
HEF40098B
NXP Semiconductors
Parameter
Conditions
VDD
Extrapolation formula[1]
tPHL
HIGH to LOW
propagation delay
nAn to nYn;
see Figure 4
5V
tPLH
tTHL
nAn to nYn;
see Figure 4
see Figure 4
tTLH
HiGH to OFF-state
propagation delay
tPHZ
tPLZ
tPZH
see Figure 4
nOE, to nYn;
see Figure 5
LOW to OFF-state
propagation delay
nOE, to nYn;
see Figure 5
OFF-state to HIGH
propagation delay
nOE, to nYn;
see Figure 5
OFF-state to LOW
propagation delay
tPZL
[1]
LOW to HIGH
propagation delay
nOE, to nYn;
see Figure 5
Min
Typ
Max
Unit
70 ns + (0.20 ns/pF)CL
80
160
ns
10 V
31 ns + (0.08 ns/pF)CL
35
70
ns
15 V
22 ns + (0.06 ns/pF)CL
25
50
ns
5V
50 ns + (0.30 ns/pF)CL
65
130
ns
10 V
24 ns + (0.13 ns/pF)CL
30
60
ns
15 V
23 ns + (0.05 ns/pF)CL
25
50
ns
5V
15 ns + (0.30 ns/pF)CL
30
60
ns
10 V
10 ns + (0.11 ns/pF)CL
15
30
ns
15 V
7 ns + (0.07 ns/pF)CL
10
20
ns
5V
10 ns + (0.50 ns/pF)CL
35
70
ns
10 V
8 ns + (0.24 ns/pF)CL
20
40
ns
15 V
6 ns + (0.18 ns/pF)CL
15
30
ns
5V
45
85
ns
10 V
35
65
ns
15 V
30
60
ns
5V
65
135
ns
10 V
40
80
ns
15 V
35
70
ns
5V
70
140
ns
10 V
35
75
ns
15 V
30
65
ns
5V
90
185
ns
10 V
40
85
ns
15 V
35
70
ns
The typical value of the propagation delay and transition times are calculated from the extrapolation formula as shown (CL in pF).
Table 8.
Dynamic power dissipation PD
PD can be calculated (in W) from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol
PD
Parameter
dynamic power
dissipation
VDD
where:
5V
10 V
15 V
HEF40098B
5 of 12
HEF40098B
NXP Semiconductors
11. AC waveforms
9,
LQSXW
90
9
W3+/
92+
W3/+
90
RXWSXW
92/
W7+/
W7/+
DDL
Measurement points are given in Table 9, VOL and VOH are typical output voltage levels that occur with the output load.
Fig 4.
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9<
9;
966
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W3=+
9<
RXWSXW
+,*+WR2))
2))WR+,*+
9;
966
RXWSXWVRQ
RXWSXWVRII
RXWSXWVRQ
DDJ
Measurement points are given in Table 9, VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5.
Table 9.
Measurement points
Supply voltage
Input
Output
VDD
VM
VM
VX
VY
5 V to 15 V
0.5VDD
0.5VDD
0.1VDD
0.9VDD
HEF40098B
6 of 12
HEF40098B
NXP Semiconductors
W:
9,
QHJDWLYH
SXOVH
90
90
9
WI
WU
WU
WI
9,
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SXOVH
90
90
9
W:
DDM
a. Input waveform
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b. Test circuit
Test and measurement data is given in Table 10.
Definitions test circuit:
DUT = Device Under Test.
RL = Load resistance;
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 6.
Table 10.
Test data
Supply voltage
Input
VDD
VI
tr, tf
CL
RL
tPLH, tPHL
tPLZ, tPZL
tPHZ, tPZH
5 V to 15 V
VDD
20 ns
50 pF
1 k
open
VDD
GND
HEF40098B
Load
VEXT
7 of 12
HEF40098B
NXP Semiconductors
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HEF40098B
8 of 12
HEF40098B
NXP Semiconductors
Revision history
Document ID
Release date
Change notice
Supersedes
HEF40098B v.9
20160318
HEF40098B v.8
Modifications:
HEF40098B v.8
Modifications:
20111121
HEF40098B v.7
HEF40098B v.7
20110914
HEF40098B v.6
HEF40098B v.6
20090624
HEF40098B v.5
HEF40098B v.5
20081031
HEF40098B v.4
HEF40098B v.4
20080731
HEF40098B_CNV v.3
HEF40098B_CNV v.3
19950101
Product specification
HEF40098B_CNV v.2
HEF40098B_CNV v.2
19950101
Product specification
HEF40098B
9 of 12
HEF40098B
NXP Semiconductors
Product status[3]
Definition
Development
This document contains data from the objective specification for product development.
Qualification
Production
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
14.3 Disclaimers
Limited warranty and liability Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
HEF40098B
10 of 12
HEF40098B
NXP Semiconductors
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
HEF40098B
11 of 12
HEF40098B
NXP Semiconductors
16. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
14.1
14.2
14.3
14.4
15
16
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 9
Legal information. . . . . . . . . . . . . . . . . . . . . . . 10
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Contact information. . . . . . . . . . . . . . . . . . . . . 11
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section Legal information.