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Recent
Router Architectures
hardware
switching fabrics
efficient and faster lookup algorithms
have created routers that are capable of
routing at multi-gigabit speeds
Introduction
Introduction
Basic
line
First-Generation IP Routers
Introduction
Second-Generation IP Routers
CPU
Shared Backplane
CPU
Buffer
Memory
CP
L
U In i n e
te
rf a
M
ce
em
or
y
DMA
DMA
DMA
Line
Interface
Line
Interface
Line
Interface
MAC
MAC
MAC
Third-Generation
Switches/Routers
Buffer
Memory
Switched Backplane
DMA
DMA
DMA
Line
Card
Local
Buffer
Memory
Line
Card
Local
Buffer
Memory
Line
Card
Local
Buffer
Memory
MAC
MAC
MAC
L Lin
LiILniInneitnee e
L
I
n
t
L Ininntee er rfa
L ILiIninetee rf fa ce
CPI Initnnetneeterf rfac ace ce
nUt er rfa ac e
er f a c e e
f c
M
em ac e e
or
y
Line
Card
CPU
Card
Line
Card
Local
Buffer
Memory
Local
Buffer
Memory
MAC
MAC
match
It is necessary to design a very *fast*
lookup algorithm
lookup
tries
hash tables
hybrid approaches
limitations of CAMs
lower
Hashing Techniques
Function
easy
PATRICIA Trie
PATRICIA Trie
Longest-match
Can
Host route
Network address
Single pass
Host route
Network address
Multiple passes
Host route
Network address
Default address
Participate
to
in routing algorithms
Resolve
scheduling
Admission
to
control
Well
Output
no path to output
trunk unavailable
Buffers
at
input or output
Backpressure
if
Parallel
switch fabrics
increases
Switch fabrics
Transfer
Routing
Buffered crossbar
What
Buffering
All
Where
input
in
the fabric
output
shared
with
No
From N. Mckeowns
Hot Interconnects 7 presentation (1999)
From N. Mckeowns
Hot Interconnects 7 presentation (1999)
queues at inputs
Arbiter must choose one of the input ports
for each output port
How to select?
Iterated Matching
inputs
Output queueing
Output queueing
Can
10
Shared memory
11