Poster 148

Fully Integrated Power Supply Design for Wireless Biomedical Implants

Maysam Ghovanloo, Khalil Najafi
Centerfor Wireless Integrated Microsystems
University of Michigan, Ann Arbor MI 48109-2122
mavsamph@,enpin.umich.edu, Tel: (734) 763-6650, Fax: (734) 763-9324
Abstract - This paper describes implementation of several fully
integrated on-chip rectifier designs in BiCMOS technology for
rectifying the externally generated RF magnetic power and
data carrier signal in wireless biomedical implants to generate
an unregulated DC supply. It also presents application of these
rectifiers in an integrated dual d5V output supply capable of
providing up to 50mW for wireless biomedical implants. New
full-wave rectifier topologies and low power circuit design
techniques have been employed to decrease substrate leakage
current and parasitic components, reduce the possibility of
latch-up, and improve power transfer efficiency and high
frequency performance of the rectifier block. These circuits
have been designed to be used in a wireless neural stimulating
microsystem and fabricated in the University of Michigan's
single-metal, dual-poly 3 - ~ mBiCMOS process. The rectifier
areas are in the range of 0.12 to 0.48mm2 and they are capable
of delivering more than lOOmW from the receiver coil to the
regulator circuitry. The performance of all rectifier designs
has been tested and compared using up to 4MHz carrier.
Keywords - Rectifiers, implants, wireless, IW, power supply

I. INTRODUCTION
Fully integrated microsystems and system-on-chip concepts
are currently under investigation in many different sections
of microelectronic industry and MEMS.
However,
biomedical microsystems are among those that probably get
the highest benefits from progresses in this area especially
when they are intended to be implantable. Almost all of
these implantable devices except a small category, which
need large drug reservoirs out of the body, have become
wireless to improve patient's safety and comfort level.
Some of these wireless implants, which naturally have very
low power requirement like pacemakers include a DC
power source in the form of rechargeable or long-lifetime
disposable batteries and the rest of them need to be powered
by magnetic inductive coupling between an extracorporeal
transmitter coil and an intemal receiver coil inside the
implanted device. Transcutaneous electromagnetic power,
which is delivered by the extemally generated RF magnetic
field in the MHz range, generates a sinusoidal voltage in the
receiver tank circuit [ 1,2]. The next block should be a wideband rectifier to convert the AC signal to an unregulated DC
supply and finally there is a regulator block, which rejects
high frequency ripples as well as eliminated power supply
output voltage variation in case of load current variations.
However, in many recent biomedical implant designs, the

414

Fig. I. Cross-section of a diode-connected NPN transistor with its

parasitics.

rectifier block is either a hybrid diode bridge [3,4] or an

inefficient half-wave rectifier using the substrate or an offchip diode [5-81. The most important reason behind this is
lack of an efficient high current full-wave rectifier, which
does not dissipate power through substrate leakage current
and does not increase possibility of latch-up.
Low-current integrated full-wave rectifiers have been
used in remote sensing [9] and radio-frequency
identification (WID) [ 101 applications but have not been
studied in detail or employed in high current applications
such as biomedical stimulators. The design of high current
wide-band integrated rectifiers has been addressed in this
paper using BiCMOS fabrication process for wireless neural
stimulating microsystems [ 111. Diode-connected BJT
transistors have been characterized in the following section
in terms of leakage current and the effects of their geometry
and base resistance.
Conventional BJT-diode bridge
rectifiers in a BiCMOS process have been discussed in
section 111 and section IV introduces a new topology for a
CMOS full-wave bridge rectifier in a BiCMOS process with
very low risk of latch-up and leakage current. The
application of these rectifiers has been discussed in
implementation of an integrated dual f 5 V output power
supply in section V, followed by the conclusion in section
VI.
11. DIODE-CONNECTEDBJT TRANSISTORS

The vertical NPN transistors, used as rectifier diodes,

have been fabricated in the UofM BiCMOS process, which
has been described in [12]. One major difference between
the UofM and standard BiCMOS processes is the lack of an
nf buried layer, which deteriorates performance of the NPN
devices. Fig. 1 shows cross section of a diode-connected
NPN transistor with its associated parasitic components.
Here, N-epi and P-well are shorted to prevent the parasitic
PNP transistor from turning on. However, when the diode

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Poster 148

is forward biased, current passes through P-well and turns

the original NPN on. This in turn passes some of the diode
forward current through the N-epi, which has a high
resistivity under the P-well region because of the lack of nf
buried layer in this process. If the voltage drop across the
N-epi resistor exceed VBE(on),the parasitic PNP transistor
turns on, resulting in current leakage from P-well to the
grounded P-substrate. Two methods were tested to decrease
the substrate leakage current without changing the process.
1) Increase the diode-connected NPN geometry: This
method puts several of N-Epi distributed resistors in parallel
resulting in reduction of their lumped value. The minimumsize NPN transistor emitter size, so called NPN1, was
chosen to be 7 x 3 7 ~ m . Diode connected NPN1, so called
D1, was forward biased as shown in Fig. 2a and Vd was
changed from 0.5V to 1.2V while measuring I,, I,, and
substrate leakage current I,. The resulting curves in Fig. 2b
show that I, becomes significant when Id>3mA. However
this is not enough for many applications including our
wireless neural stimulator. To test the effect of diode
geometry in the leakage current, two other diode-connected
NPN transistors, D7 and D10, with emitter areas 7 and 10
times higher than D1 respectively, were compared in a
similar way. The results shown in Fig. 2c agree with our
speculation, showing that D10 can pass up to lOmA without
significant substrate leakage.

2) Adding a base resistor: Fig. 1 shows that the

vertical NPN base is the emitter node for the parasitic
vertical PNP, which is responsible for the substrate leakage.
Therefore, it suggests that adding more base resistance in
the leakage current path while keeping the collector
resistance constant in the main forward current path can
reduce substrate leakage. This was tested on D1 by
switching to a current source, Id and changing Rb in Fig. 2a
from 0 to 2kR. The results are shown in Fig. 3. Fig 3a
shows that the leakage current has been decreased
significantly specially at high currents. For example at
Id=lOmA, I, has been reduced to less than a quarter of its
initial value from 0.8mA to 0.16mA as shown in Fig. 3c.
However the disadvantage of this method is increasing the
diode forward voltage drop, which is shown in Fig. 3b. Fig
3c shows that the diode forward voltage drop increases from
1.05V to 2.0V when Rb changes from 0 to 2kQ and
Id=lomA. Therefore, even though adding a base resistor
saves power in reducing the substrate leakage current, it
dissipates more power in rectifier diodes and increases the
required minimum operational coil voltage of the wireless
implant.
111. BJT-BRIDGE
RECTIFIERS

I: : : : : : : :. (

'.:
:0.8

A variety of on-chip conventional BJT bridge rectifiers

.........

...........................

6
Id (mA)

".L

II

1.6
1.4 ............ ..................... ...... .............................
-1.2
......................
,
. .........................
-.
0.8 ................................
o0.6
..................
0.4
.................

. .............,...............
IRb= 0. lb, 5O,l00~200,500.~lk
and 2d Ohms
0

"

,
Id ( m A r

'

...
'"

0.2

................

0.5
0.6

0.4

0.3

UI

0.1

500

1000
1500
Rb (Ohm)

2000

(a)
(b)
(C)
Fig. 3. The effect of base resistance (Rb)on diode-connected NPN substrate leakage current. (a) Substrate leakage current when Rb is changed from 0 to
2kR. (b) Diode-connected NPN voltage drop (c) Comparison between the desirable substrate leakage current reduction and undesirable diode voltage drop
increase by increasing Rb when diode current is fixed at 10mA.

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415

Poster 1 4 8

D
Fig. 4. Conventional BJT bridge rectifiers with different topology, size, breakdown voltage, and current handling capabilities on a rectifier test stmcture.

with different topology, size, breakdown voltage, and

current handling capabilities were tested on a rectifier test
structure, shown in Fig. 4. In terms of maximum input
voltage, designs A, B, and C, which have a single diode in
each branch, cannot handle more than 22V peak input
voltage because of the NPN-diode reverse breakdown.
Designs D and E have 2 series diodes in each branch and
their reverse breakdown goes beyond 40V.
The
disadvantage of the 8 diode full-wave rectifier bridge in
design E is its large area consumption, but in design D the
required area is reduced by 50% by using the parasitic Nepi-P-sub diodes (enclosed in dashed box) for the returning
current path. Reducing the rectifier area also reduces the
parasitic capacitors and improves their high frequency
performance. The frequency responses of rectifiers C and D
have been compared in Fig. 5 , which shows the average
current passing through a lkn load at different frequencies
when the sinusoidal input voltage has been constant.
Rectifier D10, which has Fig. 4D topology and D10 diodes,
has the best performance at low frequency (1OOkHz)
because of its lower resistive voltage drop. However, at
high frequency (4MHz) rectifier C1, which has Fig. 4C
topology and D1 diodes, shows the best performance
because of its lower parasitic capacitance. Even though
scaling the rectifier diodes up decreases the diode parasitic
resistors, it increases the parasitic capacitors as well, which
degrade the high frequency performance, in addition to the
cost of chip area. Therefore the optimum rectifier diode size
in each fabrication process will be determined based on the
rectifier operating frequency and peak current by a
compromise between the parasitic resistor and capacitor
values.

Iv. CMOS BRIDGE RECTIFIERS

To eliminate substrate leakage current, described in the
BJT-diode section, diode-connected MOS transistors can be
used instead of BJTs to have a CMOS full-wave bridge
rectifier as shown in Fig. 6. Another advantage of these
rectifiers is their compatibility with standard CMOS
process, which is more popular and cost effective than
BiCMOS. Mpl and Mp2 conduct in the forward direction
when coil voltage is higher than V,,,, delivering power from
the coil to the load. Current passes through the load to
grounded P-substrate and returns back to the coil from MNI
and MN2,which work as switches controlled by the coil
voltage. The instantaneous voltage drop on a diodeconnected MOS when current IDis passing trough it can be
found from:

The MOS threshold voltage, VTh,is basically a process

dependent parameter and can be minimized in the circuit
design by eliminating the body effect. To minimize the
second term, W/L ratio should be increased as much as the
area consumption and parasitic capacitance allow.
Reducing the rectifier voltage drop decreases power
dissipation in the rectifier block and increases the average
rectified DC voltage available at the regulator block input,
lowering the implant required minimum operational input
voltage. The substrate leakage is not significant in MOS
diodes except when the reverse diode voltage is close to the
gate oxide or junction breakdown.
Coil 1

Coil2

12
10

z8
E6
-4
v

vout

0
0.1

Mn2
v + n

1
freq (MHz)

Fig. 5 . Integrated rectifiers frequency response.

416

10

Fig. 6 . Simplified schematic diagram of a CMOS full-wave rectifier.

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Poster 148

Since the sources of all rectifier MOS transistors in

Fig.6 are connected to the coil terminals, which have large
voltage variations going above V, and below GND at high
frequency, protecting this circuit against latch-up and
substrate leakage current is crucial, which can be done by
eliminating the vertical parasitic transistors, shown in Fig.
7b, from turning on. Therefore, the body potential of both
NMOS and PMOS transistors should be dynamically
controlled. In order to dynamically control the body
potential of the rectifier transistors, both NMOS and PMOS
transistor pairs have to be implemented in separated P-Well
and N-Epi regions with enough distance from the rest of
circuits and equipped with auxiliary MOSFETs.
The resulting rectifier circuit is shown in Fig. 7a. Half
of the symmetrical cross section of this circuit can be seen
in Fig.7b, demonstrating the NMOS and diode-connected
PMOS complexes and parasitic vertical BJT transistors in
separated P-Well and N-Epi regions. The source-side
auxiliary PMOS (Mp3) shares its source and gate with the
diode-connected Mpl and turns on whenever Mpl is ON
connecting the separated N-Epi to the coil voltage, which is
higher than V,,,.
The drain-side auxiliary PMOS (MP4)
shares its drain with Mpl and tums on whenever Mpl is OFF
connecting the separated N-Epi to the output voltage, which
is higher than the coil voltage at this time. Similarly, MN3
and MN4 dynamically control the separated P-Well potential
and connect it to the lower of either ground or coil voltages.
Since no current passes through auxiliary MOSFETs when
they turn on, their drain-source voltage is close to zero.
Therefore, they do not let the parasitic vertical BJT
transistors to turn on and leave little chance for leakage
current or latch-up. Another advantage of this configuration
is eliminating the body effect on the rectifying MOS
transistors [ 131, which reduces the rectifier voltage drop and
power dissipation as mentioned above. To decrease the risk
of latch-up further, the PMOS and NMOS complexes were
widely separated and protected by N+ and P+ guard rings
respectively as shown in Fig. 7c. Fig. 8 shows simulated
waveforms of the CMOS rectifier. The two upper traces are
V,, and coil1 voltages and the lower two traces show how
separated N-Epi and separated P-Well potentials follow
Max(V,,,,Coill) and Min(GND,Coill) respectively. Figs.
8b and 8c show measured waveforms on the prototype
CMOS rectifier, while connected to a 1kQ load. These
traces are Coill, separated N-Epi, and V,,, from top to
bottom in Fig. 8b. Fig 8c shows similar waveforms
superimposed to demonstrate their relative amplitudes,
which are in agreement with simulation results in Fig. 8a.
At high frequency, parasitic capacitors should be
considered as a limiting factor to the size of the rectifier
MOSFETs. However, in a complete wireless implant chip
most of these capacitors are lumped in parallel with the tank
resonant circuit capacitor, connected between the coil input
terminals, or the rectifier low pass filter capacitor,
connected between the output and ground terminals.
Therefore, their most significant effect is varying these two
capacitors, which can be adjusted after fabrication by

vout

..... .

(c)
Fig. 7. (a) Schematic diagram of the CMOS full-wave rectifier implemented
in an N-Epi BiCMOS process (b) Cross section of half of the symmetrical
structure showing the NMOS and diode-connected PMOS complexes and
parasitic BJTs. (c) Prototype rectifier fabricated in the UofM 3pm
BiCMOS process. Size: 0.5x0.73mm

trimming provisions. The experimental results of Fig. 5

show that the CMOS rectifier frequency response is superior
to all other BJT counterparts, which have been fabricated in
the same process.

v. DUAL-OUTPUT
POWER SUPPLY
The rectifiers discussed in previous sections were
employed in design of an integrated dual-output power
supply. Fig. 9 shows a simplified schematic diagram of the
voltage regulator block. It generates 5V/l OV outputs and is
able to supply over lOmA from its 1OV output. A VBE
referenced current source (Iref) is mirrored to bias two 5.4V
Zener diodes, which generate 5.4V and 12.2V reference

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417

Poster 148

11 314

(%T2,

11 338

MI

9 3 . Q4

: 11

5v~7+&,j;;
M3

M5

M6

Fig. 10. The complete schematic diagram of the unity-gain buffer.

@)

(a)

Fig. 1I. PNP transistor and its NPN-PMOS equivalents.

Fig. 8. Simulation and measured waveforms when the CMOS rectifier is

loaded by a 1kQ resistor. (a) Simulation waveforms from top: rectified
output voltage, one of the coil input voltages, separated N-Epi voltage
controlled by auxiliary PMOS's, and separated P-Well voltage controlled
by auxiliary NMOS's. (b) Measured waveforms from top: coil input,
separated N-Epi, and output voltage. (c) Similar measured waveforms
superimposed to demonstrate their relative amplitudes.

voltages for the unity-gain buffer and a Darlington pair

pass-transistor pair respectively.
The extra 0.4V
compensates for the voltage drop caused by the passtransistor parasitic resistors shown in Fig. 1.
One of the challenges in this design is producing both
+5V supply voltages on a single chip. One method could be
having two separate regulators for +5V and -5V outputs

with a common ground. The main disadvantage of a

negative voltage regulator is its isolated PNP pass transistor,
which has poor performance in this process because of the
lateral structure. Besides having voltages less than the
grounded P-substrate on-chip can produce a lot of
complications and increase the chance for leakage current
and the overall power consumption. Another method is to
divide a 1OV regulator into two equal parts and buffer the
central node to act as a virtual ground. Therefore, an
isolated chip can assume the 1OV and GND rails as +5V and
-5V supplies respectively. A class B output stage seems to
be a good choice for the unity gain buffer because of its
negligible standby power consumption, but since the output
should always stay around 5V, the amplifier dead-zone
generates a lot of ripple on the isolated chip GND rail. Fig.
10 shows the schematic diagram of the class AB output
stage used in this power supply. The PNP transistors were
avoided and replaced by their PMOS-NPN counterparts [ 141
as shown in Figure 11. The major difference between a
PNP transistor and its PMOS-NPN equivalent is the VBE(on)
voltage, which is a weak hnction of the collector current in
the former but is defined from (1) in the latter with ID
replaced by VBE/RB. To reduce the effect of the second term
in (l), we want to increase RB and W/L ratio of the PMOS
transistor. However, a large RB, which is found to be in the
order of lOOKQ consumes a lot of chip area. Therefore, RB
in Figure l l b was replaced by an NMOS with small W/L
ratio, biased in the triode region. The equivalent RB can be
calculated from

'

11'

(2)
= b n c o . r (wn Ln )('Cis - 'ThN - ' B E ( 0 N )
It can be shown [14] that the small signal output resistance
of the PMOS-NPN compound is
(3)
Ro =''gmp(l+gmn(R, II yn))=l'gmp',e
Fig. 9. Simplified schematic diagram of the dual-output voltage regulator
block.

418

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Poster 148

TABLE 1
SPECIFICATIONS OF VARIOUS RECTIFIER DESIGNS

where g,, and g,

are M,, and Mp transconductance
respectively and r,and h/, are Qn hybrid n parameters.
This resistance in parallel with the resistance seen from Q2
emitter is low enough for the unity gain buffer and test
results, which can be seen in Fig. 12 show that this circuit
can easily source and sink as much as 5mA with less than
1V variations in its output voltage.

tested and compared using up to 4MHz carrier signal. Table

1 summarizes some of the rectifier specifications.
ACKLOWLEDGMENTS
The authors wish to thank Prof. K. D. Wise and Dr. W. J. Heetderks
of the National Institute of Health for their guidance. This work was
supported by the Neural Prosthesis Program, NIH, under contract number
NIH-NINDS-NO I -NS-9-2304.

V. CONCLUSION

REFERENCES

Several fully .integrated rectifiers in BiCMOS

technology have been implemented for rectifying the
externally generated RF carrier signal in wireless
biomedical implants to generate an unregulated DC voltage.
This voltage was then regulated and divided by a unity gain
buffer to generate dual +5V supplies. New rectifier
topologies and low power circuit design techniques have
been employed to decrease substrate leakage current and
parasitic components, reduce the possibility of latch-up, and
improve power transfer efficiency and high frequency
performance of the rectifier block. Increasing the size or
adding a base resistor can reduce the diode-connected BJT
leakage at high currents but a compromise should be made
between the parasitic resistor and capacitor values based on
the maximum current and frequency in which the rectifier is
being used. The body bias of diode-connected MOSFETs
in CMOS rectifiers have been adjusted using two auxiliary
MOSFETs for each of them to eliminate substrate leakage
and threshold voltage increase, which consequently decrease
the rectifier voltage drop and power dissipation. These
circuits have been fabricated in the University of Michigans
3-ym BiCMOS process and occupy areas in the range of
0.12 to 0.48.
These rectifiers are capable of delivering
more than lOOmW from the receiver coil to the implant
circuitry. The performance of all rectifier designs has been

[IO]

[ll]

[I21

>

[ 131
0.01

0.1

10

100

R+RFig.12: The dual-output power supply load balance curve. Setting both
loads at IKR and increasing them one at a time.

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