STLD 2006

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Code No: RR210203 Set No. 1

II B.Tech I Semester Supplementary Examinations, March 2006
SWITCHING THEORY AND LOGIC DESIGN
( Common to Electrical & Electronic Engineering, Electronics &
Communication Engineering, Computer Science & Engineering, Electronics
& Instrumentation Engineering, Bio-Medical Engineering, Information
Technology, Electronics & Control Engineering, Computer Science &
Systems Engineering, Electronics & Telematics and Electronics & Computer
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Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. (a) Perform the subtraction with the following unsigned binary numbers by taking
the 2’s complement of the subtrahend.
i. 11010-10000
ii. 11010-1101
iii. 100-110000
iv. 1010100-1010100
(b) The binary numbers listed have a sign bit in the left most position and, if nega-
tive, are in 1’s complement form. Perform the arithmetic operations indicated
and verify the answers.
i. 101011+111000
ii. 001110+110010
iii. 111001-001010
iv. 101011-100110
[8+8]
2. (a) Each of the following functions actually represents a set of four functions
corresponding Pto the various assignments
P of the dont care terms.
f1 (w,x,y,z) = P(1,3,4,5,9,10, 11) P
+ φ(6,8)
f2 (w,x,y,z) = (0,2,4,7,8,15) + φ (9,12)
then
i. Find such that f3 = f1 .f2
ii. Find such that f4 = f1 + f2
iii. Simplify and obtain minimal sop for f3 and f4 .
(b) Determine the canonical sum-of-products representation of the below func-
tions.
i. f (x, y, z) = z + (x + y)(x + y)
ii. f (x, y, z) = x + (x y + xz)
[3+3+4+3+3]
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3. Using the Quine-Mc Cluskey method of tabular reduction
P ,minimize the given
combinational single - output function f(w,x,y,z) = m(0,1,5,7,810,14,15) [16]
4. (a) Design 4 to 6 decoder using 2 to 4 decoders and basic gates.

(b) Implement Full adder circuit using ROM and Verify the working.
[8+8]
5. (a) Define the following terms in connection with a flip-flop
i. set-up time
ii. hold-time
iii. propagation delay time
iv. preset
v. clear
(b) Draw the schematic circuit of D-Flip-Flop with negative edge triggering using
NAND gates. Give its truth-table and explain its operation
[10+6]
6. Design a sequential circuit with two D flipflops A and B and one input x. When
x=0, the state of the circuit remains the same. When x=1, the circuit goes through
the state transitions from 00 to 01 to 11 to 10 back to 00 and repeats. [16]
7. For the machine shown in the table below obtain:
(a) The corresponding reduced machine table in standard form

(b) Find a minimum length that distinguishes state A from state B where PS:
present state, NS: next state, Z: output, X: input
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A
B
C
D
E
F
G
H
NS,Z
X=0 X=1
B,1
F,1
D,0
C,0
C,1
C,0
H,1
D,1
E,1
F,1
D,1 C,1
C,1 C,1
D,1
A,1
[10+6]
8. Obtain the ASM charts for the following state transition
(a) If x = 0, control goes from T1 to state T2, if x = 1, generate the conditional

operation and go from T1 to T2.
(b) If x = 1, control goes from T1 to T2 and then to T3, if x = 0, control goes
from T1 to T3.
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(c) Start from state T1, then if xy = 00, go to T2, if xy = 01, then go to T3, if xy
= 10, then go to T1, otherwise go to T3. and design its control circuit using
i. D flip flop & decoder
ii. Input multiplexer & a register
[8+8]
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Engineering)
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1. (a) Decimal system became popular because we have 10 fingers. A rich person on
earth has decided to distribute Rs. One lakh equally to the following persons
from various planets. Find out the amount each one of them will get in their
respective currencies.
A from planet VENUS possessing 8 fingers
B from plant MARS possessing 6 fingers
C from planet JUPITER possessing 14 fingers
D from plant MOON possessing 16 fingers
(b) Write short notes on different types and properties of four bit codes with the
aid of suitable examples.
[8+8]
2. Four persons, members of a TV panel game, each have an ON/OFF button that is
used to record their opinion of a certain pop record. Instead of recording individual
scores, some data processing is required such that the score board shows a HIT when
the majority vote is in favour of and a MISS if it is against Provision must also be
made for a TIE. From this verbal statement.
(a) Derive the truth tables separately for HIT, MISS and TIE.
(b) Extract S-O-P and P-O-S for each of the three outputs.
(c) Simplify the equation in SOP form.
[6+6+4]
3. (a) Draw the AND-OR gate implementation

P of the following function after sim-
plifying it . F(A,B,C,D) = (0,2,5,6,7,8,10)
(b) Simplify the following expression and implement them with two level NAND
gate circuits.
i. A B+ABD+ABD+A C D+A B C
ii. BD+BCD+AB C D
[8+8]
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4. (a) Design a combinational circuit that accepts a 3-bit number and generates an
output binary number equal to the square of the input number.
(b) Realize a 3-bit odd-parity generator circuit using only two-input ex-or gate
[8+8]
5. (a) Define the following systems
i. synchronous sequential system
ii. asynchronous sequential system
iii. combinational system
(b) Draw the schematic circuit of a negative edge triggered D-Flip-Flop using
NAND gates and give its truth-table. Justify the entries in the truth-table.
[6+101]
6. Design a sequential circuit with two D- flipflops A and B and one input x. When
x=0, the state of the circuit remains the same. When x=1, the circuit goes through
the state transitions from 00 to 01 to 11 to 10 back to 00 and repeats. [16]
7. For the machine shown in the table below obtain:
(a) The corresponding reduced machine table in standard form
(b) Find a minimum length that distinguishes state A from state B where PS:
present state, NS: next state, Z: output, X: input
PS NS,Z
X=0 X=1
A B,1 H,1
B F,1 D,1
C D,0 E,1
D C,0 F,1
E D,1 C,1
F C,1 C,1
G C,1 D,1
H C,0 A,1
[10+6]
8. (a) Design a digital system with three 4-bit registers, A, B and C to perform the
following operations by drawing the ASM chart.
i. Transfer two binary numbers to A and B when a start signal is enabled.
ii. If A<B, shift left the contents of A and transfer the result to register C.
iii. If A>B, shift right the contents of B and transfer the result to register C.
iv. If A+B, transfer the number to register C unchanged.
(b) Realize the above using JK flipflops and D flip flops.
[8+8]
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Engineering)
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1. (a) i. Express decimal digits 0-9 in BCD code and 2-4-2-1 code.
ii. Determine which of the above codes are self complementing.
(b) i. Convert the decimal number 96 into binary and convert it to gray code
number.
ii. Convert the given gray code number to binary: 1001001011.
[8+8]
2. (a) Find the minimal

P expression
Pfor the function
f(w,x,y,z)= (0,2,5,9,15) + d (6,7,8,10,12,13) using Karnaughs-map.
(b) i. Determine the Canonical sum-of-products form for T (x, y, z) = xy + z +
xyz
ii. Minimize the function f (x, y, z, w) = x + xyz + wx + xy + wx + xyz.
[8+4+4]
3. (a) Implement the following function using only NOR gates F=a .(b+ c.d) + (b
. c).
(b) Implement the following function using only NAND gates G=(a + b). (c. d
+e)
(c) Give the minimum two-level SOP realization
P of the following switching func-
tion using only NAND gates. F(x,y,z) = m (0,3,4,5,7)
[4+4+8]
4. (a) Design 4 to 6 decoder using 2 to 4 decoders and basic gates.

(b) Implement Full adder circuit using ROM and Verify the working.
[8+8]
5. (a) What is meant by Lock-mode and count mode in Flip-Flop.

(b) Draw the circuit of J-K-Master slave Flip-Flop with active high clear and
active low preset and explain its operation.

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[16]
Figure 1:
(c) Give transition Table for the given(figure1) Flip-Flop.

[4+6+6]
6. Design a synchronous modulo 10 up down counter .Use T flip flops for synthesis.
7. For the machine given below, find the equivalence partition and a corresponding
reduced machine in standard form and also explain the procedure:
PS NS,Z
X=0 X=1
A B,0 E,0
B E,0 D,0
C D,1 A,0
D C,1 E,0
E B,0 D,0
8. Design a half adder and half subtractor circuit using
(a) multiplexer and registers

(b) one flipflop per state..Draw the state diagram and convert it to ASM block
and tablulate its state table.
[16]
[8+8]
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Engineering)
⋆⋆⋆⋆⋆
1. (a) Perform the subtraction with the following unsigned binary numbers by taking
the 2’s complement of the subtrahend.
i. 11010-10000
ii. 11010-1101
iii. 100-110000
iv. 1010100-1010100
(b) The binary numbers listed have a sign bit in the left most position and, if nega-
tive, are in 1’s complement form. Perform the arithmetic operations indicated
and verify the answers.
i. 101011+111000
ii. 001110+110010
iii. 111001-001010
iv. 101011-100110
[8+8]
2. (a) Obtain the simplified expressions in sum of products for the following Boolean
functions using Karnaugh-Map.
P
i. F(A, B,C,D) = (7,13, 14, 15)
P
ii. F(w,x,y,z) = (2,3,12,13,14,15)
(b) Minimize the following Boolean expressions to the required no. of literals
i. BC +AC +AB+BCD to four literals
ii. ABC+ A BC + ABC+ABC+A B C to five literals
(c) Obtain complement and dual for the given expression (AB+BC+AC) (EF)
[6+6+4]
3. (a) Implement the following function using only NOR gates F=a .(b+ c.d) + (b
. c).
(b) Implement the following function using only NAND gates G=(a + b). (c. d
+e)
1 of 2
(c) Give the minimum two-level SOP realization
P of the following switching func-
tion using only NAND gates. F(x,y,z) = m (0,3,4,5,7)
[4+4+8]
4. (a) Give the schematic circuit for a BCD-to-decimal decoder. Give the truth-table
for the same.
(b) A combinational circuit is specified by the following two Boolean functions
Design
P the circuit with a decoder and basic gates.
F = P m (1,5,9,15)
G= m (0,1,9,10,12)
[8+8]
5. (a) Compare combinational Vs sequential logic circuits.
(b) Define the following terms of a flip flop
i. Hold time
ii. Set up time
iii. Propagation delay time.
(c) Draw the circuit diagram of a master slave RS flip flop and explain its opera-
tion with the help of truth table.
[4+6+6]
6. (a) Compare merits and demerits of ripple and synchronous counters.
(b) Design a modulo-12 up synchronous counter using T-flip flops and draw the
circuit diagram.
[6+10]
7. For the machine given below, find the equivalence partition and a corresponding
reduced machine in standard form and also explain the procedure:
PS NS,Z
X=0 X=1
A B,0 E,0
B E,0 D,0
C D,1 A,0
D C,1 E,0
E B,0 D,0
[16]
8. Construct an ASM block that has 3 input variables (A,B,C), 4 output (W,X,Y,Z)
and 2 exit paths. For this block, output Z is always 1, and W is 1 if A & B are
both 1. If C=1 & A=0, Y=1 and exit path 1 is taken. If C=0 or A=1, X=1 and
exit path 2 is taken.
Realize the above using the One flip flop per state. [16]
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www.andhracolleges.

com The Complete Information About Colleges in Andhra Pradesh

Code No: RR210203 Set No. 1

www.andhracolleges.com Engineering-MBA-MCA-Medical-Pharmacy-B.Ed-Law Colleges Information

Code No: RR210203 Set No. 1

4. (a) Design 4 to 6 decoder using 2 to 4 decoders and basic gates.

(a) The corresponding reduced machine table in standard form

8. Obtain the ASM charts for the following state transition

(a) If x = 0, control goes from T1 to state T2, if x = 1, generate the conditional

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Code No: RR210203 Set No. 1

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Code No: RR210203 Set No. 2

3. (a) Draw the AND-OR gate implementation

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Code No: RR210203 Set No. 2

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Code No: RR210203 Set No. 3

2. (a) Find the minimal

4. (a) Design 4 to 6 decoder using 2 to 4 decoders and basic gates.

5. (a) What is meant by Lock-mode and count mode in Flip-Flop.

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Code No: RR210203 Set No. 3

(c) Give transition Table for the given(figure1) Flip-Flop.

(a) multiplexer and registers

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