Commutation Overlap in 3 Phase Converter

Consider a 3-phase converter being fed by a transformer which is sure to have some leakage reactance.
This will not allow the current to be transferred from one device to another (for eg. From device no. 5 to
device no.1, i.e., from phase C to phase A) abruptly because if the source inductance Ls has some stored
energy, it has to be given back completely before it can allow the current to be transferred from one
phase to another. Due to this situation, three devices will conduct simultaneously in a three-phase
converter during the transition period rather than two devices (one form upper half and another from
lower half of the converter) conducting at a time. The situation wherein three devices conduct
simultaneously is called Commutation overlap.
In a HVDC system, normally several synchronous generators with a very high synchronous reactance are
connected to their respective power transformers (which have their own leakage reactances). The
generated voltage is at about 15 kV level; this stepped upto 400 kV level by the power transformers for
transmission further. Apart from getting connected to the AC transmission lines, this 400 kV windings
will also be feeding the converter transformers which are connected in Y--Y configuration. These
secondary and tertiary windings are connected to two 6-pulse thyristor rectifiers which will convert the
230kV AC from the converter transformer secondary (and tertiary) into about 250kV DC. These two 6pulse converters together give an output of a 500kV DC 12-pulse output voltage (with a very small
ripple) when connected in series. Because of the synchronous reactance, power transformer reactance
and converter transformer reactance, the overall source reactance visualized by the 12-pulse converter
in a HVDC system is very large which results in an overlap of 12 to 14 in a 60 conduction period of a
specific pair of thyristors. Such a HVDC system is shown in Fig.1. The converter transformer is in Y--Y
configuration to make sure that the secondary and tertiary voltages are 30 phase shifted from each
other to give the output voltage with a ripple frequency of (12x50) Hz at the DC link. The power
transformer steps up the 15kV output of the alternator to 400kV transmission level voltage. But the
converter transformer converts this 400kV to 230kV line voltage so that the output at each of the 6pulse thyristor converter is at about 250kV. On series connection, the two 6-pulse converters yield an
output of 500kV. The circulation of the DC current in the HVDC system takes place from the +500 kV line
to the -500 kV line; ground carries hardly any DC current and hence saturation of the power transformer
and converter transformer (due to DC current circulating through the ground) is completely prevented.
Fig. 2 shows a 6-pulse converter with source inductance in each of the phases. The incoming three phase
point in any factory, which is also known as point of common coupling (PCC) where all the other loads
are connected is shown in the figure. The voltage at PCC gets modified due to commutation overlap in
the converter. This will cause the voltage applied to the other loads to be deviating from the normal
sinusoidal wave shape. If some induction and synchronous motors are connected to this PCC, this will
make the motors noisier as they experience harmonic voltages which will also cause harmonic currents
to be drawn by these motors.
Lets try to analyse the circuit during commutation overlap in a 3-phase uncontrolled converter using
Fig.3 especially when device no. 1 takes over the current from device no.5. During this current transfer
all three devices namely, devices 5,6 and 1 conduct. If the DC side load is highly inductive, then the
current through B phase (or device no.6) is a constant (at Idc) whereas the current through 5 is declining
and the current through 1 is increasing. This causes Ls(di/dt) value to be non-zero in phases A and C.
Thus Va at PCC is {Va-Ls(di/dt)} whereas Vc at PCC is {Vc+ Ls(di/dt)}

Fig. 1 HVDC system configuration

Fig. 2 Six-pulse uncontrolled converter with source inductance showing PCC for each phase

Fig.3 Equivalent circuit during overlap of D1 and D5

If we write the loop equation for the loop formed by Va,Ls,D1,D5, Ls and Vc, then it would be
Va-Vc = VAC = Ls[ (di1/dt)-(di5/dt)] ------------------------------------------------------------(1)
But i1+i5=Idc=i6; (di1/dt)+(di5/dt) = dIdc/dt =0 ; therefore, (di1/dt)= -(di5/dt)----- -(2)
So VAC = 2Ls(di1/dt); ----------------------------------------------------------------------------(3)
If we assume that the instant at which device 1 is taking over is at wt=0 , for an angle of , both 5 and 1
will be conducting during which time, i5 is decreasing from Idc to 0 and i1 is rising from 0 to Idc.
Had it been a thyristor rectifier, device 1 would have been fired at and overlap would have continued
until (+). Therefore,
+
Idc
VAC d(wt) =2wLs di1-------------------------------------------------------------------(4)

0
So, Vm {cos-cos(+)} = 2wLsIdc---------------------------------------------------------(5)
During this angle , the DC link voltage across the load would be the difference between the voltage at
the junction point of D5 and D1 and Vb (there is no drop across Ls in B phase because there is no rate of
change of current in B phase).
The voltage at the junction point of D1 and D5 is {Va-Ls(di1/dt)} or {Vc + Ls(di1/dt)}
But from (1) we can write that this junction point voltage is =Va-0.5 VAC = (VA+VC)/2
Thus the load voltage is (VA+VC)/2 - VB =(VAB+VCB)/2-------------------------------(6)
If there had not been any overlap, then, the load voltage would have been VAB. The difference between
the load voltages without and with commutation overlap is
VAB - 0.5(VAB+VCB) = VAC/2-----------------------------------------------------------------(7)
Thus the voltage drop due to commutation overlap between devices 5 and 1 is 0.5 VAC.
Thus, the drop can also be stated as wLsIdc as per equation (4).
This drop takes place during every transition, i.e., 6 times in a cycle and hence should be averaged over
60 or /3 radians.
Thus, average drop due to commutation overlap = wLsIdc/(/3) = 3wLsIdc/ ---(8)
So, the output of a 3-phase full-converter working at a firing angle with source inductance effect being
considered is =(1/){3VmCos -3wLsIdc} --------------------------------------(9)
where Vm=line to line peak voltage.
The waveforms due to commutation overlap in a diode rectifier are shown in Fig.4. The three-phase
source voltages, DC load current, source current (which rises and falls slowly), DC voltage and PCC
voltages of Va and Vc are shown in the figure.

Fig.4. and Fig.5 Waveforms for a 3-phase diode rectifier for a highly inductive load and resistive load
with source inductance effect.
Fig.5 shows the waveforms of the diode rectifier with R load. Even in this case, commutation overlap
effect is felt because the current happens to be continuous. Fig.6 shows the waveforms of the supply
voltages and voltage at PCC due to commutation overlap in a thyristor rectifier with a firing angle . The
voltage drop due to overlap is shown in the figure below.

This time lag is due to commutation inductance.

Fig. 6 Commutation overlap effect for =60 in a 3-phase full-converter

So, the effect of overlap is mainly felt in four ways:
1. The DC link voltage decreases. As the DC current is higher or the frequency is higher or Ls value
is higher, more drop will occur.
2. The voltage at the PCC gets modified; it is not a pure sinusoid any more. It has dents and bumps
due to drop in Ls.
3. The source side current does not rise or fall abruptly. It has a finite rate of rise and rate of fall.
So, the harmonic content in the source current will come down.
4. The power factor visualized from the source side will come down because the source current is
delayed further due to Ls.