CONTENT

1. INTRODUCTION
2. DESIGN PRINCIPLE
3. CIRCUIT DESCRIPTION

A. Power supply
B. Mother board
C. Led indicator
D. Bi directional Motor driver
E. DC Motor Driver
F. Relay Driver
G. DTMF Encoder
H. DTMF Decoder
I. FM Transmitter
J. FM Receiver
K. Audio Amplifier
L. Signal Conditioning Circuit

4. FUTURE EXPANSION
5. CONCLUSION
WIRELESS VIDEO MONITORING SYSTEM
1. INTRODUCTION

The wireless video monitoring system is one of the major equipment used for security
purpose. The security system is not only used in industries but also it is mostly used for
private and public security. The security system is one of the major importances in the
present scenario. A need of all modern industries and public place and private premises

2. DESIGN PRINCIPLE

In this project there is one base station and three wireless monitoring systems, in the
monitoring system a wireless camera is installed on rotating tower. The rotating tower is
designed with a micro controller based stepper motor driver. The stepper motor driver
drives the camera base in steps. There are two guide bars placed at the extreme ends
of the camera position. The wireless camera is fixed on the top of the tower, to limit the
viewing angle the camera rotation or movement is restricted to a limited angle. The
rotating tower rotates with the camera and the camera base is fixed with one logic
signal source, to limit the angle of rotation two feed back signals are taken to the mother
board. The micro controller 89c51 programmed to rotate the stepper motor and check
the feed back signal after each step of rotation. When ever the logic signal touches the
feed back point the controller receives the feedback and change the direction of
movement. The controller is having two feedback inputs to understand the left and right
extreme positions and on receiving the feedback signal the controller change the
direction of movement of the stepper motor. This way the camera can oscillate with in a
fixed point from left to right and right to left. There are three wireless stations designed
for monitoring three locations. In this stations there are wireless video cameras are
mounted which transmit signal in the AV range of the TV channels.

Base monitoring station

There is another unit called base monitoring station which is designed with an AT 89c51
microcontroller. This is basically a sequential switch. Which multiplex the received
signal to the TV AV channel. This station is having three receivers and tuned to
receive signals from different video transmitters. The micro controller is designed to
sample the receivers and multiplex to one of the channel of the TV unit used to monitor
the three systems. There are three numbers of electromagnetic relays which is operated
with time slot. In the relay array only one relay is remained closed for a given time
period and others are remained open. This sequential switching allot the time slat to the
receiver for viewing the video.

3. CIRCUIT DESCRIPTION
A. POWER SUPPLY

Circuit connection:- In this we are using Transformer(0-12)v,1Amp, IC 7805 & 7812,

diodes IN 4007,LED & resistors.
Here 230V,50 Hz ac signal is given as input to the primary of the transformer and the
secondary of the transformer is given to the bridge rectification diode. The o/p of the
diode is given as i/p to the IC regulator (7805 &7812) through capacitor (1000mf/35v).
The o/p of the IC regulator is given to the LED through resistors.
Circuit Explanations:- When ac signal is given to the primary of the transformer, due
to the magnetic effect of the coil magnetic flux is induced in the coil(primary) and
transfer to the secondary coil of the transformer due to the transformer action.”
Transformer is an electromechanical static device which transformer electrical energy
from one coil to another without changing its frequency”. Here the diodes are connected
in a bridge fashion. The secondary coil of the transformer is given to the bridge circuit
for rectification purposes.
During the +ve cycle of the ac signal the diodes D2 & D4 conduct due to the forward
bias of the diodes and diodes D1 & D3 does not conduct due to the reversed bias of the
diodes. Similarly during the –ve cycle of the ac signal the diodes D1 & D3 conduct due
to the forward bias of the diodes and the diodes D2 & D4 does not conduct due to
reversed bias of the diodes. The output of the bridge rectifier is not a power dc along
with rippled ac is also present. To overcome this effect, a capacitor is connected to the
o/p of the diodes (D2 & D3). Which removes the unwanted ac signal and thus a pure dc
is obtained. Here we need a fixed voltage, that’s for we are using IC regulators (7805 &
7812).”Voltage regulation is a circuit that supplies a constant voltage regardless of
changes in load current.” This IC’s are designed as fixed voltage regulators and with
adequate heat sinking can deliver output current in excess of 1A. The o/p of the bridge
rectifier is given as input to the IC regulator through capacitor with respect to GND and
thus a fixed o/p is obtained. The o/p of the IC regulator (7805 & 7812) is given to the
LED for indication purpose through resistor. Due to the forward bias of the LED, the
LED glows ON state, and the o/p are obtained from the pin no-3.

B. MOTHERBOARD
Introduction
Despite it’s relatively old age, the 89C51 is one of the most popular Microcontroller in
use today. Many derivatives Microcontroller have since been developed that are based
on--and compatible with--the 8051. Thus, the ability to program an 89C51 is an
important skill for anyone who plans to develop products that will take advantage of
Microcontroller.

Many web pages, books, and tools are available for the 89C51 developer.

The 89C51 has three very general types of memory. To effectively program the 8051 it
is necessary to have a basic understanding of these memory types.

The memory types are illustrated in the following graphic. They are: On-Chip Memory,
External Code Memory, and External RAM.
On-Chip Memory refers to any memory (Code, RAM, or other) that physically exists on
the Microcontroller itself. On-chip memory can be of several types, but we'll get into that
shortly.

External Code Memory is code (or program) memory that resides off-chip. This is often
in the form of an external EPROM.

External RAM is RAM memory that resides off-chip. This is often in the form of
standard static RAM or flash RAM.

Code Memory

Code memory is the memory that holds the actual 8051 program that is to be run. This
memory is limited to 64K and comes in many shapes and sizes: Code memory may be
found on-chip, either burned into the Microcontroller as ROM or EPROM. Code may
also be stored completely off-chip in an external ROM or, more commonly, an external
EPROM. Flash RAM is also another popular method of storing a program. Various
combinations of these memory types may also be used--that is to say, it is possible to
have 4K of code memory on-chip and 64k of code memory off-chip in an EPROM.

When the program is stored on-chip the 64K maximum is often reduced to 4k, 8k, or
16k. This varies depending on the version of the chip that is being used. Each version
offers specific capabilities and one of the distinguishing factors from chip to chip is how
much ROM/EPROM space the chip has. However, code memory is most commonly
implemented as off-chip EPROM. This is especially true in low-cost development
systems and in systems developed by students.
Programming Tip: Since code memory is restricted to 64K, 89C51 programs are
limited to 64K. Some assemblers and compilers offer ways to get around this limit when
used with specially wired hardware. However, without such special compilers and
hardware, programs are limited to 64K.

External RAM

As an obvious opposite of Internal RAM, the 89C51 also supports what is called
External RAM.

As the name suggests, External RAM is any random access memory which is found off-
chip. Since the memory is off-chip it is not as flexible in terms of accessing, and is also
slower. For example, to increment an Internal RAM location by 1 requires only 1
instruction and 1 instruction cycle. To increment a 1-byte value stored in External RAM
requires 4 instructions and 7 instruction cycles. In this case, external memory is 7 times
slower!

What External RAM loses in speed and flexibility it gains in quantity. While Internal RAM
is limited to 128 bytes (256 bytes with an 8052), the 8051 supports External RAM up to
64K.

Programming Tip: The 8051 may only address 64k of RAM. To expand RAM beyond
this limit requires programming and hardware tricks. You may have to do this "by hand"
since many compilers and assemblers, while providing support for programs in excess
of 64k, do not support more than 64k of RAM. This is rather strange since it has been
my experience that programs can usually fit in 64k but often RAM is what is lacking.
Thus if you need more than 64k of RAM, check to see if your compiler supports it but if
it doesn't, be prepared to do it by hand.

On-Chip Memory

As mentioned at the beginning of this chapter, the 89C51 includes a certain amount of
on-chip memory. On-chip memory is really one of two types: Internal RAM and Special
Function Register (SFR) memory. The layout of the 89C51's internal memory is
presented in the following memory map:
As is illustrated in this map, the 8051 has a bank of 128 bytes of Internal RAM. This
Internal RAM is found on-chip on the 8051 so it is the fastest RAM available, and it is
also the most flexible in terms of reading, writing, and modifying it’s contents. Internal
RAM is volatile, so when the 8051 is reset this memory is cleared.

The 128 bytes of internal ram is subdivided as shown on the memory map. The first 8
bytes (00h - 07h) are "register bank 0". By manipulating certain SFRs, a program may
choose to use register banks 1, 2, or 3. These alternative register banks are located in
internal RAM in addresses 08h through 1Fh. We'll discuss "register banks" more in a
later chapter. For now it is sufficient to know that they "live" and are part of internal
RAM.

Bit Memory also lives and is part of internal RAM. We'll talk more about bit memory very
shortly, but for now just keep in mind that bit memory actually resides in internal RAM,
from addresses 20h through 2Fh.

The 80 bytes remaining of Internal RAM, from addresses 30h through 7Fh, may be
used by user variables that need to be accessed frequently or at high-speed. This area
is also utilized by the Microcontroller as a storage area for the operating stack. This fact
severely limits the 8051’s stack since, as illustrated in the memory map, the area
reserved for the stack is only 80 bytes--and usually it is less since this 80 bytes has to
be shared between the stack and user variables.
SFR Descriptions

There are different special function registers (SFR) designed in side the 89C51 micro
controller. In this micro controller all the input , output ports, timers interrupts are
controlled by the SFRs. The SFR functionalities are as follows.

This section will endeavor to quickly overview each of the standard SFRs found in the
above SFR chart map. It is not the intention of this section to fully explain the
functionality of each SFR--this information will be covered in separate chapters of the
tutorial. This section is to just give you a general idea of what each SFR does.

P0 (Port 0, Address 80h, Bit-Addressable): This is input/output port 0. Each bit of this
SFR corresponds to one of the pins on the Microcontroller. For example, bit 0 of port 0
is pin P0.0, bit 7 is pin P0.7. Writing a value of 1 to a bit of this SFR will send a high
level on the corresponding I/O pin whereas a value of 0 will bring it to a low level.

Programming Tip: While the 8051 has four I/O port (P0, P1, P2, and P3), if your
hardware uses external RAM or external code memory (i.e., your program is stored in
an external ROM or EPROM chip or if you are using external RAM chips) you may not
use P0 or P2. This is because the 8051 uses ports P0 and P2 to address the external
memory. Thus if you are using external RAM or code memory you may only use ports
P1 and P3 for your own use.

SP (Stack Pointer, Address 81h): This is the stack pointer of the Microcontroller. This
SFR indicates where the next value to be taken from the stack will be read from in
Internal RAM. If you push a value onto the stack, the value will be written to the address
of SP + 1. That is to say, if SP holds the value 07h, a PUSH instruction will push the
value onto the stack at address 08h. This SFR is modified by all instructions which
modify the stack, such as PUSH, POP, LCALL, RET, RETI, and whenever interrupts are
provoked by the Microcontroller.
Programming Tip: The SP SFR, on startup, is initialized to 07h. This means the stack
will start at 08h and start expanding upward in internal RAM. Since alternate register
banks 1, 2, and 3 as well as the user bit variables occupy internal RAM from addresses
08h through 2Fh, it is necessary to initialize SP in your program to some other value if
you will be using the alternate register banks and/or bit memory. It's not a bad idea to
initialize SP to 2Fh as the first instruction of every one of your programs unless you are
100% sure you will not be using the register banks and bit variables.

DPL/DPH (Data Pointer Low/High, Addresses 82h/83h): The SFRs DPL and DPH
work together to represent a 16-bit value called the Data Pointer. The data pointer is
used in operations regarding external RAM and some instructions involving code
memory. Since it is an unsigned two-byte integer value, it can represent values from
0000h to FFFFh (0 through 65,535 decimal).
Programming Tip: DPTR is really DPH and DPL taken together as a 16-bit value. In
reality, you almost always have to deal with DPTR one byte at a time. For example, to
push DPTR onto the stack you must first push DPL and then DPH. You can't simply
plush DPTR onto the stack. Additionally, there is an instruction to "increment DPTR."
When you execute this instruction, the two bytes are operated upon as a 16-bit value.
However, there is no instruction that decrements DPTR. If you wish to decrement the
value of DPTR, you must write your own code to do so.

PCON (Power Control, Addresses 87h): The Power Control SFR is used to control
the 8051's power control modes. Certain operation modes of the 8051 allow the 8051 to
go into a type of "sleep" mode which requires much less power. These modes of
operation are controlled through PCON. Additionally, one of the bits in PCON is used to
double the effective baud rate of the 8051's serial port.

TCON (Timer Control, Addresses 88h, Bit-Addressable): The Timer Control SFR is
used to configure and modify the way in which the 8051's two timers operate. This SFR
controls whether each of the two timers is running or stopped and contains a flag to
indicate that each timer has overflowed. Additionally, some non-timer related bits are
located in the TCON SFR. These bits are used to configure the way in which the
external interrupts are activated and also contain the external interrupt flags which are
set when an external interrupt has occurred.

TMOD (Timer Mode, Addresses 89h): The Timer Mode SFR is used to configure the
mode of operation of each of the two timers. Using this SFR your program may
configure each timer to be a 16-bit timer, an 8-bit auto reload timer, a 13-bit timer, or
two separate timers. Additionally, you may configure the timers to only count when an
external pin is activated or to count "events" that are indicated on an external pin.

TL0/TH0 (Timer 0 Low/High, Addresses 8Ah/8Ch): These two SFRs, taken together,
represent timer 0. Their exact behavior depends on how the timer is configured in the
TMOD SFR; however, these timers always count up. What is configurable is how and
when they increment in value.

TL1/TH1 (Timer 1 Low/High, Addresses 8Bh/8Dh): These two SFRs, taken together,
represent timer 1. Their exact behavior depends on how the timer is configured in the
TMOD SFR; however, these timers always count up. What is configurable is how and
when they increment in value.
P1 (Port 1, Address 90h, Bit-Addressable): This is input/output port 1. Each bit of this
SFR corresponds to one of the pins on the Microcontroller. For example, bit 0 of port 1
is pin P1.0, bit 7 is pin P1.7. Writing a value of 1 to a bit of this SFR will send a high
level on the corresponding I/O pin whereas a value of 0 will bring it to a low level.

SCON (Serial Control, Addresses 98h, Bit-Addressable): The Serial Control SFR is
used to configure the behavior of the 8051's on-board serial port. This SFR controls the
baud rate of the serial port, whether the serial port is activated to receive data, and also
contains flags that are set when a byte is successfully sent or received.

Programming Tip: To use the 8051's on-board serial port, it is generally necessary to
initialize the following SFRs: SCON, TCON, and TMOD. This is because SCON controls
the serial port. However, in most cases the program will wish to use one of the timers to
establish the serial port's baud rate. In this case, it is necessary to configure timer 1 by
initializing TCON and TMOD.

SBUF (Serial Control, Addresses 99h): The Serial Buffer SFR is used to send and
receive data via the on-board serial port. Any value written to SBUF will be sent out the
serial port's TXD pin. Likewise, any value which the 8051 receives via the serial port's
RXD pin will be delivered to the user program via SBUF. In other words, SBUF serves
as the output port when written to and as an input port when read from.

P2 (Port 2, Address A0h, Bit-Addressable): This is input/output port 2. Each bit of this
SFR corresponds to one of the pins on the Microcontroller. For example, bit 0 of port 2
is pin P2.0, bit 7 is pin P2.7. Writing a value of 1 to a bit of this SFR will send a high
level on the corresponding I/O pin whereas a value of 0 will bring it to a low level.

Programming Tip: While the 8051 has four I/O port (P0, P1, P2, and P3), if your
hardware uses external RAM or external code memory (i.e., your program is stored in
an external ROM or EPROM chip or if you are using external RAM chips) you may not
use P0 or P2. This is because the 8051 uses ports P0 and P2 to address the external
memory. Thus if you are using external RAM or code memory you may only use ports
P1 and P3 for your own use.

IE (Interrupt Enable, Addresses A8h): The Interrupt Enable SFR is used to enable
and disable specific interrupts. The low 7 bits of the SFR are used to enable/disable the
specific interrupts, where as the highest bit is used to enable or disable ALL interrupts.
Thus, if the high bit of IE is 0 all interrupts are disabled regardless of whether an
individual interrupt is enabled by setting a lower bit.
P3 (Port 3, Address B0h, Bit-Addressable): This is input/output port 3. Each bit of this
SFR corresponds to one of the pins on the Microcontroller. For example, bit 0 of port 3
is pin P3.0, bit 7 is pin P3.7. Writing a value of 1 to a bit of this SFR will send a high
level on the corresponding I/O pin whereas a value of 0 will bring it to a low level.

The Microcontroller design consist of two parts

1) Hardware.
2) Software.

HARDWARE: The controller operates on +5 V dc, so the regulated +v 5 v is

supplied to pin no . 40 and ground at pin no. 20. The controller is used here need not
required to handle high frequency signals, so as 4 MHz crystal is used for operating the
processor. The pin no. 9 is supplied with a +5V dc through a push switch. To reset the
processor .As prepare codes are store in the internal flash memory the pin no. 31 is
connected to + Vcc.

C. LED INDICATOR
The indicator section consists of a light emitting diode and its driver circuit is designed
on the basis of current required to glow the light emitting diode. Here the driver circuit is
required for the following functionality.
1) The Microcontroller cannot provide adequate current for glowing the LED. The
LED’s requires a current between 10mA to 20mA of current to glow.
2) The driver circuit provides current to the load from a separate source, so the load
current used not pass through the Microcontroller.
3) The driver circuit activates the load on receipt of a logic signal from the
Microcontroller and of the load in the absence of the signal as he current
requirement Is very less to glow a LED a single stage driver is sufficient to drive
the load. The driver circuit is nothing other than a perfect a transistor switch. The
driver transistor goes in to saturation on receipt of base signal and drives into
cut-off region, in absence of base signal.
The driver designs around a BC548/BC547 transistor and designed for a working
voltage of +5 V dc and 10mA current.
Rc= Vcc-VCEsat = 5-0.2V
IC 10mA
= 4.8KΩ
Ib=Ic/β =10mA/200=5x10-5 A=0.5x10-6A
=0.5µ A
As per the design a 0.5µ A current is sufficient to trigger the driver circuit. As this
current is very small and to avoid mistriggering a base current of 100µ A is assumed
VB-IBRB-VBE=0 ⇒ IBRB = 5-0.7
 RB = 5-0.7V/100µ A = 4.3/100 MΩ
= 0.043x10-6Ω = 43KΩ
On approximation 68K is connected by calculating back
IB = 4.3/68K = 60≅ 70µ A
Which is adequate to avoid mis-triggering level also this amount of current can be
drawn from the Microcontroller without any problem.The indicator section consists of
8 no of driver with 8 no of LED as indicator load. The circuit diagram is enclosed.
Whenever there is a fault in any of the condition (parameter) it indicates a high
output at the Microcontroller, which is given to the base of the driver transistor
(BC547/BC548) with a base resistance (68k/56k) & thus transistor
r comes to saturation condition i.e. ON condition, thus the emitter current flows to the
collector of the transistor at which the LED is connected through a current limiting
resistor (330E/470E) thus the LED gets forward biased which turns ON the LED it
indicates the channels fault .

D) BIDIRECTIONAL MOTOR DRIVER

ELECTRO MAGNETIC RELAY
These are very much reliable devices and widely used on field. The operating
frequency of these devices are minimum 10-20ms.That is 50Hz – 100Hz.The relay
which is used here can care 7mA currents continuously. The electromagnetic relay
operates on the principle magnetism. When the base voltage appears at the relay driver
section, the driver transistor will be driver transistor will be driven into saturation and
allow to flow current in the coil of the relay, Which in turn create a magnetic field and the
magnetic force produced due to that will act against the spring tension and close the
contact coil. Whenever the base voltage is withdrawn the transistor goes to cutoff .So
no current flow in the coil of the relay. Hence the magnetic field disappears so the
contact point breaks automatically due to spring tension. Those contact points are
isolated from the low voltage supply, so a high voltage switching is possible by the help
of electromagnetic relays.
The electromagnetic relays normally having 2 contact points. Named as normally closes
(NC) NO normally open (NO). Normally closed points will so a short CKT path when the
relay is off. Normally open points will so a short CKT path when the relay is energized.
Circuit operation:

Here the relay drivers are used for the controlling of the car due to the right and left
obstacle. At normal condition, the output of the AND & OR gate are LOW due to which
both of the relays is in OFF state or de-energized means the contactor point i.e. COM &
NC is in that position means is in same potential. That output signal is given to the bi-
directional dc motor driver through a NOT gate, means at the normal condition both of
the relay driver is in OFF condition, thus the output of the NOT gate are normally HIGH
which drives the both of the DC motor is in forward direction through Bi-directional DC
motor driver. The operation of the relay driver is given below:
This application is in some ways a continuation of he discussion introduced for diodes
how the effects of inductive kick can be minimized through proper design. In the below
figure (a), a transistor is used to established the current necessary to energize the relay
in the collector circuit. With no input at the base of the transistor, the base current,
collector current, and the coil current are essentially 0A, and the relay sits in the
unexercised state (normally open, NO).
However when a positive pulse is applied to the base, the transistor turns ON,
establishing sufficient current through the coil of the electromagnet to close the relay.
Problem can be now develop when the signal is removed from the base to turn OFF the
transistor and de-energized the relay. Ideally, the current through he coil and the
transistor will quickly drop to zero, the arm of the relay will be released, and the relay
will simply remain dormant until the next “ON” signal. However we know from our basic
circuit courses that the current through the coil cannot change instantaneously, and in
fact the more quickly changes, greater the induced voltage across the coil as defined
by,
VL = L (diL / dt).

In this case, the rapid changing current through the coil will develop a large voltage
across the coil with the polarity shown in figure (a), which will appear directly across the
output of the transistor. The chances are likely that its magnitude will exceeds the
maximum ratings of the transistor, and the semiconductor device will be permanently
damaged. The voltage across the coil will not remain at its highest switching level but
will oscillate as shown until its level drops to zero as the system settles down.
The destructive action can be subdued by placing a diode across the coil as shown in
below figure (b). During the “ON” state of the transistor, the diode is back biased: it sits
like an open circuit and does not affect the thing. However, when the transistor turns
“OFF”, the voltage across the coil will reverse and will forward biased the diode, placing
the diode in its “ON” state. The current through the inductor established during “ON”
state of the transistor can then continue to flow through the diode, eliminating the
severe change in current level. Because the inductive current is switched to diode
almost instantaneously after the “OFF” state is established, the diode must have a
current rating to match the current through the inductor and the transistor when is in
“ON” state. Eventually, because of the resistive elements in the loop, including the
resistance of the coil windings and the diode, the high frequency (quickly oscillating)
variation in voltage level across the coil will decay to zero and the system will settle
down.
 V c c = + 1 2 v
10uF

RELAY
1N4007

1 . 5 k
B C 5 4 7 +

V c c = + 1 2 v
M
V c c = + 1 2 v

-
10uF

RELAY
1N4007

1 . 5 k
B C 5 4 7

D C M O T O R D R I V E
E. DC Motor driver
The D.C. Motor used in this project operates at 12 volt and carries approximately
400mA of current. The motor driver is designed to inter face the motor with TTL logic.
The TTL output is +12volt and can maximum give a current of 25µA. The driver stage
changes the current and voltage level suitably to drive the motor. The driver stage not
only drives the motor but also helps to control the direction of rotation. As the output
current (Ic) is large the driver section requires a Darlington pair to switch the load. The
Darlington pair I.C. TIP 122 is used here for designing. Here the driver stage is
configured as a Emitter Follower (C.C) configuration for impedance matching and the
output is given to the Dc motor to drive the motor smoothly.

F ) RELAY DRIVER
The relay driver is design by using a BC547 transistor .The relay used here having
the specification as follows
 Coil resistance =400ohm
 Coil voltage=12Vdc
 Contact capacity=230V, 7A

The above specification indicates that the coil requires 12V dc and 200mA current dc.
The Microcontroller can’t supply more then 10mA current. So driver section is very
much required. BC547 has a typical current gain of 200 and maximum current capacity
of 1A. So a typical base current of 200 µ A can trigger to on the relay.

ELECTRO MAGNETIC RELAY

These are vary much reliable devices and widely used on field. The operating
frequency of these devices are minimum 10-20ms.That is 50Hz – 100Hz.The relay
which is used here can care 25mA currents continuously. The electromagnetic relay
operates on the principle magnetism. When the base voltage appears at the relay
driver section, the driver transistor will be driver transistor will be driven into saturation
and allow to flow current in the coil of the relay, Which in turn create a magnetic field
and the magnetic force produced due to that will act against the spring tension and
close the contact coil. Whenever the base voltage is withdrawn the transistor goes to
cutoff .So no current flow in the coil of the relay. Hence the magnetic field disappears
so the contact point breaks automatically due to spring tension. Those contact points
are isolated from the low voltage supply, so a high voltage switching is possible by the
help of electromagnetic relays.
The electromagnetic relays normally having 2 contact points. Named as normally
closes (NC), normally open (NO). Normally closed points will so a short CKT path
when the relay is off. Normally open points will so a short CKT path when the relay is
energized.

R E L A Y D R I V E R

V C C

5
3
4
1
2
IN 4 0 0 7
1 0 u F R E L A Y S P D T

1 .5 K
DATA
INPUT B C 5 4 7

G) DTMF ENCODER

Introduction to DTMF
DTMF means: Dual Tone Multi-Frequency, There is no base band multiplexing done on
DTMF signals. The signal generated by a DTMF encoder is a direct algebraic
summation, in real time, of the amplitudes of two sine (cosine) waves of different
frequencies. i.e. pressing '1' will send a tone made by adding 1209 Hz and 697 Hz to
the other end of the line.

What frequencies used for touch tones numbers

The touch tone system uses pairs of tones to represent the various keys. There is a
"low tone" and a "high tone" associated with each button (0 through 9, plus * (star) and
#. The low tones vary according to what horizontal row the tone button is in, while the
high tones correspond to the vertical column of the tone button.

The tones and assignments are as follows:

Matrix Key Board Form:

or:
1209 Hz 1336 Hz 1477 Hz 1633 Hz

ABC DEF
697 Hz 1 2 3 A

GHI JKL MNO

770 Hz 4 5 6 B

PRS TUV WXY

852 Hz 7 8 9 C
 oper
941 Hz * 0 # D

Algebric/ Mathematical Form

1 697+1209
2 697+1336
3 697+1477
4 770+1209
5 770+1336
6 770+1477
7 852+1209
8 852+1336
9 852+1477
0 941+1336
* 941+1209
# 941+1477
A 697+1633
B 770+1633
C 852+1633
D 941+1633

When the 4 button is pressed, the 770 Hz and 1209 Hz tones are sent together from the
DTMF encoder. The DTMF decoder decodes the tone and generates the equivalent of
the key number at the output.

The tone frequencies were designed to avoid harmonics and other problems that could
arise when two tones are sent and received. Accurate transmission from the encoder
and accurate decoding on the decoder is important. They may sound rather musical
when dialed (and representations of many popular tunes are possible).

The tones should all be +/- 1.5% of nominal. The high frequency tone should be at least
as loud, and preferably louder than the low frequency. It may be as much as 4 db
louder. This factor is referred to as "twist." If a Touchtone signal has +3db of twist, then
the high frequency is 3 db louder than the low frequency. Negative twist is when the low
frequency is louder.

The A, B, C and D touch tone keys and their function:

These are extensions to the standard touch-tones (0-9, *, #) which originated with the
U.S. military's Autovon phone network. The original names of these keys were FO
(Flash Override), F (Flash), I (Immediate), and P (Priority) which represented priority
levels that could establish a phone connection with varying degrees of immediacy,
killing other conversations on the network if necessary with FO being the greatest
priority, down to P being of lesser priority. The tones are more commonly referred to as
the A, B, C and D tones respectively, and all use a 1633 Hz as their high tone.

Nowadays, these keys/tones are mainly used in special applications such as amateur
radio repeaters for their signalling/control. Modems and touch tone circuits tend to
include the A, B, C and D tones as well. These tones have not been used for general
public service, and it would take years before these tones could be used in such things
as customer information lines; such services would have to be compatible with the
existing 12-button touch tone sets in any case.

In DTMF, the tone '8' is represented with the sum of 852 Hz and 1477 Hz sinusoids. We
understand that the energy of the sinusoids present in the generated tone should
exceed the energy present at any other frequencies by 30dB. Also, notice that the
DTMF frequencies are effectively divided into two subsets. One contains the lower four
frequencies, and the other contains the upper four. Each DTMF tone is defined by the
presence of exactly one of the frequencies from each of those subsets.
CCITT DTMF Recommendations
Frequency Tolerance: Operation: <= 1.5%
Non-Operation: >= 3.5%
Signal Duration: Operation: 40ms max
Non-Operation: 23ms min
Signal Interruption: 10ms max
Twist: Normal: 8db max
Reverse: 4db max
We assume these recommendations are among the most noteworthy, mostly because
they are mentioned in our sources, especially

It took us a while to decide what the each of the recommendations mean. Any
frequency within 1.5% of the DTMF frequency should be detected. Frequencies with
3.5% error should never be detected. Inside the 1.5% - 3.5% range is a don't care.
DTMF signals lasting 40ms should always be detected. Signals less than 23ms should
never be detected. Inside the 23ms-40ms range is a don't care. DTMF signals that are
interrupted for 10ms or less should not detect two separate signals. Twist is caused by
a non-uniform power loss across the frequency spectrum. Normal twist is when low
frequency power is greater than high frequency. Reverse twist is obviously the reverse
condition. The detector must be reject 8db and 4db for normal and reverse twist
respectively.

We have not found any DSP DTMF implementations that are able to meet these
specifications. Some algorithms come much closer than others, but none meet the
specifications completely. We are attempting to improve upon the current DTMF
implementations and hopefully meet most (if not all) of the CCITT recommendations.
Encoding DTMF:
There are many ways to generate DTMF tone. Using oscillator and filter array is one of
the method also this can be designed by using lookup table in the digital method.
The Integrated IC version is having one key board section, on receiving proper row
column section the tone generator section generator generates DTMF tone output.

Encoder IC Operation:

The DTMF encoder IC UM91214B/ UM91215B based circuit generates DTMF

frequencies as per the key pressed in the keyboard connected to the ROW and
COULMN of the IC. This IC requires 3 volts for its operation. This is provided by a
simple zener diode voltage regulator, which converts 9 volts into 3 volts for use by this
IC. For its time base, it requires a quartz crystal of 3.58 MHz. The Encoder IC Pins 1
and 2 are used as chip select and DTMF mode select pins respectively. When the row
and column pins (12 and 15) are shorted to each other, DTMF tones corresponding to
digit 1 are output from its pin 7.
H) DTMF DECODER

Features:

• Low Power Consumption

• Adjustable Acquisition and Release Times
• Central Office Quality and Performance
• Power-down and Inhibit Modes
• Inexpensive 3.58 MHz Time Base
• Single 5 Volt Power Supply
• Dial Tone Suppression

Applications:

• Telephone switch equipment

• Remote data entry
• Paging systems
• Personal computers
• Credit card systems

Description:
The M-8870 is a full DTMF Receiver that integrates both bandsplit filter and decoder
functions into a single 18-pin DIP or SOIC package. Manufactured using CMOS process
technology, the M-8870 offers low power consumption (35 mW max) and precise data
handling. Its filter section uses switched capacitor technology for both the high and low
group filters and for dial tone rejection. Its decoder uses digital counting techniques to
detect and decode all 16 DTMF tone pairs into a 4-bit code. External component count
is minimized by provision of an on-chip differential input amplifier, clock generator, and
latched tri-state interface bus. Minimal external components required include a low-cost
3.579545 MHz color burst crystal, a timing resistor, and a timing capacitor.The M-8870-
02 provides a “power-down” option which, when enabled, drops consumption to less
than 0.5 mW. The CM-8870 - 02 can also inhibit the decoding of fourth column digits .

Functional Description

CM-8870 operating functions (see block diagram on page 1) include a band split filter
that separates the high and low tones of the received pair, and a digital decoder that
verifies both the frequency and duration of the received tones before passing the
resulting 4-bit code to the output bus.

Filter

The low and high group tones are separated by applying the dual-tone signal to the
inputs of two 6th order switched capacitor bandpass filters with bandwidths that
correspond to the bands enclosing the low and high group tones. The filter also
incorporates notches at 350 and 440 Hz, providing excellent dial tone rejection. Each
filter output is followed by a single-order switched capacitor section that smoothes the
signals prior to limiting. Signal limiting is performed by high gain comparators provided
with hysteresis to prevent detection of unwanted low-level signals and noise. The
comparator outputs provide full-rail logic swings at the frequencies of the incoming
tones.

Decoder

The M-8870 decoder uses a digital counting technique to determine the frequencies of
the limited tones and to verify that they correspond to standard DTMF frequencies. A
complex averaging algorithm is used to protect against tone simulation by extraneous
signals (such as voice) while tolerating small frequency variations. The algorithm
ensures an optimum combination of immunity to talkoff and tolerance to interfering
signals (third tones) and noise. When the detector recognizes the simultaneous
presence of two valid tones (known as signal condition), it raises the Early Steering flag
(ESt). Any subsequent loss of signal condition will cause ESt to fall.

Steering Circuit

Before a decoded tone pair is registered, the receiver checks for a valid signal duration
(referred to as character- recognition-condition). This check is performed by an external
RC time constant driven by ESt. A logic high on ESt causes VC (see block diagram on
page 1) to rise as the capacitor discharges. Provided that signal condition is maintained
(ESt remains high) for the validation period (tGTF), VC reaches the threshold (VTSt) of
the steering logic to register the tone pair, thus latching its corresponding 4-bit code
(see DC Characteristics on page 2) into the output latch. At this point, the GT output is
activated and drives VC to VDD.
GT continues to drive high as long as ESt remains high. Finally, after a short delay to
allow the output latch to settle, the delayed steering output flag (StD)
goes high, signaling that a received tone pair has been registered. The contents of the
output latch are made available on the 4-bit output bus by raising the three state control
input (OE) to a logic high. The steering circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting signals too short to be considered
valid, the receiver will tolerate signal interruptions (dropouts) too short to be considered
a valid pause. This capability, together with the ability to select the steering time
constants externally, allows the designer to tailor performance to meet a wide variety of
system requirements.
Pin Functions:

Pin Name Description:

1 IN+ Non-inverting input Connections to the front-end differential amplifier.

2 IN- Inverting input
3 GS Gain select. Gives access to output of front-end amplifier for connection of
feedback resistor.
4 VREF Reference voltage output (nominally VDD/2). May be used to bias the
inputs at mid-rail.
5 INH* Inhibits detection of tones representing keys A, B, C, and D.
6 PD* Power down. Logic high powers down the device and inhibits the oscillator.
Internal pull down.
7 OSC1 Clock input 3.579545 MHz crystal connected between these pins completes
the internal oscillator.
8 OSC2 Clock output
9 VSS Negative power supply (normally connected to 0 V).
10 OE Tri-statable output enable (input). Logic high enables the outputs Q1 -
Q4. Internal pullup.
11-14 Q1, Q2, Tri-statable data outputs. When enabled by OE, provides the code
corresponding to the last valid tone pair
Q3, Q4 received .
15 StD Delayed steering output. Presents a logic high when a received tone pair
has been registered and the output latch is
updated. Returns to logic low when the voltage on St/GT falls below VTSt.
16 ESt Early steering output. Presents a logic high immediately when the digital
algorithm detects a recognizable tone pair (signal
condition). Any momentary loss of signal condition will cause ESt to return to a logic
low.
17 St/GT Steering input/guard time output (bidirectional). A voltage greater than
VTSt detected at St Causes the device to register the
detected tone pair and update the output latch. A voltage less than VTSt frees the
device to accept a new tone pair. The GT
output acts to reset the external steering time constant, and its state is a function of ESt
and the voltage on St.
18 VDD Positive power supply. (Normally connected to +5V.)

Guard Time Adjustment

Where independent selection of signal duration and inter digit pause are not required,
the simple steering circuit of Basic Steering Circuit is applicable.
Component values are chosen according to the formula:
tREC = tDP + tGTP
tGTP @ 0.67 RC
The value of tDP is a parameter of the device and tREC is the minimum signal duration
to be recognized by the receiver. A value for C of 0.1 µF is recommended
for most applications, leaving R to be selected by the designer. For example, a suitable
value of R for a tREC of 40 ms would be 300 k. A typical circuit using this steering
configuration is shown in the Single - Ended Input Configuration on page 4. The timing
requirements for most telecommunication applications are satisfied with this circuit.
Different steering arrangements may be used to select independently the guard
times for tone-present (tGTP) and tone-absent (tGTA). This may be necessary to meet
system specifications that place both accept and reject limits on both tone
duration and interdigit pause. Guard time adjustment also allows the designer to tailor
system parameters such as talk off and noise immunity. Increasing tREC improves
takeoff performance, since it reduces the probability that tones simulated by
speech will maintain signal condition long enough to be registered. On the other hand, a
relatively short tREC with a long tDO would be appropriate for extremely noisy
environments where fast acquisition time and immunity to dropouts would be required.
Power-down and Inhibit Mode (-02 only)
A logic high applied to pin 6 (PD) will place the device into standby mode to minimize
power consumption. It
Tone Decoding
FLOW FHIGH Key (ref.) OE Q4 Q3 Q2 Q1
697 1209 1 H 0001
697 1336 2 H 0010
697 1477 3 H 0011
770 1209 4 H 0100
770 1336 5 H 0101
770 1477 6 H 0110
852 1209 7 H 0111
852 1336 8 H 1000
852 1477 9 H 1001
941 1336 0 H 1010
941 1209 S 1011
941 1477 # H 1100
L = logic low, H = logic high, Z = high impedance

Decoding DTMF :
There are many ways to detect and decode these DTMF tones. One idea
could be an eight sharp-tuned filter combination with detection circuits.
Needless to say, this is very impractical, considering the various ICs
(Integrated Circuits or 'chips') made by different manufacturers all over the
world.

Most of these ICs do not require more than one (inexpensive) 3.58 MHz x-tal
or resonator and the power circuitry. Usually the output is 4-bit binary + 1
strobe.

Basic Functionality of the DTMF Decoder

Decoder IC Operation.

The FM receiver receives the frequency modulated DTMF signals and the
outputs (DTMF tones) are fed to the dedicated IC KT3170 which is a DTMF-
to-BCD converter. This IC when fed with the DTMF tones gives
corresponding BCD output; for example, when digit 1 is pressed, the output
is 0001 and when digit 4 is pressed the output is 0100. This IC also requires
a 3.58MHz crystal for its operation.
 DTMF DEC ODE R(CM8 870)

V C C = + 5V

1 .5 k
B C 547
P1.0
10k

0 .1 u F
1 .5 k
B C 547
F R O M 100k 330k P1.1
FM RxR 2 16 10k
1M C 0 .1 u F
18
3 M 1 .5 k
B C 547
17
P1.2
4 SYNC 330E
8 15 10k
D 330E
1 8 14
C 330E 1 .5 k
7 7 12 B C 547
B 330E P1.3
0 12
10k
A 330E
8
3.579MHz

11

10 1 .5 k
5 6 9 B C 547
P1.4
10k

SIGNAL CONDITIONING
I) FM transmitter
Introduction to FM broadcasting

Frequency Modulation (FM) is the method of varying a carrier wave's

frequency proportionally to the frequency of another signal, in our case the
human voice. This compares to the other most common transmission
method, Amplitude Modulation (AM). AM broadcasts vary the amplitude of
the carrier wave according to an input signal. Standard FM broadcasts are
based in the 88 - 108 MHz range; otherwise known as the RF or Radio
Frequency range. However, they can be in any range, as long as a receiver
has been tuned to demodulate them.

Thus the RF carrier wave and the input signal can't do much by themselves,
they must be modulated. That is the basis of our transmitter. An example is
useful to illustrate what is actually going on. If we were to broadcast a
100MHz signal and tune a radio into that frequency, we would hear nothing.
That 100MHz signal has locked or captured that spot and simply produces a
DC value. Now if we were to move the incoming signal +/-100KHz in either
direction at a frequency of 1000Hz, then we would hear a 1000Hz signal on
the radio. If we only moved +/-10Khz then the sound from the radio would
be 1/10th the original in loudness. Thus the rate or frequency at which we
change the RF carrier produces the audible frequency that we hear, and the
further from the main RF carrier we move, the louder the output will be. This
is the basis of all FM transmitters. We will now look at how this is achieved
by examining the basic circuit.

It is also important to note that the Federal Communications Commission

(FCC) have very strict rules regarding broadcasting in these ranges. It is
important that you check FCC regulations before attempting to build this
circuit or any similar circuits.

Basic Circuit Operation

Below is a block diagram of our circuit showing the functional elements of an
FM transmitter.

RF Oscillator

The oscillator is the primary subsystem in the telephone bug circuit. It

determines the FM band at which the audio signal is heard (the carrier
frequency). The main components of the oscillator are the transistor (Q1),
the inductor (L1) and capacitors (C2, C3, C4). The oscillator is L-C tuned
meaning that the frequency of oscillation is controlled by the inductance and
capacitance in the circuit. Specifically, inductor, L1, capacitors C2, C3, and
the capacitance in the transistor control the natural resonant frequency of
the oscillator. By fixing the inductor and using a variable capacitor, the
oscillator can be made to resonate between 88Mhz and 108Mhz. Thus the
two component values which radically affect our circuit are the inductor
value, and the capacitance value of C2. We also note that the inductor is
actually 6 inches of 30-gauge enameled wire.

Audio Amplifier

The audio amplifier is used to increase the amplitude of the audio (voice)
signal to boost the range of the transmitted signal. The amplifier is basically
a common-collector transistor amplifier consisting of transistor, Q1, and a
resistor, R1. It is also interesting to note that the load on the transistor is
the oscillator circuit itself. (Smart!)

In order to amplify a signal it takes power. This power is supplied by the

telephone line itself. When the telephone is off the hook a potential of 6-8
volts is found across the red and green wires of the telephone cable. This
potential causes a current to flow through resistor R1 which biases the
transistor Q2 into operation. Any audio frequencies on the telephone line will
be amplified and appear on the collector of the transistor. Q2 is a PNP
transistor since large currents will keep the transistor off. Since when the
telephone is on hook, a potential of ~50V is found across the red and green
wires. The green wire acts the positive supply and the red wire acts as a
circuit ground.

Modulator

The modulator is the subsystem that combines the audio signal with the
carrier signal from the oscillator to allow the audio signal to transmit over
radio waves. As the audio signal fluctuates, the current into the base of the
transistor fluctuates similarly, and changes the capacitance between the
collector and emitter of the transistor Q1. As shown above in the oscillator
circuit, a change in capacitance results in a change in frequency. Therefore,
as the audio signal changes, the frequency changes or modulates.

Antenna

The antenna is used to transmit an electrical signal through the air waves.
The size of the antenna determines the length of broadcast. Our antenna is a
6", 22-gauge wire. We could use a longer one to get a larger broadcast
range but we didn't for a couple reasons. First, the FCC might get upset.
Second, the longer wire would have some inherent capacitance and
impedance that would have to be compensated for by changes to other parts
of the oscillator circuit.

J) FM receiver

It is easily being noticed that this is the receiver with inter-frequency (IF)
amplifier with ZN415 .By adding ZN415 IC multiple enhancements are
performed. Thanks to its huge input resistance, the MFT's oscillatory circuit
is not choked, resulting in better selectivity. The sensitivity of the device is
extremely increased since this IC has big amplification and the AAR
(automatic amplification regulation) is also accomplished, making the usage
of this device is easier and comfortable.

FROM DTMF
ENCODER
 • It is very important to obtain the necessary value of the DC voltage in
pin 6 of the ZN415 for its proper operation. The receiver is set to some
weaker station, the sound volume is made very low with potentiometer
P, and the slider of the TP1 is carefully moved until the best reception
is made. If that doesn't work, one should try changing the value of R5
resistor; this is to be done also if the supply voltage being used is
other than 12 V. In case of voltage on the pin being much bigger than
1.3 V, and cannot be reduced on the trimmer, short-circuit one of the
diodes.
* The voltage stabilizer with 78L06 isn't needed if the receiver is
supplied from the 6 v battery.
• The receiver needs input circuit to be 100% complete. That can be an
independent input circuit, or input circuit and the HF amplifier that are
described .If the former circuit is used, station tuning is being
accomplished with 2 knobs, as explained in the previous chapter.

All the receivers we made with NE612 IC were tested in our lab, except the
one from the previous project, since we didn't have ZN415 "with us". We
found, however, a ZN414 IC, so we tested the receiver with it. The receiver
was working great, from the amateur's point of view. He played us for long
time, until we didn't require the board to test one of the receivers from
previous projects afterwards, when we regretfully had to disassemble it.
* DC voltage setting on pin 1 of ZN414 is done with the trimmer TP. Its
slider is put in mid position; the receiver is tuned to some weaker station
close to the upper bound of the bandwidth. While making the reproduction
very quiet (slider of P as low as possible), the trimmer slider is moved until
reaching optimum reception. After that the trimmer is disconnected, its
resistance measured and the ordinary resistor of similar value is put into
circuit.
* The device operates nicely with the outside antenna made of a piece of
wire measuring only half metres in length.
* The reception would certainly become better if an input circuit would be
added, which we spoke about in the previous project.
4.2. Super heterodyne FM Receivers

The FM receivers are extremely simple devices, that cannot perform the
noiseless tuning, automatic oscillator frequency regulation and other
features that ensure very high quality of the reproduction, being expected
from an UHF FM receiver. The true solution is the super heterodyne FM
receiver, whose block-diagram is given. Station signals are taken from the
dipole antenna and led through the appropriate cable into the input circuit
(UK). Inside it, the signal selection is performed, of station whose frequency
is fS, this signal is then amplified in the HF amplifier and led into the mixer.
As in the case of earlier described AM receiver, the inter-frequency signal is
obtained at the mixer output, whose carrier frequency is fm=10.7 MHz (this
is the standard value, used in all radio-broadcast FM receivers). The IF signal
is being amplified in the IF amplifier and led on the amplitude limiter (Ogr.).
In this stage the signal whose amplitude exceeds certain level is being cut
off, accomplishing with this the elimination of the parasite amplitude
modulation, which is performed by various noise sources during the
transmission (atmospheric charges, various electrical devices etc.), which
significantly improves the signal quality. The signal then goes to the FM
signal detector, where the information being modulated in the transmitter is
extrapolated from the signal, followed by the LF part of the receiver. With
AFC the circuit that performs the automatic frequency regulation of the local
oscillator is labeled.

K. SIGNAL CONDITINIONG

The output form the input signal i.e. comparator or any other external circuit must be
compatible with the µ -controller, because the µ -controller can takes 5V as input
voltage and gives a 5V as output voltage. That for we need a signal conditioning circuit
as given in the below figure.
 SIGNAL CONDITIONING
VC C = +5 v VC C = +5v

INPUT 10k
1 .5 k OUTPUT
B C 547 INPUT
1 .5 k
B C 547
OUTPUT
10k

(1:1) (1:0)

fig..1:1
In the fig1: 1, whenever the base voltage is HIGH the transistor comes to saturation
condition i.e. the collector current flows to the emitter which gives a high voltage at the
output corresponding to Vcc given at the collector. The output is taken from the emitter
junction through a current limiting resistance and the output signal is given to the µ -
controller or any other circuit which needs a compatible (5V) voltage. Similarly,
whenever the base voltage is LOW the emitter current flows from the emitter junction of
the transistor, which gives a low voltage at the output corresponding to GND. The
output is taken from the emitter junction through a current limiting resistance and the
output signal is given to the µ - controller or any other circuit which needs a compatible
(5V) voltage.

fig..1:0
In the fig1: 0, whenever the base voltage is HIGH the transistor comes to saturation
condition i.e. the emitter current flows to the collector which gives a low voltage at the
output corresponding to GND. The output is taken from the collector junction through a
current limiting resistance and the output signal is given to the µ - controller or any
other circuit which needs a compatible (5V/0V) voltage. Similarly, whenever the base
voltage is LOW the collector current flows from the collector junction of the transistor,
which gives a high voltage at the output corresponding to Vcc. The output is taken from
the emitter junction through a current limiting resistance and the output signal is given to
the µ - controller or any other circuit which needs a compatible (5V/0V) voltage.
S I G N A L C O N D I T I O N I N G / N O T G A

V C C

1 0 K

1 . 5 K
D A T A
I N P U T B C 5 4 7

FUTURE EXPANSION

This project is designed with limitation to time and cost. This project can be modified and
advanced further by using IP camera.

CONCLUSION

This project is tested in the laboratory condition and found to be operating satisfactory. The
errors observed frequency overlapping is quit less and it is well bellow the experimental
tolerance level.
 M O T H E R B O A R D
5 V

3 9 2 1
3 8 P 0 . 0 / AP D2 .0 0 2/ A 2 8
3 7 P 0 . 1 / AP D2 .1 1 2/ A 3 9
3 6 P 0 . 2 / PA 2D . 2 /2 A 4 1 0
3 5 P 0 . 3 / PA 2D . 3 /2 A 5 1 1
3 4 P 0 . 4 / PA 2D . 4 /2 A 6 1 2
3 3 P 0 . 5 / PA 2D . 5 /2 A 7 1 3
P 0 . 6 / PA 2D . 6 /2 A 8 1 4 T O S T E P E R M O T O R
F E E D B A C3 K2 P 0 . 7 / PA 2D . 7 / A 1 5 D R I V E R & L E D
1
P 1 . 0
1 0
P 3 . 0 / 1R 1 X D
I N D I C A T O R
2
3 P 1 . 1 P 3 . 1 / 1 T 2X D
4 P 1 . 2 P 3 . 2 / 1I N 3 T 0
5 P 1 . 3 P 3 . 3 / 1I N 4 T 1
6 P 1 . 4 P 3 . 4 1 / T5 0
7 P 1 . 5 P 3 . 5 1 / T6 1
2 2 P F 8 P 1 . 6 P 3 . 6 /1 W 7 R
P 1 . 7 P 3 . 7 / R D
1 9 3 0
4 M H z 1 8 X T A LA 1 L E / P 2 R 9 O G
2 2 P F X T A L 2 P S E N
3 1
9 E A / V P P
R S T
8 .2 K

5 V A T 8 9 C 5 1
10uF

R E S E T S W I T C H
 POWER SUPPLY(+VE)

7812

2.2K

0-12
9 - 0 -V9 V
LE D Vout

7805
1 T1 5
1

IN4007*4
230V 50HZ
4 - + 2
4 8

1K
3

Vout
1000MF/35V
LE D
LED INDICATOR

V C C

3 3 0 E

L E D

6 8 k
DATA
INPUT B C 5 4 7
 R E L A Y D R I V E R

V C C

5
3
4
1
2
IN 4 0 0 7
1 0 u F R E L A Y S P D T

1 .5 K
DATA
INPUT B C 5 4 7
 D T M F E N C O D E R V C C = + 9 --1 2 V

150E

3 . 6 V Z D1 0 0 u F
6
R 1 3
1 5 U
R 2 M 4
3 .5 7 9 M H z

N CN O N CN O N CN O
1 6 9
C 3 1
1 4 2 D T M F O / P
C 2
1 3
1 7

C 1 5
N C N O N C N O N CN O 1 2 B
T O F M
2 1 5 1K T x R
FROM RELAY DRIVER
 ANT.
FM TRA NSMITTER
7 T
2 4 S W G1 0 p F

5 T TRIMMER
24 S W G 7 T 22pF
V C C = + 9V 2 4S W G
15 p F
1 0K p F 1 K pF 2 N 3 8 66
1 K p F B C 5 4 7
1 K p F
C 2 57 0 1 0 p F
1 K 4 T
2 4 SW G
1 0 pF 1K
1K
TRIMMER 1K pF 2 2 E
22pF

V C C = +9 V

4 .7 K 2 .2 u F 1 0 K

1 5K
1 K p F

4 .7 K
FROM DTMF DECO
 D T M F D E C O D E R
V c c = + 5 V

1 0 4
1 0 41 0 0 K
1 0 1 8
2 1 7

1 M C 3 3 0 K
1 6

F R O M F . M
3
R x R M S Y N 3 C3
T O GATEO
TO AND R G A
4 0 E
1 5
8 D 3 3 0 E
1 1 4
8 C 3 3 0 E
7 1 3
7 B 3 3 0 E
1 2
3 .5 7 M H z

0 A 3 3 0 E
8 1 1
5 6 9
T OGATEO
TO AND R G A