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Integrating Analog to Digital Converter

Pratap Tumkur Renukaswamy, Darshan Shetty FH-Kaernten, Carinthia University of Applied Sciences Project: IADC analog frontend design E-Mail: edurenpra001@edu.fh-kaernten.ac.at , edushedar001@edu.fh-kaernten.ac.at

Abstract

This project presents a 10-bit integrating analog to digital converter (IADC) based on dual-slope integrating princi- ple. The input voltage is measured in terms of reference voltage of opposite polarity and the ratio of two time inter- vals. The analog front end of IADC consisting of integrator stage, comparator stage, switches and current references designed using ams-0.35um technology to meet the specifi- cations. The goal of IADC design is to increase the effective number of bits (ENOB) which is achieved by optimising the offset of each stage, gain of integrator stage and switching speed of comparator.

1. Introduction

Dual slope integrating analog to digital converters provide high accuracy and are widely used when a high conversion speed is not required. The critical factors which limits the converter’s performance are the offset and gain of the in- tegrator stage, switching speed and offset of the compara- tor stage [1], [2]. The circuit design for analog frontend including the integrator, comparator [3], switches, current references [4],[5] and test interfaces is done using the ams- 0.35um technology. Figure 1 shows the block diagram of the IADC along with the digital control logic. The operation of the IADC is divided in to two phases, namely integration phase and disintegration phase [6]. The integrator is reset by switch S 3 for a short duration. During integration phase input signal V in is applied by switch S 1 for a constant duration of T 1 , where T 1 corresponds to time of a 10-bit counter. The output voltage of integrator will ramp up linearly from its defined common mode level with the input value as follows:

V out (T 1 ) =

RC

1

1

(V in )dt =

T

T

RC · V in

1

During the disintegration phase switch S 1 is off and fixed reference voltage V ref of opposite polarity is connected to

voltage V r e f of opposite polarity is connected to Figure 1: IADC block diagram

Figure 1: IADC block diagram

integrator stage by switch S 2 . The integrator’s output will be disintegrated with a constant slope until it is equal to its defined common mode level, so change in output is zero. If time required for this process is T 2 , then :

V out (T 2 ) =

T

RC · V in +

1

T 2 =

V in · T 1

V ref

RC

2

T

1

1

T

(V ref )dt = 0

Thus the error due to RC mismatch is compensated in IADC using dual slope principle.

2. Differential Integrator

The integrator stage consists of a differential amplifier with input resistors and capacitors in the feedback. The ideal differential amplifier has infinite gain and zero offset. The accuracy of the IADC is limited by the gain and offset of the differential amplifier of the integrator stage. An offset voltage affects the slope of integration. With an off- set of V , the following equation is obtained for T 1 and T 2 :

V in + V · T 1 + V ref V

RC

RC

Accordingly,

· T 2 = 0 .

V in

V ref

= (1

1

V ref ) · T 2

V

T

V

V ref .

The gain affects the slope of integration and also adds non-linearity in the output during integration and disinte- gration phases. With a gain of A, the following equation is obtained for T 1 :

V out =

1

A )

1

(V in + V out

1

A

T

RC(1+

2.1

Implementation

)dt .

The output voltage level for the maximum allowed input voltage and fixed integration phase defines the value of input resistor and feedback capacitors. The output voltage magnitude at the end of integration phase at T 1 without gain and offset errors is :

V out =

T

RC · V in

1

.

For 10 bit IADC the time T 1 = 2 10 · T clk . For clock fre- quency of 50MHz , T clk = 20ns. Allowing a maximum output voltage change of 0.36V for the maximum input volt- age of 0.5V , the value of RC = 28us. The value chosen for R = 4M and C = 7pF to meet the area requirements of final IADC. The maximum output voltage change of 0.36V

is assumed to keep all the transistors of differential ampli- fiers in saturation under all worst case conditions. The high value of R reduces the current during the integration cycles

and becomes difficult to distinguish leakage current

and input current on silicon , which is not modelled in the

simulator. Figure 2 shows the proposed circuit for differential ampli- fier. It consists of NMOS differential input pair (MN0 and MN1) with PMOS current source load (MP0 and MP1) to maximise the gain. The small signal gain is given by :

by V in

R

A v = gm n · (r 0n ||r 0p ) .

where gm n and r 0n is transconductance and output resis- tance of input differential pair and r 0p is output resistance on PMOS current source load. Simplifying the above equa- tion yields :

A v =

A v =

2I

d

V

e

ff

·

(

λn·I d || λp·I d ) ,

1

1

2

V

e

ff · (

λn+λp ).

1

Thus to maximise the gain reduce channel length modula- tion λn and λp by increasing the length of transistors and reduce V ef f of input differential pair by increasing the W ratio of input differential pair for given current I ss defined by MN2.

L

pair for given current I s s defined by MN2. L Figure 2: Differential amplifier of

Figure 2: Differential amplifier of integrator stage

The output common mode voltage V cm is applied to transistor MN5 , which defines the V GS for the differential pair during the reset phase when switch S 3 is ON. The input NMOS differential pair act as MOS diode with V G = V D during reset phase and the gate input of MN5 which is V cm appears at the output. Thus transistors MN5 and MP2 act as feedback loop with very high loop gain to keep the output common mode fixed. The feedback loop transistors MN5 and MP2 should have same dimensions as MN0 and MP0 to keep the output common mode fixed. This adds additional area on the chip at the expense of well defined output common mode of the differential amplifier, which is necessary for proper operation of the comparator.

By choosing the I ss = 60uA for the differential ampli- fier with above feedback structure defined by the transistor MN2 and for achieving the gain of A dd = 600 and to meet the output voltage swing of integrator the dimensions of dif- ferent transistors are obtained as shown in Table 1.

Table 1: Dimensions of transistors in differential amplifier

Component Name

W/L(um/um)

NG

MN0, MN1, MN5

300/2.5

15

MP0, MP1, MP2

50/5

5

MN2

150/1

15

MN4

50/1

5

The minimum output voltage of amplifier is V incm V tn , limited by input common mode voltage and threshold voltage of NMOS differential pair. The maximum output

voltage is V dd V DSsatp , is limited by the overdrive voltage of PMOS current source load. For above transistor dimensions V DSsatp = 0.4V .

The offset of the differential amplifier can be reduced by increasing the area W L of the NMOS differential pair. The one sigma of offset due to threshold mismatch is given by:

(1σ) =

A

vt

W·L

For the above dimensions of NMOS differential pair W L = 750um 2 , the one sigma of offset due to threshold mis- match is 0.35mV for ams-0.35um technology. The offset is reduced at the expense of transistor area.

2.2 Simulation Results And Discussion

The differential amplifier is designed using ams 0.35um technology and simulated using cadence spectre simulator. Table 2 shows the variation of differential gain and output common mode voltage for different process corners (tm, ws, wp, wo, wz), supply voltages (3V to 3.6V), designed widlar current reference (section 5), V cm (1.3 to 1.7) and tempera- ture (0 C to 70 C) variations.

Table 2: Amplifier parameters for different corners

Parameters

Min

Nominal

Max

Differential Gain (V/V)

506

606.9

648.5

V outcm (V)

1.301

1.501

1.702

From Table 2 the output common mode voltage is stable for all different corners due to the feedback loop formed by MN5 and MP2.

The effect of transistor mismatch on the differential gain A dd , common mode to differential gain A cd , differential gain due to power supply noise A V dd output common mode voltage V outcm and offset is studied using the monte carlo simulations for worst conditions of V cm = 1.3V , 70 C tem- perature, designed widlar current reference(section 5) and 3V supply. Table 3 summarises the results and Figure 3 shows the histogram of amplifier parameters due to mis- match. From Table 3 , CMRR = A dd,mean = 30, 685.95 =

89.73dB and P SRR =

A

cd,mean

A

dd = 1.18M .

dd

A V

Figure 4 shows the output of integrator during integration and disintegration phases along with the control signals to switches S 1 , S 2 and S 3 for the input of v in = 0.5V . The maximum output voltage change is 0.36V for v in = 0.5V . The ideal crossing of integrator should be at 41.06us.

Table 3: Amplifier parameters due to mismatch

Parameters Measured

Min

Max

Mean

Sigma 1σ

A dd (V/V)

532.9

604.9

572.6

15.1

A cd (V/V)

14.56u

234m

18.66m

16.45m

A V dd (V/V)

0

2.42n

127.7p

402.3p

V outcm (V)

1.3

1.303

1.301

484.7u

Offset (V)

-1.377m

1.403m

-6.087u

468.1u

Offset (V) -1.377m 1.403m -6.087u 468.1u (a) A d d Histogram (c) Offset Histogram (b) V

(a) A dd Histogram

1.403m -6.087u 468.1u (a) A d d Histogram (c) Offset Histogram (b) V o u t

(c) Offset Histogram

468.1u (a) A d d Histogram (c) Offset Histogram (b) V o u t c m

(b) V outcm Histogram

(c) Offset Histogram (b) V o u t c m Histogram (d) A c d Histogram

(d) A cd Histogram

Figure 3: Histogram of amplifier parameters

Table 4 shows the integrator cross during disintegration phase and LSB error in time due to integrator alone for dif- ferent process corners (tm, ws, wp, wo, wz), supply voltages (3V to 3.6V), designed widlar current reference (section 5), V cm (1.3 to 1.7) and temperature (0 C to 70 C) variations for maximum input differential peak of v in = 0.5V .

Table 4: Integrator cross for different corners

Parameters

Min

Nominal

Max

Ideal value

Integrator Cross (us)

40.80

41.05

41.08

41.06

LSB Error

-12.80

-0.236

0.879

0

(us) 40.80 41.05 41.08 41.06 LSB Error -12.80 -0.236 0.879 0 Figure 4: Integrator operation

Figure 4: Integrator operation

The maximum LSB error occurs at transistors, resistors and capacitors are at worst power process corner, supply voltage of 3V, V cm = 1.3V and temperature of 70 C. Figure 5 shows the operation of integrator at above corner. The value of R = 2.889M and C = 6.356pF at worst power corner and RC slope decreases RC = 18.36u allowing V out to increase up to 0.55V for v in = 0.5V . The NMOS transistor threshold voltage will be around 0.4V for worst power process corner and decreases with increase in temperature. The minimum output voltage on the integrator differential amplifier to be in saturation is limited by V incm V t , and in this case V out minimum reduces further and LSB error increases as transistor goes out of sat- uration. This can be overcomed by decreasing the RC slope.

uration. This can be overcomed by decreasing the RC slope. Figure 5: Integrator operation at worst

Figure 5: Integrator operation at worst corner

Table 5 shows the integrator cross during disintegration phase and LSB error in time of integrator alone due to tran- sistor mismatch at supply voltage of 3V , designed widlar current reference (section 5), V cm = 1.3V and temperature of 70 C for maximum differential input peak of v in = 0.5V is studied using the monte carlo simulations. The LSB error is dominated by amplifier offset.

Table 5: Integrator cross due to mismatch

Parameters Measured

Min

Max

Mean

Sigma 1σ

Integrator Cross (us)

40.95

41.17

41.06

0.03267

LSB error

-5.704

5.333

-217.9m

1.634

3 Latched Comparator

Latched comparator is designed with 2 stages with an ini- tial pre-amplification stage followed by a track and latch stage. Pre-amplifier is designed to minimize effects of kickback and obtain a higher resolution. Track and latch stage on the other hand is a positive feedback stage which regenerates

the analog input to a digital output of VDDA or VSSA. Table 6 summarizes the input of the comparator based on which it needs to be designed.

Table 6: Comparator operating conditions

Parameter

Typical

Min

Max

V outd-Integrator

0

-0.5

0.5

Vsupply

3.3

3

3.6

V out CM -Integrator

1.5

1.3

1.7

3.1

Pre-amplifier

The gain is chosen between a value of 3 to 10 which ensures that it is not high enough to reduce the switching time of the comparator. The main advantage as seen in Figure 6 below is the reduction of charge kickback. This phenomenon occurs because of the high switching of the output node of comparator due to which charge is injected onto the input node of the comparator. Since, this is a sensitive device, this has a huge impact on the performance of the comparator. Pre-amplifier, which could also be a source-follower, helps to disconnect the input node from the output.

To achieve, a controllable output common mode voltage of the device, a differential amplifier with MOS diode is chosen. The limitation of this approach is lower gain.

However, the advantage of this circuit is that output CM is insensitive to input CM variation (1.3 to 1.7V). Since, the PMOS on top is a MOS diode, the PSRR is 1 which implies that the Vout-CM follows the Vsupply.

The main concern of the first stage is the input referred offset. Ways of solving the offset issues are by zeroing techniques or by implementing chopper circuits. However, these circuits involve the usage of external capacitors to store the offset charge. For the speed of the comparator of 20Mhz, Cgate cannot be used which is very low, as opposed to the requirement of a capacitor in the range of 1-10pF. Poly capacitor cannot be used as well considering the limitation of the circuit area.

The below given equations give a good approximation of the offset arising from the Pre-amplifier stage. I d = 0.5 µC ox W n /L n (V op V dd + V tp ) 2

V os = ((V eff n /V eff p ) V tp) 2 + ∆V tn 2

As seen here, increasing V eff p , and reducing the mis- match in threshold voltage of the NMOS and PMOS is the best way to reduce the offset. This is done by scaling up

Figure 6: Schematic comparator the width and length of the transistors. 3.2 Track and Latch

Figure 6: Schematic comparator

the width and length of the transistors.

3.2 Track and Latch stage

The track and latch stage of a comparator takes in the amplified signal from the pre-amplifier and amplifies this signal further during the track phase, and then re-amplifies during the latch-phase, when poistive feedback is enabled. With the outptut of this, a fully digital value of Vsupply or GND is generated which is then used by the digital blocks to sample the analog input at the integrator. The principle requirements of this stage are regenerative latches for faster settling and large gain for resolving small inputs. However, this is trade-off between speed and power consumption. The time constant of the circuit is given by τ latch = τ/(A v 1) τ latch = C L /G m = C L V eff /I d Since, Id is more or less fixed by the current mirror, the time constant is now more or less dependent on the sizes of the transistors and Veff. This gives a general idea that the transistor dimensions need to be small to ensure a small time constant.

There are 2 main aspects to the design of the latch phase as seen in Figure 6 below. The transistors MP7, MP5, MP0, MP4 act as current mirrors in the given circuit which removes the need to use a current souce on top/bottom to generate the fixed current for the track and latch stage. The advantage of this design is the added headroom achieved which helps to ensure that all transistors are in saturation for all corners of Vsupply and Vin-CM. In order to avoid hysterisis situation, switches are added during the track phase to reset the output nodes to a pre-defined value. During the high phases of the clock, the switches I49,I50 are closed which brings the output node closer to GND. During the latch phase, the switches are opened and the immediately the output nodes come to the swtiching point

and immediately depending on the input at MP5 and MP4, the nodes Outp and Outn go to either of the extreme values. This value is now taken by the DFF which sends out a digital value. Dummy load has been added on the node Outn to ensure balanced loads at both the output nodes.

Offset of the track and latch stage is not of high concern because it gets divided by the gain of the pre-amplifier of the first stage. For offset, primary goal is to reduce the mismatch occurring from the first stage of the comparator.

Another aspect of the design is the usage of differential switches instead of 1 switch between the 2 output nodes. The differential switches negate the charge injection prob- lems at the input nodes because of the equal transfer of charge for each of the nodes. As a result, the charge in- jection which happens due to the fast switching of the input clock is avoided. However, this comes with a disadvantage that the output nodes are now shorted to GND instead of the tripping point during the track phase.

3.3

Implementation

1>MN0 uses a ratio of width of 5:1 to MN6 which increases the current 5 fold from 20uA to 100uA. 2>W/L of transistors MN4, MN7 mainly change the value of Vds of MN0. W/L are chosen accordingly to ensure that this node is always high enough for the input common-range as a result of which the current mirror MN0 is always in saturation. 3>Gain of the pre-amplifier is gmn4/gmp0 which eventu- ally comes to V ef fp0 /V ef fn4 . 4>In the latch stage, MP7 and MP5 mirror the current onto the second stage. Hence they are given the same width and length. 6>However, the value of the output node at its tripping point is defined by MN3, MN5 which helps to ensure

that this node is independent of Vsupply as seen in the table above. This being independent of Vin-CM makes this tripping point almost constant over all the external parameters. 7>W/L of MN3, MN5 are kept low to ensure that the regenerative latch phase has a low capacitive load which reduces the time constant of the circuit.

The tables below summarise the dimensioning strategy and the DC operating point of the standalone comparator.

Table 7: Comparator transistor dimensioning

Component name

W/L (um)

Id (uA)

MN6

16/2

20

MN5

80/2

100

MN4, MN7

160/2

50

MP0, MP7, MP5, MP4

20/3.5

50

MN5, MN3

20/1.5

50

Table 8: Comparator DC-operating point

Vsup

Vds-MN5

Vgs-MN5

Vout-Stage1

Outp

3.3

0.5V

0.840V

1.8

1.01

3

0.498

0.838

1.5

1.0

3.6

0.495

0.843

2.1

1.0

3.4 Simulation results

Switching behaviour of the comparator is shown at the end of the report which includes the simulation of the en- tire IADC. Corner simulation was done for the standalone comparator by varying Vsupply from 3V to 3.6V, temper- ature from 0 to 70 Degrees and CMOS process parameter from cmos-typical mean, worst speed and worst power and changing the poly resistor from worst power to worst speed. The offset was measured by capturing the input value for which the comparator switched from high to low and vice- versa.

Table 9: Comparator input referred offset-Corner analysis

Parameter variation

Min

Max

V

off lowhigh

-259uV

645uV

V

off highlow

157.2uV

823uV

The critical conclusion from the exercise is the maximum value which is roughly 800uV which is less than 2 LSB loss of the IADC. The corner for which this offset is obtained is at low temperature, cmosws, resws which is expected

considering that the transistors are slow which leads to delayed switching. The fastest corner on the other hand is high temperature coupled with cmoswp, reswp which leads to earlier switching of the comparator.

Monte-carlo analysis was done on the comparator to see the effects of mismatch on the offset of the comparator for low to high and high to low switching. The result is attached in the figures 7,8 below.

switching. The result is attached in the figures 7,8 below. Figure 7: Comparator Monte Carlo: Offset

Figure 7: Comparator Monte Carlo: Offset for Low to High switch

7: Comparator Monte Carlo: Offset for Low to High switch Figure 8: Comparator Monte Carlo: Offset

Figure 8: Comparator Monte Carlo: Offset for High to Low switch

With the mismatch included the 3 sigma value comes to less than 2mV which is 4 LSB loss of the ADC. The mismatch can be reduced further at the loss of the speed of the comparator.

3.5

Limitation

1>Charge injection is a critical issue with the comparator which cannot be completely avoided. With the integrator

included, the charge injection comes to 1mV which is high enough for an erroneous switching of 2LSBs. 2>The usage of differential switch in the design makes the switching of logic from 0 to 1 faster as compared to the switching of logic from 1 to 0. This is because the circuit stays in 0 during the reset phase.

4 Transmission Gate Switch

The switches S 1 , S 2 and S 3 used for the integrator opera- tions are designed using the transmission gate. The advan- tage of transmission gate switch is high dynamic range , less charge injection and clock feedthrough. The ON resistance of switch S 3 along with the integrating capacitor C = 7pf determines the reset time of the IADC.

4.1 Implementation

The ON resistance of the NMOS and PMOS transistor for small V DS is given by:

R ON,n =

1

µn·C OX ·(W/L)·(V GS V tn )

R ON,p =

1

µp·C OX ·(W/L)·(V GS V tp )

The switching time depends of ON resistance of switch R ON and the load capacitance C L given by:

τ = R ON C L .

Thus decreasing the ON resistance by increasing tran- sistor W/L ratio increases the load capacitance and hence the switching time. Also increasing the W/L increases the clock feedthrough. Thus there is a trade off between the transistor dimensions and switching time.

Table 10 shows the dimensions of the transmission gate along with inverter as implemented in Figure 9.

Table 10: Dimensions of transmission gate switch

Component Name

W/L (um/um)

NG

MN1

5/0.4

1

MP1

12/0.4

2

MN0

0.7/0.4

1

MP0

2/0.4

1

4.2 Simulation Results And Discussion

Figure 10 shows the variation of R ON of a transmission gate switch when V AB is varied from 0 to V DD and enable is high.

A B is varied from 0 to V D D and enable is high. Figure 9:

Figure 9: Transmission gate switch

D and enable is high. Figure 9: Transmission gate switch Figure 10: R O N of

Figure 10: R ON of Transmission gate switch

The maximum R ON = 926.76Ω when V AB = V DD

.

The variation of maximum R ON over different process cor-

ner, supply voltages (3V to 3.6V) and temperature (0 C to 70 C) is shown in Table 11.

2

Table 11: R ON of switch for different corners

Paramerter

Min

Nominal

Max

R ON (Ω)

474.7

926.8

1585

The time constant for switch S 3 for maximum R ON is τ = 11.1ns. The reset time for the integrator of IADC is 5 · τ = 55.5ns. The OFF resistance of the switch is 4.5G

5 Current Reference

Current reference circuit is the next critical component of the IADC which delivers the required current over all the process corners and temperature variation. The circuit in question needs current of 20uA for both the integrator and the comparator. The requirement for the current source also includes a power down circuit to switch off the circuit when the power down signal is high along with a start up circuit to ensure that the current source starts to give out a fixed current. There are many ways to design the current source. Threshold current source is one such method which provides current which is independent of supply voltage. However, when designed, the dependence of current on V th was found to be very high over different CMOS corners. In order to improvise the same, Widlar current source is now taken and the loads of the same are modified to achieve a very low dependence on supply voltage and CMOS corners. An ideal current source primarily needs a process and supply compensated proportional to absolute temperature (PTAT) along with complementary to absolute temperature(CTAT) currents. The idea behind this circuit is to achieve a process, voltage supply independent current source which has a positive gradient with temperature. This is now tuned with a CTAT component which has a negative gradient with temperature. However, in the scope of the design, only PTAT is designed to achieve independence to supply and process.

is designed to achieve independence to supply and process. Figure 11: PTAT current source Figure 11

Figure 11: PTAT current source

Figure 11 is a modification of the WIDLAR current source where the current in the branch is V R2 /R2. Transistors MN7, MN4 are adjusted such that they are always in

subthreshold region where they behave like BJTs. The advantage of this circuit is that the current no longer depends on V th or Vsupply. Instead, the current is now a function of Vt as shown in the equations below. Using this, the variations of CMOS, Vsupply are efficiently removed. However, the critical point as shown above is still the temperature and variation of the external resistor used which defines the current.

I N7

I N7

=

=

I o A(W 7 /L 7 )e (V GS7 V tn+V R2 )/V T )

I o (W 7 /L 7 )e (V GS7 V tn)/V T )

V R2 = K V T ln(A)

K and A are constants. This gives a fixed V R2 which divided over resistor R2 gives a fixed current Iref. It has to be ensured that MN7 and MN4 are operating in sub-threshold region and MP0, MP7 are in strong inversion region.

Corner and mismatch analyses were done to see the op- eration at different corners. Current (Iref) is plotted at the current mirror branch which is used by comparator and in- tegrator. Results are attached in the table below.

Table 12: I ref Mismatch and corner analysis

Parameter

Analysis

Min

Mean

Max

Iref- Power off

Corner

300nA

400nA

500nA

Iref - Power on

Corner

13.82uA

20.31uA

28.27uA

Iref- Power off

Mismatch

320nA

407nA

500nA

Iref - Power on

Mismatch

14.77uA

19.58uA

25.42uA

Worst case corner of resws yields the lowest current of 13.82uA while the reswp corner yields the maximum cur- rent of 28.27uA. MC analysis was done to analyse the effect

of mismatch on the current generation. Mismatch analysis

yields the following results. Table 13 summarises the tran- sistor dimension of the current reference designed here.

Table 13: Current reference:Component parameters

Component name

Parameter

Id(uA)

MP7

6/3 (um)

5.01uA

MP0

6/3(um)

4.99uA

MN7

30/3(um)

5.01uA

MN4

100/3 (um)

4.99uA

R2

10k ohm

 

Power down is achieved by disconnecting nodes A and

B which pulls node A to Vdda which stops the current

generation. At this point Point B goes to Ground to ensure 0 current in MN7. The advantage of this is that when the switch is closed, the high value of node A and node B are shorted which immediately starts up the circuit. The only problem associated with this is the extra resistance seen at the path of the current reference.

6 IADC analog front end

The IADC analog front end consists of Integrator with switches, comparator stage and current reference. The out- put of comparator is applied to the digital control logic.

6.1 Implementation

Figure 12 shows the final IADC analog front end including all the blocks designed above.

analog front end including all the blocks designed above. Figure 12: IADC analog front end Figure

Figure 12: IADC analog front end

Figure 13 shows the layout of IADC by placing all the components, which is realisable for given area specification.

which is realisable for given area specification. Figure 13: IADC layout with all components 6.2 Simulation

Figure 13: IADC layout with all components

6.2 Simulation Results And Discussion

Figure 14 shows the final IADC analog front end opera- tion for an input differential peak of v in = 0.5V simulated at typical conditions of process corner and temperature. There is 32.7ns delay between integrator crossing during disintegration phase and comparator switching.

during disintegration phase and comparator switching. Figure 14: IADC Functionality With all the components

Figure 14: IADC Functionality

With all the components combined, the critical aspects identified are ENOB, hysterisis of the comparator, offset and gain of the integrator and the slope of the integrator. As seen in the corner analysis, the variation of poly resistor and poly capacitors are huge which lead to a huge variation of the slope of the integrator. Owing to this, the transistors are not in saturation for some corners which leads to a higher inaccuracy for maximum input voltage.

Table 14 and Table 15 shows the LSB error in time of IADC output for different process corners (tm, ws, wp, wo, wz), supply voltages (3V to 3.6V), designed current ref- erence (section 5), V cm (1.3 to 1.7) and temperature (0 C to 70 C) variations for maximum differential input peak v in = 0.5V and v in = 0.25.

Table 14: IADC corner anaysis for v in = 0.5V

Parameters

Min

Nominal

Max

LSB Error

-13.80

-1.236

2.179

Table 15: IADC corner anaysis for v in = 0.25V

Parameters

Min

Nominal

Max

LSB Error

-2.5

-1.5

0.5

Mismatch analysis of LSB error in time of IADC output is performed using monte-carlo simulations for v in = 0.5V .

Table 16: IADC mismatch analysis

Parameters Measured

Min

Max

Mean

Sigma 1σ

LSB error

-4.421

5.582

-217.9m

1.36

7

Conclusion

The IADC analog front end was tested for supply voltage range of 3V to 3.6V, operating temperature of 0 C to 70 C and input common mode of 1.3V to 1.7V and mismatches. The effective number of bits was found to be roughly 7-bits under worst case conditions and mismatch simulation. The critical corner for integrator performance was worst power process corner and high temperature where differential am- plifier goes out of saturation, which can be overcomed by decreasing the RC slope. The critical corner for comparator operation was cmosws corner and low temperature where the switching speed is the lowest.

References

[1] HIROSHI A, "Dual-Slope Integrating Analog-to- Digital converter with Digital Self-Calibration", IEEE Transactions on Instrumentation and measurement, VOL.IM-28, NO.1, MARCH 1979.

[2] Earle W.Owen, "The Elimination of Offset Errors in Dual-Slope Analog-to-Digital Converters", IEEE Transactions on Circuits and Systems, VOL.CAS-27, NO.2, February 1980.

[3] Ken Martin, David A Johns, "Analog integrated circuit design", 2nd edition,John Wiley and Sons, Inc

[4] Suhas Shinde, "PVT insensitive Reference Current Generation", IMECS, Vol II, March 2014

[5] Hongschin Lin, "Low-Voltage Process Corner Insensi- tive Subthreshold CMOS Voltage Reference Circuit", IEEE transactions, 2006

[6] Howard Tang, Joshua Yung Low, "A Compact 16-bit Dual-Slope Integrating Circuit for Direct Analog-to- Residue Conversion", Circuits and systems (APCCAS), Pg:272-275, Dec.2012.