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Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typographic and Syntax Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1
Diva Flow: Simulating Analog Circuits with Parasitics. . . . . . . . 11
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preparing Cell Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preparing Technology Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding Component Description Format (CDF) Simulation Information . . . . . . . . . . .
Creating Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating Extracted Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extracting Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating ConcICe Views from Extracted Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Comparing Schematic and Extracted Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Building an analog_extracted View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating and Using a Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Probing Parasitic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Backannotating Parasitic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
13
13
13
16
17
17
19
20
23
24
29
30
31
2
Diva Flow: Simulating Mixed-Signal Circuits with Parasitics
33
34
35
43
43
46
51
61
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3
Diva Flow: Working Through an Extended Design Example 71
Simulating with Schematic Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Configuring and Partitioning the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Modifying the Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Simulating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Choosing an Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Generating a Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Plotting Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Alternate Waveform Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Saving the Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Simulating with Analog Parasitics and Estimated Digital Delays . . . . . . . . . . . . . . . . . . . 88
Extracting Analog Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Setting Partitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Estimating Digital Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Simulating with Analog and Digital Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Cell Library Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Creating a Mixed Extracted View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Building a Mixed Extracted View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Simulating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Whole Design Approach to Mixed-Signal Parasitic Simulation . . . . . . . . . . . . . . . . . 126
Comparing Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4
Assura Flow: Simulating Analog Circuits with Parasitics
. . . 131
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preparing Cell Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preparing Technology Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating Extracted Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Comparing Views using LVS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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133
133
134
134
134
138
140
142
146
149
152
A
LVS Form Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Diva . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Assura . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Schematic and Layout Format Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
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Preface
This manual describes how you can use Cadence tools to investigate the effect of parasitics
on your circuits. The guidance here is designed for users who are already familiar with circuit
design, simulation, and layout.
The information is divided into four chapters. Chapters 1-3 are based on the Diva physical
verification flow and Chapter 4 on the Assura flow.
Chapter 1, Diva Flow: Simulating Analog Circuits with Parasitics describes the flow and
tools for analog circuits. If your design contains only analog circuits, and you use the Diva
physical verification tool to extract parasitics, use the information in Chapter 1.
Chapter 2, Diva Flow: Simulating Mixed-Signal Circuits with Parasitics, describes the flow
used for digital or mixed-signal designs. Taking digital elements into account leads to a flow
that includes using the Cadence timing analyzer. If your design is digital or mixed-signal, you
can skip Chapter 1 and go directly to Chapter 2.
Chapter 3, Diva Flow: Working Through an Extended Design Example is a tutorial that
guides you through a series of examples illustrating the information in Chapters 1 and 2.
Chapter 4, Assura Flow: Simulating Analog Circuits with Parasitics describes the flow and
tools for analog circuits. If your design contains only analog circuits, and you use the Assura
physical verification tool to extract parasitics, use the information in Chapter 4.
This preface discusses the following:
Related Documents
Running a simulation with parasitics requires knowledge of several Cadence tools, which are
described in the following documents.
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ConcICe Help
z_argument
[ ]
{ }
Used with vertical bars and encloses a list of choices from which
you must choose one.
=>
text
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Important
The language requires many characters not included in the preceding list. You must
type these characters exactly as they are shown in the syntax.
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10
1
Diva Flow: Simulating Analog Circuits
with Parasitics
This chapter describes how you can use Cadence tools to investigate the effect of parasitics
on analog circuits. By accounting for the effect of parasitics, you can improve the accuracy of
your circuit simulations. If your design includes digital or mixed-signal circuits, skip this
chapter and go to Chapter 2, Diva Flow: Simulating Mixed-Signal Circuits with Parasitics.
Click a topic below for more information.
Overview on page 11
Overview
Simulating an analog circuit with parasitics requires these steps.
1. Preparing cell libraries
2. Creating an analog_extracted view of your design
In this step, the tool calculates parasitics from information in the layout view of your
circuit.
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layout View
Extractor
extracted View
concICe View
LVS
map files
Build_Analog
analog_extracted
View
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symbol cellview
symbol cellview
The analogLib library contains examples of analog primitives and parasitic cells that you
can copy to create your cell library.
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Creating Designs
If you intend to extract parasitic components from the layout view and run a simulation with
parasitics, use the following guidelines to avoid problems as you plan your design.
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Extracting Parasitics
To extract parasitics from the layout view of a cell or block,
1. Be sure that the environment variable CDS_Netlisting_Mode is set to Analog.
2. Choose Verify Extract from the layout cellview of the cell.
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To select more than one item, click on your first selection, then hold down the Control
key and make the rest of your selections.
6. When you have specified the parasitics you want, click OK.
The Extractor form reappears with the parasitics you selected in the Switch Names
field.
19
In a concICe view, all cross-coupling capacitors between analog nets are grounded.
When you use a concICe view in the flow, you can probe interconnects in the layout view
only at the terminals.
For detailed information on creating concICe views from extracted views, see the ConclCe
Help.
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3. Enter the names of the rules file and rules library for the Diva LVS rules.
4. Click the Run button near the bottom of the form to begin the comparison.
Click here.
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Click here
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2. Select one of the following choices to specify the analog parasitics that you want to use
for simulation.
Select
If you want to
Include All
None
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8. Click on the Use Template button located at the bottom of the form.
The Use Template form appears.
9. Select a template that is compatible with the simulator you are running from the Name
drop-down list box.
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The Hierarchy Editor window configures the design by using a default View List and
Stop List in the Global Bindings section. You need to modify these lists for your design.
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2. In the Max list size field, specify how many parasitic instances to display.
3. Sort parasitics by resistance or capacitance by selecting R or C.
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Click Whole Net and then click on a net in the schematic or extracted view to display
an ordered list of all the parasitics on the net. The largest resistances or
capacitances appear at the top of the list.
Click Point to Point and then click on two pins or instance pins in the schematic or
extracted view to collect all the parasitics between two points.
If the points are on the same net, both resistances and capacitances are collected.
If the points are on different nets, only capacitances are collected.
Click Net to Net and then click on two nets in the schematic or extracted view to
collect parasitic capacitances between two different nets.
A list of the collected parasitic instances appears. Select an instance from this list to
highlight the component symbol associated with this parasitic on the extracted view.
2. Select the font size and label offsets that you want and click the Add Parasitics button.
Resistance and capacitance labels appear on the schematic view. To see them, you
might need to zoom in on a portion of the schematic. Note that the new information
displayed on the schematic is for viewing only. Using the Add Parasitics button does not
include the parasitics in the schematic.
3. Click the Remove Parasitics button to remove these labels.
4. Choose Print All to write all of the parasitics to a file.
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2
Diva Flow: Simulating Mixed-Signal
Circuits with Parasitics
The information in this chapter describes how you can use Cadence tools to investigate the
effect of parasitics on mixed-signal circuits. By accounting for the effect of parasitics, you can
improve the accuracy of your circuit simulations. If your design includes only analog circuits,
go to Chapter 1, Diva Flow: Simulating Analog Circuits with Parasitics instead.
Click a topic below for more information.
Overview on page 34
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Overview
The flows in this chapter describe two ways to calculate delays for mixed-signal circuits.
You can estimate delays before layout by using timing library format (TLF) and fan-in and
fan-out information.
You can use layout information to determine delays with increased accuracy.
The pre-layout flow is discussed in Estimating Delays (Pre-Layout). For information on using
layout information to calculate delays, see Calculating Delays (Post-Layout) on page 43.
Before following any of the flows in this chapter, be sure that the environment variable
CDS_Netlisting_Mode is set to Analog. To ensure that all the tools for the flow are
available, start your session with the command icfb.
For more information about the options you can use with the command to start the software,
refer to the Cadence Design Framework II User Guide.
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pearl.cmd
Mixed-Signal Netlister
gcfConstraints.gcf
Digital Netlist
Analog Netlist
compiled TLF
SDF
SPECTRE
IPC
VERILOG.VMX
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Provide these files in one of the locations listed in Locations Searched for the pearl.cmd
and gcfConstraints.gcf Files on page 38
If you provide the files, clicking on the Command and Constraints buttons opens the
files for editing.
Create these files from templates by clicking on the Command and Constraints buttons
If the files do not exist, clicking the buttons copies templates to your run directory and
opens the copies for editing.
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The Cadence timing analyzer searches for the pearl.cmd and gcfConstraints.gcf files
in the following locations, which are searched in the order given.
1. The run directory
For example, if the simulation directory is $HOME/simulation, the run directory is
$HOME/simulation/topLevelCellName/simulatorName/viewName/
netlist/digital
You can change the contents of the gcfConstraints.gcf and pearl.cmd files as
necessary.
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Important
Change the design name to the name of your top-level design. Ensure that the path
to the compiled timing library format (CTLF) files is specified with one of the
following.
An absolute path
For more information about the run directory, see Locations Searched for the pearl.cmd
and gcfConstraints.gcf Files on page 38.
Do not use a tilde (~) to specify the path.
When you finish editing the file, save it.
2. To change the contents of the pearl.cmd file, click the Command button in the Mixed
Signal Options form.
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The Command Options form allows you to change the options that are listed in the
following table.
Option
Default
Meaning
Power Node
VDD
Ground Node
VSS
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Option
Default
Meaning
Library
Corner
all
Slew Mode
all
Wireload
Library
Blank
Wireload
Group and
Value
Blank
Wireload
Name
Blank
Wireload
Topology
balanced
SDF Timing
Scale
ns
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Option
Default
Meaning
SDF
Precision
4 for ns
units; 0 for
ps units
Report
Boundary
Nets
Not
selected
SDF Edge
Specifier
Not
selected
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2. Change the values as necessary. If you need guidance, see the SDF Annotator User
Guide.
43
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layout View
Extractor
extracted View
.simrc File
config View
concice View
LVS
config View
map files
Build_Mixed
mixed_extracted
View
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SPF
45
Top Level
config View
SPF
MS Netlister
pearl.cmd
gcfConstraints.gcf
Digital Netlist
Analog Netlist
compiled TLF
SDF
External SDF
SPECTRE
IPC
VERILOG.VMX
Digital parasitics are calculated by the Cadence timing analyzer or can be imported from an
external calculator. The SDF file created by the Cadence timing analyzer is annotated to the
netlist at simulation time.
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schematic view
symbol view
symbol view
msps view
schematic view
Each digital primitive must have an msps stopping view, which is required for layout versus
schematic (LVS).
To create msps views,
1. In the CIW, choose Tools Mixed Signal Environment Prepare Library for MSPS.
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2. Select the primitives for which you want to create msps views. As described below, you
can either select the primitives manually or select primitives that have certain specified
views.
Selecting Primitives Manually
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For standard settings for these variables, refer to the Assura Diva Verification
Reference.
3. Save the .simrc file.
Preparing to Create the top.spf File
The Cadence timing analyzer uses a standard parasitic format (SPF) file called top.spf,
which contains the parasitic information for your design. In preparation for creating this file,
you must ensure that the property names for resistance and capacitance are set to r and c.
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2. Click OK.
The CIW displays a list of any discrepancies. Fix them before you extract the parasitics.
Extracting Parasitics and Creating Extracted Views
To extract parasitics and create extracted views,
1. From a window displaying a layout view of the cell, choose Verify Extract.
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To select more than one item, click on your first selection, then hold down the Control
key and click on the rest of your selections.
5. Click OK.
The Extractor form reappears with the parasitics you selected in the Switch Names
field.
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In a concice view, all cross-coupling capacitors between analog nets are grounded.
When you use a concice view in the flow, you can probe interconnects in the layout view
only at the terminals.
For detailed information on creating concice views from extracted views, see the ConcICe
Help.
Comparing Schematic and Extracted Views
To compare the schematic view with the extracted view created earlier, follow these steps. (To
compare the schematic view with a concice view, follow the same steps but substitute the
concice view for the extracted view.)
1. From a window displaying the extracted view, choose Verify LVS.
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3. Fill in the names of the rules file and rules library for the Diva LVS rules.
4. Click the Run button near the bottom of the form to begin the comparison.
Click here.
57
2. Verify that the Library, Cell, and View fields correctly specify the configuration view that
you want to use.
If your design does not have a configuration view associated with it, refer to the Cadence
Hierarchy Editor User Guide and create a configuration.
Note: The msps view, used as the digital stopping view for LVS, is also used as the
internal stopping view for SPF generation when the build mixed process runs. Be sure
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If you want to
Include All
None
4. Ensure that the pearl.cmd and gcfConstraints.gcf files are ready and available
in one of the following locations, which are searched in the order given.
For guidance on using the Command and Constraints buttons to view or change these
files, see Preparing the pearl.cmd and gcfConstraints.gcf Files on page 37. When the
files are ready, turn on the Calculate button in the Digital Delays section.
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5. Click Yes if you want to use the default templates for the option files.
6. To build the mixed_extracted view, click OK in the Build Mixed Extracted View form.
The build mixed process removes all digital parasitics and places them in the SPF file. The
Cadence timing analyzer uses the SPF file to calculate the delays and generate an SDF file.
The mixed_extracted view contains analog parasitics and analog and digital instances for
netlisting and simulation.
The build mixed process creates or places the following files in the layout_msb directory.
Filename
Description
msbCheckFile
msbEnableFlag
pearl.cmd
gcfConstraints.gcf
top.spf
top.tmp.sdf
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Filename
Description
annotate.com
runPearl.log
61
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4. To use the SDF files created during the build mixed process, turn on the SDF From
Mixed Extracted View button.
5. To import SDF files created by a different tool, turn on the Import SDF Files button and
fill in the associated fields.
In the File field, type the path to and filename of the SDF file that you want to import.
The name you enter must be a legal Verilog language name.
In the Scope field, type the hierarchical scope of the instance for which the delay
file is to be annotated during simulation. For example, you might type something like
I1/I3 to indicate an instance one level down in the hierarchy.
6. If you want to import more SDF files, click the Import More button and fill in the Import
SDF Files form as described in Importing Additional SDF Files on page 64.
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2. In the Max list size field, specify how many parasitic instances to display.
3. Sort parasitics by resistance or capacitance by selecting R or C.
4. Click the appropriate button to specify the parasitics to be collected.
Click Whole Net and then click on a net in the schematic or extracted view to display
an ordered list of all the parasitics on the net. The largest resistances or
capacitances appear at the top of the list.
Click Point to Point and then click on two pins or instance pins in the schematic or
extracted view to collect all the parasitics between two points.
If the points are on the same net, both resistances and capacitances are collected.
If the points are on different nets, only capacitances are collected.
Click Net to Net and then click on two nets in the schematic or extracted view to
collect parasitic capacitances between two different nets.
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Select an instance from this list to highlight the component symbol associated with this
parasitic on the extracted view.
5. To backannotate the resistances and capacitances to the schematic view, click the
Backannotate button on the LVS form.
The Parasitic Backannotation form appears.
6. Select the font size and label placement that you want and click the Add Parasitics
button.
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You can select several terminals on the same net. Each selected terminal is marked with a
different color X. The associated waveform displays in the same color as the X on the
schematic.
You can select and probe only real geometries from a mixed_extracted view. For example, if
the metal layer is broken up into resistors, the geometries do not have connectivity. In this
case, you need to probe the metal layer at contacts and vias.
If you are unable to select a geometry on the mixed_extracted view, the layer might be invalid.
Set valid layers from the Edit menu of the LSW form.
If you probe a net that cannot be mapped to a terminal in the mixed_extracted view, warnings
similar to the following appear:
*WARNING* Could not obtain the external name
*WARNING* Unable to map net 'VBG'
*Warning* no valid full path name for net "VBG", selection not taken
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Analog Block
Analog Block
D2A
A2D
In the netlist
In the netlist
The D2A and A2D elements are attached to the digital components in the netlist. The output
of the D2A element or the input of the A2D element, therefore, is a valid analog net in the
extracted view.
Because digital parasitics are removed from the mixed_extracted view, digital nets can be
probed anywhere and do not have to be associated with terminals. An X is placed in the
middle of the net indicating its selection.
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3
Diva Flow: Working Through an Extended
Design Example
The three sections of this design example provide an overview of the front-to-back mixedsignal simulation flow for the Cadence Analog Design Environment (ADE) 5.0. The circuit
used throughout this design example is a counter-controlled A/D converter (ccadc). The
circuit simulator used is spectreVerilog. For more information on mixed-signal simulation,
refer to the Cadence Mixed-Signal Circuit Design Environment User Guide.
The three sections of this example are
Before you can follow the steps in these sections, you need to prepare the libraries and start
the tools that are used.
1. Copy the mixed-signal design example files to your home directory by typing the
following at the command prompt:
cp -r your_inst_dir/tools/dfII/samples/artist/mixSig/msps
4. To start the Cadence software and enter the mixed-signal simulation environment, type
the following at the command prompt:
icfb &
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Note: If the icfb command does not work, contact your Cadence system administrator for
assistance.
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4. In the Tool drop-down list box, choose Hierarchy - Editor. Notice that the View Name
field automatically changes to config.
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9. In the Top Cell section, View field, replace myView with schematic.
The configuration file is built from the original schematic.
10. Click OK.
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11. To save this new configuration, choose File Save in the Hierarchy Editor window.
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4. Repeating this process, change the View To Use for the Comparator cell to ahdl and
for the counter cell to schematic.
You have to scroll down in the Cell Bindings section to the counter cell.
5. To propagate the changes through the hierarchy, update the configuration by using either
of the following methods:
From the menu bar in the Hierarchy Editor window, choose View Update.
Note: Whenever a white exclamation mark with a red background appears over the update
icon, an update is needed.
update icon
Because you are updating the configuration, you need to save the changes to disk to syncup the Hierarchy Editor (HED) with icfb (because they are separate processes). The Update
Sync-up form appears. Click OK.
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2. Notice that the title bar of the schematic window identifies the schematic as being
opened from a configuration (config) view.
Note: You run subsequent netlisting processes and simulations from this configured
schematic view to access the design expansion information.
For more information about design partitioning and creating a configuration file, refer to
Cadence Mixed-Signal Circuit Design Environment User Guide.
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2. Make sure the status bar displays Simulator: spectreVerilog and that ~/simulation
is the project directory. (To check the project directory, choose Setup Simulator/
Directory/Host).
Note: If a different simulator or project directory is displayed, choose Setup Simulator/
Directory/Host and use the Choosing Simulator/Directory/Host form to make changes as
needed.
3. Choose Setup Model Libraries.
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You need to specify every model file that is used in the simulation. In this case, all the
device models that you need are in a file called models.scs.
4. Click Browse.
The Unix Browser form appears.
5. Find models.scs and click on it.
6. Click Apply.
7. In the Model Library Setup form, click Add.
The path to the msps model file appears at the top of the Model Library File list box.
Because you are using mixed signal, you also need to add the interface elements to the
model file list.
8. Add CML_a2d.scs and CML_d2a.scs to the list displayed in the Model Library Setup
form.
9. Choose Cancel in the Unix Browser form.
10. Click OK in the Model Library Setup form.
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Choosing an Analysis
1. From the simulation window, choose Analyses Choose.
The Choosing Analyses form appears.
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Generating a Netlist
The ADE automatically creates a netlist when you run a mixed-signal simulation, so this
procedure is optional.
1. From the simulation window, choose Simulation Netlist Create.
The mixed-signal netlister creates separate analog (Spectre) and digital (Verilog)
netlists.
2. Examine the netlists.
Notice that hierarchical netlisting preserves the design hierarchy.
Both analog and digital netlists contain interface elements. These interface elements are
placed at every analog-to-digital and digital-to-analog connection. Interface elements
allow the Spectre and Verilog simulators to exchange information during simulation. For
more information on interface elements, refer to Mixed-Signal Interface of the Cadence
Analog Circuit Design Environment User Guide.
Spectre interface elements definitions
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Plotting Results
1. From the simulation window, choose Outputs To Be Plotted
Select On Schematic.
2. On the configured schematic, click on the output of the AND gate (andOut), the output
of the comparator (compOut), and the output of the DAC (dacOut).
Select these
outputs.
The outputs to be plotted appear in the Outputs section of the Analog Design
Environment Simulation window.
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dacOut
compOut
The counter counts up. The digital output of the counter converts to an analog voltage
via the DAC. Once the DAC voltage exceeds the input reference voltage (as defined by
the Input design variable), the comparator output swings low and shuts off the clock.
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2. Press Return.
3. In the Waveform window, choose Window Reset.
4. From the simulation window, choose Results Plot Outputs Transient.
The analog simulation results appear as strips in the Waveform window.
6. Press Return.
7. In the Waveform window, choose Window Reset.
8. Replot the results from the simulation window.
For more information on plotting, refer to Plotting Results on page 83.
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The Saving State form appears with state1 in the Save As field.
2. Click OK.
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Setting partitions
In this design example, you also view the analog backannotated parasitics.
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"4_bit_DAC
layout" ***
12. Close the 4-bit DAC layout window. Do not save changes.
Comparing Views
In this procedure, you run LVS, which compares the schematic view with the extracted view
you just created. Any mismatches are identified at the end of the run.
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Click Sel by Cursor on the schematic side and click again in the 4-bit DAC
schematic window. The Library, Cell, and View fields are updated automatically.
Click Sel by Cursor on the extracted side, then click in the 4-bit DAC extracted view
window. The Library, Cell, and View fields are updated automatically.
5. Click the Run button at the bottom of the LVS form to begin the comparison.
6. Click the Info button to view the log file while LVS is running.
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Upon successful completion of the LVS run, the log file displays information about the
netlist comparison.
The net-lists match.
un-matched
rewired
size errors
pruned
active
total
un-matched
merged
pruned
active
total
un-matched
total
End comparison:
layout schematic
instances
0
0
0
0
0
0
0
0
80
80
80
80
nets
0
0
0
62
62
0
0
0
62
62
terminals
0
0
14
14
Aug 4 22:35:43 1997
96
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Clicking Whole Net dumps all parasitics on the net, up to the Max list size designated
on the form. Clicking Point to Point dumps the parasitics between two terminals you
select on the schematic. Clicking Net to Net shows the parasitics between two different
nets.
2. Click Whole Net.
3. On the schematic, select the output of the 4-bit DAC.
A form appears, displaying the parasitics for the net you selected.
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Setting Partitions
In this section, you prepare to run the simulation with the analog extracted view you just
created.
Setting Up the Simulator
1. In the Library Manager window, choose mixSigLib as the library, tutorial as the cell, and
config_FE as the view. (Scroll down the list of cells to select the tutorial cell.)
2. Choose File Open.
Either the Open Configuration or the Top CellView form appears.
3. Click yes to open both the Configuration and the Top Cell View.
4. Click OK.
The configured schematic for the tutorial cell opens, and the Hierarchy Editor window
appears.
5. In the configured schematic window, choose Tools Analog Environment.
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6. Make sure the status bar displays Simulator: spectreVerilog and that ~/simulation
is the Project directory. (To check the Project directory, choose Setup Simulator/
Directory/Host.)
Modifying the Configuration
In the following steps, you display the View to Use and Inherited View List properties on
the configured schematic and change those properties prior to circuit simulation.
Viewing the Design Partition
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8. On the comparator and counter cells, verify that View to Use is schematic.
9. In the Partition Display form, click Cancel.
Changing the View to Use
Before running the simulation, you must change the View To Use field to the analog
extracted view you created earlier. You can change View To Use from the hierarchy editor
(HED) or from the Hierarchy-Editor menu in the configured schematic window. In this
example, you use the Hierarchy-Editor menu.
1. In the configured schematic window, choose Hierarchy-Editor Set Instance
Binding.
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The Cadence timing analyzer requires two initialization files to run: pearl.cmd and
gcfConstraints.gcf. The Cadence timing analyzer searches for these files in the
locations described by Locations Searched for the pearl.cmd and gcfConstraints.gcf
Files on page 38. If the files are not in these locations, the Cadence timing analyzer
uses a default, which can be found at $CDS_INST_DIR/tools/dfII/etc/tools/
mmsimenv. For this example, use the defaults.
3. Click Command to open the Command Options form.
The information in this form is used in the pearl.cmd file.
4. Click OK to close the form.
5. In the Mixed Signal Options form, click Constraints.
An edit window opens with the gcfConstraints.gcf file.
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7. Select config-frontEnd.
This is the name of the results file you saved from the front-end simulation in Simulating
with Schematic Data on page 72.
8. Click OK.
9. Click the Plot Outputs button in the lower right corner of the Analog Design Environment
Simulation window.
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10. To end this session, close all windows except the CIW. Do not save any changes.
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Waveform probing
Layout view
Note: For analog layouts with pins, ivCellType must be graphic.
auLVS view (the default stopping view for auLVS) and CDF simulation information for
analog primitives
Layout view
Note: For hierarchical digital blocks, ivCellType must be graphic.
msps view (stopping view for auLVS and Build Mixed) and CDF simulation information
for digital primitives
Note: For information on creating an msps view, refer to Creating an msps View for a
Digital Primitive on page 47.
If using the Cadence timing analyzer, a compiled TLF (.ctlf) file provides a timing
definition for each digital primitive
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The pin direction check finds that the supply pins in the layout do not exist in the
schematic. This does not matter for digital blocks because, in the final mixed extracted
view, the symbol of the counter takes the place of the macro cells. Therefore, the final
netlisting view does not contain the supply pins.
4. From the layout view window, choose Verify Extract.
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Note: You must set Extract Method to macro cell to stop extraction of digital cells
below the top level of hierarchy.
6. Click OK to create the extracted view.
As the extracted view is created, you can view progress in the CIW.
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Note: View must be set to config. The config view tells the software which cells are
analog and which cells are digital.
2. Click Command.
The Command Options form appears. If the mixed extracted view did not previously exist,
the form uses a pearl.cmd file found in the locations detailed in Locations Searched
for the pearl.cmd and gcfConstraints.gcf Files on page 38. If there is no pearl.cmd file
in one in those locations, the form gets a default file from $CDS_INST_DIR/tools/
dfII/etc/tools/mmsimenv.
3. Click OK.
4. Click Constraints in the Build Mixed Extracted View form.
The gcfConstraints.gcf file opens in an edit window. Update the DESIGN entry to
"counter" and the CTLF_FILES entry to the path to timing.ctlf.
5. Save your changes and close the edit window.
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8. Zoom into the origin until you see symbols of all blocks in the counter stacked one on top
of the other.
Notice that all macro cells in this view are replaced with modified schematic names to
preserve the original schematic hierarchy in the digital netlist.
9. Close all windows except the CIW.
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Note: For more information on parameters in the sdf.cfg file, refer to the SDF
Annotator User Guide.
11. Set the MTM (delay) value to TYPICAL.
12. Click OK.
Note: You can annotate only one delay value to the simulation. This value is determined
by the MTM setting.
13. On the Mixed Signal Options form, click OK.
14. Run the simulation by choosing Simulation Netlist and Run in the Analog Design
Environment Simulation window.
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15. Close all windows except the CIW. Do not save changes.
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7. Click Config.
On the standard delay format (SDF) form, ensure that MTM is set to TYPICAL.
8. Click OK in the SDF Annotator Config File form.
9. Click OK in the Mixed Signal Options form.
10. In the Analog Design Environment Simulation window, choose Simulation Netlist
and Run to run the simulation.
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4. Click on config-frontEnd.
The config-frontEnd file contains the results of the front-end simulation with analog
delays.
5. Click OK.
6. Click on the Plot Outputs button in the lower right corner of the simulation window.
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4
Assura Flow: Simulating Analog Circuits
with Parasitics
This chapter describes how you can use Cadence Assura tools to investigate the effect of
parasitics on analog circuits. By accounting for the effect of parasitics, you can improve the
accuracy of your circuit simulations.
Click a topic below for more information.
Overview
Simulating an analog circuit with parasitics requires these steps,
1. Preparing cell libraries.
2. Creating an av_analog_extracted view of your design.
In this step, the tool calculates parasitics from information in the layout view of your
circuit.
3. Creating a configuration for your design.
4. Simulating the design with parasitics included.
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schematic View
layout View
LVS
RCX
av_extracted View
MSPS
Build Analog
av_analog_extracted View
Note: Diva physical verification rules files can be used with the Assura physical verification
tool to create an extracted view.
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symbol cellview
symbol cellview
auLvs cellview
The analogLib library contains examples of analog primitives and parasitic cells that you
can copy to create your cell library.
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Creating Designs
If you intend to extract parasitic components from the layout view and run a simulation with
parasitics, use the following guidelines to avoid problems as you plan your design.
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4. If you want to load previously saved LVS run settings into the form, click the Load State
button and select a name from the Assura LVS State form.
5. To create a new LVS run, type the layout and schematic library, cell, and view names into
the Library, Cell, and View text fields.
Note: You can also use the Browse button to search for a design library, cell, and view.
6. Choose a format for the layout and schematic designs from the Schematic Design
Source and Layout Design Source drop-down boxes.
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If you are using a Diva rule file containing the Extract? switch, select Extract?
from the list of switches.
If the Diva rule file contains switches to specify parasitic extraction commands, do
not select these switches.
11. Click OK in the Assura Run LVS form to start the LVS run.
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Note: If the Run RCX menu item is inactive, either the LVS run has not been completed
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Click OK to select the run and close the Open Run form.
The Run RCX menu item becomes active.
2. In the Assura Parasitic Extraction form, use the Resistance and Capacitance check
boxes in the Extract section to choose the parasitics you want to extract.
3. Select an extracted view for output using the Output drop-down box.
4. In the View text field, type the name of the view.
The default name is av_extracted, but you can create a view using any other name.
5. Select OK to start the parasitic extraction.
A dialog box appears indicating the RCX run is complete.
140
2. In the Schematic Cellview group box, if the current view is not schematic, choose
schematic in the View drop-down list box.
3. In the Extracted Cellview group box, choose the av_extracted view created in Building
an av_extracted View using RCX on page 138.
4. Click the Build Analog button.
The Build Analog Extracted View form appears.
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8. Click on the Use Template button located at the bottom of the form.
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9. Select a template that is compatible with the simulator you are running from the Name
drop-down list box.
10. Click OK in the Use Template form.
The New Configuration form redisplays with default data for the Top Cell and Global
Bindings sections. This allows you to modify a typical view list and stop list, rather than
creating them from scratch.
Templates exist for each of the simulators. (To create templates that provide defaults for
these fields, see the Cadence Hierarchy Editor User Guide.)
11. In the Top Cell section, enter the library, cell name, and schematic cellview from which
to build the configuration.
Be sure to specify schematic for the view type because the configuration is built from
the original schematic of your design.
12. Click OK.
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The Hierarchy Editor window configures the design by using a default View List and
Stop List in the Global Bindings section. You need to modify these lists for your design.
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3. In the Max list size field, specify how many parasitic instances to display.
4. Sort parasitics by resistance or capacitance by selecting the R or C button.
5. Click the appropriate button to specify which parasitics should be collected.
Click Whole Net and then click on a net in the schematic or extracted view to display
an ordered list of all the parasitics on the net. The largest resistances or
capacitances appear at the top of the list.
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Tip
If a parasitic instance is selected in the Parasitic List form, and the extracted view is
open, then the extracted view is zoomed to the component symbol associated with
the parasitic instance, and the cursor is moved to rest on the symbol. The zoom
feature works for the Whole Net, Point to Point, and Net to Net options.
Click Point to Point and then click on two pins or instance pins in the schematic or
extracted view to collect all the parasitics between two points.
If the points are on the same net, both resistances and capacitances are collected.
If the points are on different nets, only capacitances are collected.
Click Net to Net and then click on two nets in the schematic or extracted view to
collect parasitic capacitances between two different nets.
Note: To perform net to net probing, you must run RCX extraction using coupled
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3. Select the font size and label offsets that you want and click the Add Parasitics button.
Resistance and capacitance labels appear on the schematic view. To see them, you
might need to zoom in on a portion of the schematic.
Note: The new information displayed on the schematic is for viewing only. Using the Add
Parasitics button does not include the parasitics in the schematic.
4. Click the Remove Parasitics button to remove these labels.
5. Choose Print All to write all of the parasitics to a file.
The Print All Parasitics form appears:
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A
LVS Form Field Descriptions
Diva
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Browse displays a browser window that lets you select the library, cell name, and
cellview name.
Sel by Cursor lets you select information from the extracted cellview window with
the mouse. The fields are automatically filled in after you make the selection.
Rules File specifies either the UNIX location of a rules file or, if you specified a rules library,
the name of the rules file within the library.
Browse displays a browser window that lets you select the Rules Library and Rules File.
Rules Library specifies the library from which the rules are referenced. If this option is not
selected, Diva physical verification gets the rules from a UNIX location.
LVS Options generates a cross-reference text file, fix devices, and bypass errors.
Rewiring changes the extracted and schematic network to bypass errors and continue
processing. Diva physical verification flags each change.
Device Fixing uses fix properties on device instances to limit device permutability.
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Assura
OK saves the changes made to the form and starts the LVS run.
Cancel closes the form without saving changes.
Apply saves the changes made to the form and starts the LVS run. The Run Assura LVS form
remains open.
Defaults resets the form to the default settings.
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Netlist Type contains a list of netlist types: cdl, verilog, and spice.
Browse displays the search form, which you use to select the netlist file.
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162
Preview displays a description of the syntax for a selected avCompareRule. This is the
syntax written to your rsf file.
Help Text displays a description for a selected avCompareRule.
View Additional Functions expands the form to display the available functions.
Use avFlattenCell Function includes the avFlattenCell function in the LVS run when
selected.
Modify avFlattenCell Function opens the avFlattenCell Function form, so you can
edit the avFlattencell function.
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Library defines the name of the DFII library to which you want to write.
GDS2 Lib Name defines the name of the GDS2 library to use.
Note: The GDS2 Lib Name field is available only when GDS2 is selected in Target.
DFII Tech File defines the technology file path and filename for the LVS run.
Note: The GDS2 File field is available only when GDS2 is selected in Target.
Add Layer Information to Layers List adds the new layer you created to the
Layers list.
Modify edits a layer; select the layer from the Layers list.
Note: The GDS2 Layer Number and GDS2 Data Type fields are available only when
GDS2 is selected in Target.
Use joinableNet Function includes the joinableNet function in the LVS run.
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Cell Names defines the cell names. To enter multiple cell names, type a single
space between each name.
Net Names to Join defines the net names. To enter multiple net names, type a
single space between each name.
Add Command to List adds the joinableNet command, with the cell names
and net names you specify, to the list of commands in the command list. If you do
not specify cell and net names, the joinableNet command is added to the list of
commands without any arguments.
Modify edits an existing joinableNet command. Any existing cell names, label
names, and substrings displayed in the form fields can be modified.
Cell Names defines the labeled cell names. To enter multiple cell names, type a
single space between each name.
Label Names contains text label names selected from the list of changeLabel
commands.
Add Command to List adds the label names in the Label Names list to the
changeLabel command.
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Cell Names defines the cell names. To enter multiple cell names, type a single
space between each name.
Net Names to Join defines the net names. To enter multiple net names, type a
single space between each name.
Add Command to List adds the mustJoinNet command, with the cell names
and net names you specify, to the list of commands in the command list.
Modify edits an existing mustJoinNet command. Any existing cell names, label
names, and substrings displayed in the form fields can be modified.
For more information, refer to the Assura Physical Verification User Guide.
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