1

Example 1:
A 1200/5, C400 CT with excitation curves shown on above figure, is connected to a
2.0 burden. Based on the accuracy classification, what is the maximum symmetrical
fault current that may be applied to this CT without exceeding a 10% ratio error?
Answer:
Based on the criteria that the CT can deliver 20 times rated secondary current
without exceeding a 10% ratio error, the maximum fault current will be 24000A.
However, with a 2.0 burden, this will result in a voltage below the knee point of the CT
and, as a practical matter, it will be within 10% accuracy at higher currents. This can only
be accurately determined from excitation or ratio correction curves and not from the
accuracy classification. For example, a CT with characteristics shown in above figure
will produce between 180-240A without exceeding the 10% ratio error, depending on the
power factor of the 2.0 burden.

2
Example 2:
A 1200/5, C400 CT is connected on the 1000/5 tap. What is the maximum secondary
burden that can be used and still maintain rated accuracy at 20 times rated symmetrical
secondary current?
Answer:
Since the secondary voltage capability is directly proportional to the connected tap, the
CT will support a voltage of 1000/1200 400V or 333V. Twenty times the rated
secondary current is 100A. Therefore, the maximum burden is 333V/100A or 3.33
Example 3:
Assume that secondary burden in a relay circuit is 5. The relay setting is 2A and the CT
ratio is 300/5. Using above figure, calculate the primary current required to operate the
relay?
Answer:
VB=5 times 2A=10V
The secondary exciting current from above figure is approximately 0.04A.
I P N ( I ST )
N (I E I S )

= 300/5(0.04+2) A=122A
Example 4:
A relay is expected to operate for a 7000A primary current. The CT ratio is 600/5.
Secondary burden is 3.5 . What is the error for the CT shown in above figure?
Answer:
The total secondary fault current is (7000/600) 5=58A. Assume that exciting current is
negligible.

3
VS I S ( RB RS )

= 58(3.5+0.31)
= 221V
The exciting current will not be negligible, however, and the calculation will not be
iterated.
Lec 7

dcmax

N1 RI 0
Vm N1 R Vm
Vm
N1
N1 RI 0 t
N1 I 0 t
dc

N
R

v2 (t )
e i2
e
1
N 22
| Z line | N 22 | Z line | | Z line |
N 22
N2
N2

t
t
t
N1 RI 0
1
N1 RI 0

(t ) (0)
v2 dt
(1 e ) (t ) (0)
(1 e )
N 2 0
N 22
N 22

Lec- 7
v2ac (t ) R

ac (t )

Vm N1
d
V2
sin(t )
j ac
| Z line | N 2
dt
j N 2

RVm N1
RVm N1

sin(t ) acmax
2
| Z line | N 2
2
| Z line | N 22

acmax dcmax

Vm N1
R
RVm N1 N1 RVm
L
X
| Zline | N 22

2
1
1 1 line 1 line
2
Vm N1 R
| Z line | N 2 N 2 | Z line |
Rline
Rline
2
| Z line | N 2

X
R
Lec-6
1

1000
400
1200
400 I max
153 A 153
1200
2.61
5
7000
6800
VS 2 (5 0.15) 10.3V I S
5 58.33 A I S
5 68 A
600
500
IE
6
300
100 100 R B 2.5
V S 58(3.5 0.31) 58 3.81
2.04
IS
68
5
VS 68(2.5 0.25) RI 1 RS 0.51
I S 20 5 100 A RS 0.61 VS

i p [ I 'sin(t ) I 'sin e t ]u (t ) i p [ I 'sin (cos t e t ) I 'cos sin t ]u (t )

I 'cos sin t I 'cos [e t sin cos cos sin(t )] I 'sin cos t
I 'sin
( e t e t )
I 'sin [e t sin 2 cos cos(t )] I 'sin e t

Lec 5
Ip
Ip
IS
IE
Ip
IS
100 N
98 45

I
N
S
E
100 N
IS
100
IS
IS
Lec - 9
Vth VT
100
Vth
1
v(t ) Ri
Ceq

1
1
) 02
02 1 LC
f 3Hz
2
0
LC
t
di
dv
di 1
d 2i
idt

dt
dt
dt Ceq
dt 2 0
d
1
1
1
VL VC jI
( L
)
I (2 2 ) 02
I ( L L)
d
Ceq
0 Ceq
LCeq
| V V | 2 LI 2 LI 2 L
2
j 2 LI (VL VC ) tan L C 2
2 f Lm 106
| VR |
a Rb I
a Rb a 2 Rb
Lm

106
3183.1H
2

(3 ) ( L

CT saturation and DC- offset current

Role of DC off-set current
Typically fault current consists a symmetrical ac component and a dc offset current. To
understand this concept, consider a transmission line unloaded exited by an equivalent voltage
source. The fault strikes at time t t 0 . This can be simulated by closing the switch at t t1

R jL or Z

i (t ) 0

models the line impedance. The fault current in the line is given by
0 t t0
t t0

Vm sin( t )

i (t )
I 0e
|Z|

t t0

Where is the time constant of the line =L/R. The fault current has two components in
it. The first component models the steady state sinusoidal ac response while the second current
is the dc offset current due to the presence of inductive component in the circuit. Recall that
current in an inductance can not change instantaneously. As t , the instantaneous dc

current, a consequence of maintaining initial condition i (t 0 ) i (t 0 ) , decays exponentially to

zero and the current reaches the ac steady state values. While the dc offset current, would in

6
theory persist till infinity, its trace in the actual wave form would not be seen beyond a certain
t

time constants. Table-I illustrates the values of e up to 10 time constants.

Time

t=0
1

t=
0.3678

t = 2
0.1353

t = 4
0.0183

t = 6
0.0024

t = 8
0.0003

t = 10
0.00004

It is more or less obvious that, dc offset is not seen in the waveform after 5 time constants.
The value of I0 can be worked out by setting the current at t t o to zero.
This implies that
I0

Vm
sin(t 0 )
Z

Thus
(
V
V
i (t ) m sin(t ) m sin(t )e
Z
Z

fig.2
Clearly, the peak value of dc offset current depends upon
Time at which fault strikes
Phase angle of ac voltage

& of transmission line

t t 0
)

Figure 2 shows the waveforms of

a) symmetrical ac component
b) dc offset current
c) total current for various values of , & t 0
It can be seen that severity of dc offset component in fault current is maximum when
a)
b) t 0

For example, if angle of transmission line is 800, then with = 800 & t 0

1
=
2 2 50 200

m
sec = 5msec, the severity of dc offset current would equal I 0 Z , which is also the peak

value of symmetrical ac component of the current. This leads us to an important

conclusion. Viz. peak value
1) dc offset current can be as high as the symmetrical ac peak
2) The dc offset current can be positive or negative (see fig2)
3) Dc offset current may be totally absent
eg. If , t 0 0
4) While, in above analysis, we have considered a single phase current, a 3 fault on a 3
transmission line would always induce dc offset current in atleast 2 phases.

In the remaining lecture, we analyze the effect of dc offset current on CT performance.

DC- offset current and CT saturation

8
We now plan to show that CT can saturate on dc offset current. Also, we plan to show
that the resulting distortions in the CT secondary current can be un-acceptably high. While
doing this analysis, we will neglect ac symmetrical component. In other words, we rest our
belief in superposition theorem atleast qualitatively and will finally evaluate effect using it
Notice that the current that we are dealing with is non-linear, a rigorous application of super
position theorem is simply out of question.

First consider an ideal CT excited by the dc offset current source. An ideal CT will faithfully
replicates primary current waveform on the secondary side. Hence, the secondary current
would be given by

i2 (t )

I0
e
N

and the voltage developed across CT secondary would be given by

t

N2
RI
v 2 (t ) 0 e where N N
1
N

Typical voltage waveform is shown in fig. (5)

For simplicity, let us assume that the initial flux in the transformer core at t=0 is zero
( 0 ) 0 ; Then we can compute the flux in the transformer core by using faradays law
V2 N 2

d
dt

(t ) (0)

---------(2)
t

v
0

2 dt

RI 0
1 e
N2

LI 0
(1 e
N2

(t ) (0)

)
t

LI 0
(1 e )
N2
t

LI 0

(1 e )
N2

------- (3)

as a consequence of dc offset current,

Thus, flux in the core increases exponentially to a peak value of

dmax
c

LI 0
N2

as

L Vm
N Z

dmax
c

Vm
Z

10

Note that unlike ac voltage induced flux, which is sinusoidal, this flux is unidirectional. The ac
voltage induced flux has zero average value. However, dc offset induced does not have this
nice feature. The total flux in ideal CT core is a summation of ac flux and dc flux.
The ac flux in the CT core can be obtained by substituting operator

d
by j . Hence
dt

phasor relationship between phase V2 & ac is given by

V2
j N 2

If v2 (t ) Vm sin(t ) , then
ac

Vm

sin(t )
N 2
2

The peak value of ac flux is given by

acmax

Vm
N 2

acmax

R2 I 0max
N 2

max
However Vm R2 I 0

Hence

and peak value of the total flux is given by

acmax dcmax

Vm LI 0max

N 2
N2

In practice, if this flux exceeds the knee-point flux in the core (see fig.), then the CT core
will saturate.

11

As a consequence of CT core saturation, the secondary current would not faithfully replicate
the primary current. Infact, in practice it is observed that CT secondary current is clipped. The
clipping of CT current leads to blinding of the relay which cannot function further. Hence,
CT saturation in presence of dc offset current is a serious problem which relay designers have
to face. Note that dc flux accumulates gradually. (Depends upon the transmission line time
constant ( ). It is apparent that saturation should not occur immediately after the inception of
the fault. Thus, if the relay is fast enough in decision making, it is likely that a relaying
decision would be undertaken before the CT fully saturates. This is another important reason
for increasing the speed of relaying system. For bus-fault protection, where the dc saturation
due to dc offset current can be a significant contributing factor, quarter cycle operations *****
specifically are imposed. Similarly, a distance relay is expected to operate within -1 cycle
time.

CT oversizing factors
Typically, an efficient design of transformer would correspond to choosing the core cross
section such that mac should be near the knee point of B-H curve. One obvious way of
avoiding the CT saturation on dc flux is to oversize the core so that for flux ( acmax dcmax ) , the

( acmax dcmax )
corresponding B is below the knee-point. Hence, the factor
is called core acmax
oversizing factor.

12

dcmax
Core-oversizing factor = 1 max
ac
1

LI o N 2
RI 0 N 2

L
R

X
R

Note that X/R in above equation is the transmission line X/R ratio. For a 220KV line X/R 10.
This would imply that transformer core should be oversized by a factor of 11. For a 400KV
line, typical value of X/R 20. This would imply an oversizing required of about 21 times the
usual design. Clearly this high amount of oversizing is not practical. Thus, the important
conclusion is that, protection engineers have to live with the saturation problem.

Cautions in CT selection:
While choosing a CT for a particular application, it is necessary to observe following
precautions.
1. The CT rating and continuous load current should match. For example, if max load
current is 90A, a 100:5 Ct may be acceptable but 50:5 is not acceptable.
2. The maximum fault current should be less than 20 times the CT rated current. for
example 100:5 CT can be used, so long as burden on the CT & maximum primary fault
current is below 2000A.
3. The voltage rating of CT should be compatible. For example, 100:5 C100 would give
linear response, upto 20 times rated current provided CT burden is kept
below(100/20*5=1 ). With 2 burden, this CT can be used only if maximum current
is limited to 1000A.
4. Parallel of CTs e.g. in differential protection, or with SLG fault can create significant
errors in CT performance. One should in general ascertain that magnetizing current is
kept much below the pick up value.
Following example, illustrates this point

Exercise problems:

13
If the current ratio is adequate for a protection, but CT burden is high; then the
performance of CT may deteriorate due to large magnetizing current and/or saturation problem.
The CT performance can be improved by connecting the CTs in series.

1) Show the dotted terminals for correct secondary series connection

2) What is the VA of CT in fig (a) & (b) respectively?
1) Electromechanical relays tend to saturate at high currents. This reduces the relay burden
on CT, and so that the CT performance at moderately high currents may be considered
better than at relays rated burden at 5A.
2) Use of instantaneous over current relays has the potential to overcome this problem of
saturation of CTs
3) Differential protection can operate on external faults due to the un equal saturation of
CTs
Lecture-6
Examples
6. If a 300:5 class C CT is connected to a meter with resistance R I 1 and
secondary current in the CT is 4.5A find out the primary current voltage
developed across the meter and % rate error. Lead wire resistance R L 0.02
secondary resistance R S of a 300/5 CT 0.15
Diagram
R I 1 , R L 0.02 RS 0.15 I S 4.5 A
Total secondary resistance RT R I R L RS
Secondary voltage I S RT

1.17

4.5 1.17
5.265V

From Fig 5.7,

Exciting current IE for 5.265V
= 0.03A

14
Turns ratio N = 300/5 = 60

I p N (I S I E )

= 60(4.5 + 0.03)
= 271.8A
Voltage across meter I S R I
4.5 1 = 4.5V
IE
0.03
100
100
Ratio error
IS
4.5
= 0.67%
Rb

15
Lecture 8
Examples
1. Design a CCVT for a 132kV transmission line using the following data.
Resistive Burden (3 )150VA
f 3Hz , phase angle error = 40 min
Consider 4 choices of V2 as 33kV, 11kV, 6.6kV and 3.3kV
Diagram 1
Diagram 2
Transmission line voltage V = 132kV. Suppose V2 (P_N) be the voltage to be
produced by the capacitive potential divider with capacitance values C1 and C2
and L the value of tuning inductor. The standardized VT secondary voltage is 110
volts (L-L).
Here specification for phase angle error is 40 minutes variation in frequency
can be upto f 3Hz . Phase angle error for change in by in the above
equation circuit, is given by
1
( L 2 )
C
At tuning frequency 2

1
LC

2
Substituting 1 LC
Phase angle error ( L L)
2 L
2 L
% phase angle error 2
--- (1)
a Rb
Using this equation the value L for different values of V2 is found out.
1) Let V2 be 33kV (L - N)
3V22
150
Rb'

Rb' a 2 Rb 217.810 5
2f 23
40min

40
0.01164 rad
180 60

From eqn (1)

Rb' 0.01164217.810 5
L

2
223

6722.2 H
1
C1 C 2 2 1.5110 9 F 1.5110 3 F
L
2) V2 11kV ( L N )

3 (11103 ) 2
242 104
150
Rb' 0.01164 242 104
L

2
2 2 3
Rb'

16
747.2 H
C1 C 2

2 L (3/ 4) 2 747.2

1.3610 2 F

3) V2 6.6kV
3 (6.6 103 ) 2
'
Rb
150
87.1210 4

Rb' 0.01164 87.12 104

L

2
2 2 3
269H ,

C1 C 2 3.7710 2 F

4) V2 3.3kV
3 (3.3 103 ) 2
Rb'
150
21.7810 4

Rb' 0.01164 21.78 104

2
2 2 3

67.25 H

C1 C2 0.151 F
The values of L, C1 C 2 for different values of V2 are tabulated below.
V2
L
C1 C 2
33kV
6722.2H
0.00151 F
11kV
747.2H
0.0136 F
6.6kV
269H
0.0377 F
3.3kV
67.25H
0.151 F
From the above table it is clear that smaller the value of V2, the smaller is the
value of L and higher the value of C 1 and C2 for tuning condition. If we select too low
value of V2 and L then capacitance values will be beyond available limits, and if we
select higher value of V2 and L, then CCVT and inductor will become bulky. So a
compromise is necessary and let us select V2 = 6.6kV
For V2 = 6.6kV
L = 269H
C1 C 2 0.0377 F
V C1 C 2

Now,
V2
C1
13210 3
36.610

C1

0.037710 6
C1

0.0377 36.610 3 10 6 F
13210 3

0.0033F

17
C 2 0.0344 F

In this design, we explained the basic concept for CCVT design and we assumed
the transformer to be ideal. But in actual design practice the value of magnetizing
impedance of transformer, resistance of reactor etc have to be taken into account,
as ratio error and phase angle error will also get affected by these values.
2. Diagram
The equivalent circuit of a CCVT is shown in fig 8.3. The values of C 1 and C2 are
0.0018 F and 0.018 F respectively. Tuning inductor has an inductance of
497H and resistance of 4620 .
Xm of the 6.6kV VT is 1M , core loss = 20 watts per phase, VA burden =
150VA per phase. Value of Cm for compensating the current drawn by m is equal
to 3.18310 9 F .
(a) Verify the appropriateness of choice of L and Cm.
Ans: If C1 0.0018F and C 2 0.0186 F then the value L of tuning inductor
is given by
1
L 2
(C1 C 2 )
where 2 f and f = tuning frequency
1
L
2
(2 50) (0.0018 0.0186) 10 6
6
= 496.7H which is equal to the given value of L. Now X m 1 10
1
Xm
Cm
1
1
Cm

X m (2 50) 1106
3.183 109 F
The value is also same as the selected value of Cm Hence the selection of both L
and Cm is appropriate.
(b) Find out the nominal value of V/V2
V C1 C2 0.0018 0.0186

Ans:
V2
C1
0.0018
= 11.33
132
kV
V = 11.33 x 6.6
3
(c) If the frequency drops from 50Hz to 47Hz, what would be the values of ratio
error and phase angle error?
Ans: Core loss = 20w
V22
20W
Rm

18
V22 (6600) 2

20
20
6
2.18 10
VA burden = 150VA (resistive)
V22
150
Rb
Rm

V22 (6600) 2

150
150
5
2.904 10
The equivalent circuit can be represented as shown below.
Diagram 8.12
X m 106 at f = 50Hz
Rb

2 f Lm 106
106
3183.1H
2 50
The frequency of interest is 47Hz. Hence values of X m and other impedance can
be calculated at 47Hz. The above circuit can be simplified as
Diagram 8.13
1
1
j
1

jCm
Where
Z Rm X m
Rb
1
j
1

j 2 47 3.183 109
6
2.18 10 2 47 3183.1
2.904 105
0.459 106 j1.064 106 j 0.94 106 3.44 106
(3.902 j 0.124) 106 3.904 106 1.82
1
Z
256147.5 1.82
3.904 106 1.82
256018.32 j8135.15
Vth
I th
j
R j L
Z
C

6600 0

j
4620 j 2 47 497

256018.32

j
8135.15
2 47 0.0204 106

6600 0

4620 j146768.9 j165994 256018.32 j8135.15

6600 0

260638.32 j11089.84
Lm

19
6600 0
A
260874.14 2.44
VT I th Z
6600 0

256147.5 1.82
260874.14 2.44
6480.42 4.26

Hence % ratio error

(6600 6480.42)
100
6600

=1.81%
Phase angle error = 4.26

V2 6.6kV
r 2 2
M
t t0

d 2i
R di
1

i0
2
dt
L dt LCeq

wn

1
R
2 50 2 Iwn
LC
L

d 2i
2 wn wn2i 0 1
2
dt
Lec 8
2
1
n
2 50 2 R d i 2 2i 0 n 1
n
n
n
LCeq
L dt 2
V
t
I 0 m sin(t0 )

e
| Z line |

20