CatchingXpropagationrelatedissuesatRTL

ByBruceGreene,Synopsys|NoComments|Posted:February26,2014
Topics/Categories:EDAVerification(http://www.techdesignforums.com/practice/topics/edatopics/designverification/)|Tags:Xpropagation(http://www.techdesignforums.com/practice/tag/x
propagation/)|Organizations:Synopsys(http://www.techdesignforums.com/practice/organization/synopsys/)

CatchingxpropagationissuesatRTLsavestimeandreducesuncertaintyingatelevelverification
Simulationusuallyinvolvessimplificationsthatmaketheprocessmorepracticalorconvenient.Inlogicdesign,themodelsusedinRTLsimulationhavebeensimplifiedto
makeiteasiertowriteasimulatortorunthem.
Forexample,RTLmodelsandsimulatorssupportXs,whichrepresentunknownoruninitializedBooleanstates.Usingtheseenablesonesimulationruntotestall
permutationsof1,0andtheuncertaintyconditionsXandZthatmayhappenduetoareset,poweronorothereventthatintroducesuncertainty.
WithoutsupportforthisXstate,designerswouldhavetorun2nsimulationstoexploretheconditionofnregisters.ThedisadvantageofsupportingXstatesisthattheycan
propagatethroughasimulation,creatingfalseerrorstatesthatcanonlyberesolvedduringthecostlyandtimeconsumingdebugprocess.
Theresafurtherissue:XstatesarehandleddifferentlyatRTLandgatelevel.
Becauseoftheirsemantics,RTLsimulationscanbeoverlyoptimistic,wronglyturningXstatesinto0sor1s.Gatelevelsimulation,ontheotherhand,canbeoverly
pessimistic,propagatingXstatesunnecessarily.

Whyitmatters
Whyisthis?LetslookatafragmentofRTLcodeimplementedinbothVHDLandVerilog,withapossibleimplementation.

(http://www.techdesignforums.com/practice/files/2014/02/SynopsysVCSXpropfig1.jpg)
FIGURE1DifferinginterpretationsatRTLandgatelevelofunknownstatescancreateverificationissues(Source:Synopsys)

Iftheselectofthemuxisunknown,inputais1,andinputbis0,then:
IntheRTLsimulation,wecheckforctobetrue,butsincecisunknowntheRTLsemanticsmaketheexpressionfalse.TheRTLwillexecutetheElseclause,assigningb
toq,whichgivesanoutputof0.
Inthegatelevelversion,becausecisunknown,theactualoutputisalsogoingtobeunknownanX.
Therealhardwareoutputcouldbe0or1,dependingonthevalueofc.
Inthiscase,RTLoptimismmeansweevaluatetheexpressionasfalse,convertingtheXtoafalsevalueandgettinganincorrectanswer.Thisresultisalsoamismatchwith
boththegatelevelandrealhardwarebehaviors.Inasecondstate,cisXagainbutaandbare1:
TheRTLwillstilltaketheElsebranch,andassignthevalueof1becausecisXandXistreatedasfalse.
Atthegatelevel,westillgetanXvaluebecauseofthereconvergentfanoutofc,causedbyimplementingthemuxastwoAndgatesandanOrgate.
Theactualhardwareoutputwillalwaysbe1,becauseaandbarethesameandchasbecomeadontcare.

Inthiscase,thegatelevelsimulationmodelismorepessimisticthantherealhardware:anXatcispropagatedtoqunnecessarily.Theexampleshowsthatthereis
inconsistencybetweenRTLandgatelevelsimulations,dependingontheinputvalues,makingdebugmoredifficult.TheXoptimismofRTLsimulationcanalsoblockXs
andsoconceallowpowerandreseterrors.

DealingwithXoptimism
TherearevariouswaystodealwithXoptimism:
Runmoregatelevelsimulations,althoughthiscanincreasedebugeffort,duetotheextraXsthatgatelevelsimulationcanthrowup.
UsecodingguidelinestoensuredesignersavoidcodeconstructsthatcreateXoptimisticbehavior.Unfortunately,avoidingIfandCasestatementslimitstheexpressive
powerofHDLs.
Useformaltools,thoughtheymaybelimitedtotheblocklevelandtakealotofconfiguration.
WriteatooltoaddpessimisticbehaviortoRTLcodetoremovetheoptimisticbehavior.Thismakesdebugmoredifficultbecausethetransformedcodedoesntlooklike
theoriginal,andthetransformationmayhaveintroducederrors.
Domultiplesimulationrunswithrandomlyinitializedregisters,althoughthiswontoffergoodcoverageinarealisticamountoftime.
Resetallyourstateelements,retainingalltheregisters,avoidingtheproblemofhavinguninitializedregisters.Thisisntpossibleforalldesignsbecauseittakesrouting
resourcestorunresetlines.Theapproachdoesntcompletelyavoidtheproblem,either,sinceyoucould,forexample,readfromanuninitializedmemorylocation.

TheSynopsyssolution
Oursolution,embodiedinVCSXPropAddon,istomakethesimulatorconsideranXasbotha1anda0simultaneously,substitutingthetwovaluesfortheXduring
evaluationandthenmergingtheresultofthetwoevaluations.ThisreducesthemismatchbetweenRTLandgatelevelsimulation,propagatinguncertaintythroughboth
conditionalconstructsandedgeoperators.

ProblematicconstructsforXoptimism
BothVerilogandVHDLhaveconstructsthatareevaluatedoveroptimisticallywhentheyencounteranXvalue.

IF.ELSEstatements
InIF.ELSEstatements,ifthevaluebeingtestedisunknown,aclassicsimulatorconsiderstheresultasfalseandexecutestheelsebranch.Thisisincorrect,optimistic
behavior,convertinganunknownstateintoavalid0or1.

CASEstatements
InCASEstatements,ifthevaluebeingtestedisunknown,aclassicalsimulatorwillexecutethedefaultbranch,ifoneexists,ornotexecuteanybranchthatcausesthe
variablestoretainstate.Neitherbehaviorishowrealhardwarewouldwork.

EDGEoperators
InVerilog,ifaclockgoesfromXto1,thisisconsideredaclockedge,wheninrealitytheremayormaynothavebeenanedge.BothVerilogandVHDLwilloptimistically
usetheedgetoclockvaluesin,whetherornotrealhardwarewouldactuallyexperiencearealclockedge.

UsingVCSXPropforcombinationalstatements
Considerthiscodefragment:

if(c)begin
a=0;

b=3;

endelsebegin
a=d;

b=e;

inwhichonebranchoftheconditionalgivesonesetofassignmentsandtheother,twootherassignments.IfcisX,aclassicalVerilogsimulatorperformstheElse
assignmentssothatagetsthevalued,andbthevaluee.Inreality,becausecisunknown,weneedtoconsiderthevalueofbothbranchesbeingexecuted,byusingX
Proptoevaluatetheconditionalforthevaluesof0and1,andthenmergingthetworesults:

Whencisx>
a<=merge(0,d);

b<=merge(3,e);

Inaconventionalsimulator,anXvaluewillbeconvertedtoaFalsevalue,whichcausesanexpressiontobeevaluatedwithincorrectresults.WithTmerge,anexpression
yieldsanXoutputwhenalltheinputvaluesaredifferentjustliketheternaryoperatorwould.ThisremovestheoptimismfromRTLmodels.Nowconsideramuxdefinedin
RTLandimplementedinthreeways:withthreeNANDgates,threeNORgates,orasamux.

(http://www.techdesignforums.com/practice/files/2014/02/SynopsysVCSXpropfig2.jpg)
FIGURE2Mergefunctionscanhelpprovideamorerealisticviewoftheimpactofunknownstates(Source:Synopsys)

FortheNANDgateimplementation,theconditionalisalwaysX.TheTmergefunctionwillgiveareallogicalvalueifaandbarethesame,butifaandbaredifferentitwill
giveanXvalue.
ThetablealsoshowstheresultofanXmerge,theother(verypessimistic)mergemode,whichwillunconditionallysetXfortheoutput.
ThetablesYcolumnshowswhatthevalueofYwouldbefortheparticulargatelevelimplementation.
Tmergeforthesecondimplementation,usingthreeNORgates,onlygivesavalueof1whenaandbare1.
Forthemuximplementation,Tmergegivesvaluesof0and1ifaandbarethesame,otherwiseitgivesthevalueX.
Insummary,Tmergeisveryclosetotheactualbehaviorofthehardware,whileXmergewillbemorepessimisticthanthegatelevelsimulation.
TheextrapessimismbuiltintothegatelevelmodelisapparentwhencomparingtheresultsofaTmergeandofY.
SynopsysusuallyrecommendsusingTmerge,whichgivesthecorrectbehaviorminusanyadditionalpessimismthatwouldbeintroducedinagatelevelsimulation.
Xmergeissupportedforthosewhowanttoexploretheworstcasescenarioforanyimplementation.

XPropasappliedtosequentialblocks

(http://www.techdesignforums.com/practice/files/2014/02/SynopsysVCSXpropfig3.jpg)

FIGURE3Unknownstatescanalsohaveanimpactonsequentiallogic(Source:Synopsys)

ConsideralatchcodedasanIfstatement.IfaclocksignalisX,itisnotknownwhetherthelogicwilllatchinthenextvalueorholdthecurrentvalue.XProphandlesthisby
evaluatingbothcasesandmergingtheresultsforbothdandq.
Flipflopsareedgesensitive.Theyexperiencetwotypesofedge:acleanrisingedgeinwhichthesignalgoesfrom0to1and,inVerilog,anambiguousrisingedgein
whichasignalgoesfrom0toX.Inthissecondcase,standardVerilogwill(optimistically)clockinthevalueofdtoq.
UnderXPropsemantics,thesimulatorlooksatthecurrentvalueoftheflop,thed,andtheqandmergesthem.Iftheyaredifferent,thesimulatorassignsanXtotheflop,
butiftheyarethesamethenqholdsitsvalue.ThisisamoreaccuratewayofevaluatingtheexpressionthanclassicalVerilogevaluation.
CASEstatementsaresimilartoaseriesofnestedIFTHENELSEstatements,andmayincludeadefaultbranch.
Ifc,theconditionbeingevaluated,canbe0,1orX,thensubstitutingbotha0anda1forXmeansthatccouldmatchseveralbranchesofthestatement.XProphandles
thisbymergingthemultiplevaluesofthevariablebeingsetbythestatement.
XPropactsmuchasitdoeswithIfstatements,againremovingunnecessaryoptimismintheRTLmodel.

DebuggingwithXProp
XPropisbuiltintoVCSandcanbeinvokedwithaswitchthatappliestheTmergestrategytothewholedesign.
SinceXPropisintendedtostopthesimulatorhandlingXsinanoverlyoptimisticwaywhensimulatingrealhardware,theremaybepartsofyourcodetowhichthestrategy
shouldnotbeapplied.ThereisanXPropconfigurationfileinwhichonecanspecifythedesignhierarchiesthatshouldcontainthemoreaccurateXPropbehavior.
TypicallyauserwouldenableXPropbehavioronthesynthesizablepartoftheirhierarchy.
XPropdoesntdoawaywithallXpropagationissues.OnceXPropisenabled,XscanpropagatethroughIfandCASEstatements,ratherthanoptimisticallybeingturnedin
oreallogicvalues.
Thismeansthatflopsthatwereoptimisticallyclockingdatainmaystopworkingforexample,agatedcellthatwasoptimisticallyresetusingtheclassicalsemanticsisno
longresetundertheXpropsemantics.
Checkersorassertionsinthedesignshouldbeusedtocatchunintendedbehaviors,suchasimproperresets,onehotsignals,Xsoncontrolsignalsetc.,whichXProp
revealswhenmorerealisticallyevaluatingdesigns.
DesignerswillstillneedtouseanHDLdebugger,suchasVerdi(whichsupportstheXPropsemantics),tofindtherootcauseofsuchbugs.

Conclusions
Xpropagationissuesarebecomingmorecommonasaggressivepowermanagementschemesmakeitmorelikelythatpartsofadesignwillbepoweredoffwhenunused,
creatingopportunitiesforthemtoberepoweredinuncertainstates.ThesimplificationsusedtomakesimulationpracticalhavealsoledtoinconsistenciesRTLsimulation
turnsunknownstatesintovalidlogicalvalues,gatelevelsimulationisoverlypessimisticaboutXstateswhilesynthesishandlestheminathirdway.
ChangingsimulatorssothattheyevaluatewhathappensifanXisalogic0or1andthenmergetheresultsaddresstheseissues.ItreducestheoptimismofRTL
simulation,thusexposingerrorsearlierinthedesignflowwhenitissimplerandlesscostlytoaddressthem.

Furtherinformation
Productpage(http://www.synopsys.com/Tools/Verification/FunctionalVerification/Pages/vcsxpropds.aspx)
Datasheet(http://www.synopsys.com/Tools/Verification/FunctionalVerification/Documents/vcsxpropds.pdf)
Webinar(https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=701840&sessionid=1&key=7C4D1D8DE202C3E21AE69222A4F96BB9)

Author
BruceS.GreeneisaPrincipalEngineeratSynopsys.Hisprimaryfocusistohelpcustomerssolvecomplexproblemstogettheirsiliconworkingquicklyandaccurately.He
hasworkedinmanyareasofverificationincludingUVM/VMM,VCS,assertions,andstatictechnologies.BruceenjoysbeingaLectureratSantaClaraUniversityinhisfree
time.HeholdsaMSinElectricalEngineeringfromtheUniversityofIllinoisatUrbanaChampaign,andaPh.D.inElectricalEngineeringfromSantaClaraUniversity.

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