ISSN 2278-3083

International Journal of Science and Applied Information Technology (IJSAIT), Vol.5 , No.1, Pages : 14-19 (2016)
Special Issue of ICECT 2016 - Held on February 27, 2016 in Hyderabad Marriot Hotel & Convention Centre, Hyderabad
http://warse.org/IJSAIT/static/pdf/Issue/icect2016sp04.pdf

Design and Verification of Four Port Router for

Network on Chip
Y Mrudula 1, V Harshavardhan2, G Manu3, Bhavana Godavarthi4
1

Farah Institute of Technology, Hyderabad,mrudulamudu@gmail.com

Farah Institute of Technology, Hyderabad, harsh.velagapudi@gmail.com
3
Farah Institute of Technology, Hyderabad, manug0808@gmail.com
4
Institute of Aeronautical Engineering, Hyderabad, bhavana.bhanu402@gmail.com
2

Abstract: This proposed research paper is a

Multiprocessor system on chip is emerging as a new
trend for System on chip design but the wire and power
design constraints are forcing adoption of new design
methodologies. Researchers pursued a scalable solution
to this problem i.e. Network on Chip (NOC). Network
on chip architecture better supports the integration of
SOC consists of on chip packet switched network. Thus
the idea is borrowed from large scale multiprocessors
and wide area network domain and envisions on chip
routers based network. Cores access the network by
means of proper interfaces and have their packets
forwarded to destination through multichip routing
path. In order to implement a competitive NOC
architecture, the router should be efficiently design as it
is the central component of NOC architecture. Design
and Verify the functionality of the Design and
Verification Four Port Router for Network on Chip IP
core using the latest verification methodologies,
Hardware Verification Languages and EDA tools and
qualify the IP for Synthesis an implementation.

(open verification methodology) is one such efficient

methodology and best thing about it is, it is free. This
ovm is built on system Verilog and used effectively to
achieve maintainability, reusability, speed of
verification etc. This project is aimed at building a
reusable test bench for verifying 8 Port Router Protocol
Bridge by using system Verilog and OV.
The use of OVM and system Verilog to verify a
design and to develop a reusable test bench is explained
in step by step as defined by verification principles and
methodology. The test bench contains different
components and each component is again composed of
subcomponents, these components and subcomponents
can be reused for the future projects as long as the
interface is same.
The report is organized as two major portions; first
part is brief introduction and history of the functional
verification which tells about different technologies,
strategies and methodologies used today for
verification. Literature survey will contain an organized
collection of data from different sources and significant
changes that took place in the verification and design.
Ovm methodology basics illustrate some of the
methodology concepts necessary for understanding of
the project which assumes a prior knowledge of the
system Verilog language.

The Four Router Design is done by using of the three

blocks .the blocks are 8-Bit Register, Router controller
and output block. the router controller is design by using
FSM design and the output block consists of three fifos
combined together the fifos are store packet of data and
when u want to data that time the data read from the
FIFOs. In this router design has three outputs that is 8Bit size and one 8_bit data port it using to drive the data
into router we are using the global clock and reset signals,
and the err signal and suspended data signals are outputs
of the router .the FSM controller gives the err and
suspended_data_in signals

Second part is verification plan specifying the

verification requirements and approaches to attack the
problem, architecture of the test bench gives complete
description about the components and sub components
used to achieve the verification goals and also explains
about improvements made in the design of the usb-i2c
bridge, test plan identifies all the test case required to
meet the goals and finally results of the project.

Keywords: Network-on-Chip, Simulation Router,

FIFO, FSM, Register blocks
1.

1.1 Router

INTRODUCTION

System on chip is a complex interconnection of various

functional elements. It creates communication
bottleneck in the gigabit communication due to its bus
based architecture. Thus there was need of system that
explicit modularity and parallelism, network on chip
possess many such attractive properties and solve the
problem of communication bottleneck. It basically
works on the idea of interconnection of cores using on
chip network.

The challenge of the verifying a large design is

growing exponentially. There is a need to define new
methods that makes functional verification easy.
Several strategies in the recent years have been
proposed to achieve good functional verification with
less effort. Recent advancement towards this goal is
methodologies. The methodology defines a skeleton
over which one can add flesh and skin to their
requirements to achieve functional verification. OVM
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ISSN 2278-3083
International Journal of Science and Applied Information Technology (IJSAIT), Vol.5 , No.1, Pages : 14-19 (2016)
Special Issue of ICECT 2016 - Held on February 27, 2016 in Hyderabad Marriot Hotel & Convention Centre, Hyderabad
http://warse.org/IJSAIT/static/pdf/Issue/icect2016sp04.pdf
The communication on network on chip is
carried out by means of router, so for implementing
better NOC, the router should be efficiently design.
This router supports four parallel connections at the
same time. It uses store and forward type of flow
control and Fsm Controller deterministic routing which
improves the performance of router. The switching
mechanism used here is packet switching which is
generally used on network on chip.
A router is a device that forwards data packets across
computer networks. Routers perform the data "traffic
direction" functions on the Internet. A router is a
microprocessor-controlled device that is connected to
two or more data lines from different networks. When a
data packet comes in on one of the lines. the router
reads the address information in the packet to determine
its ultimate destination. Then, using information in its
routing table, it directs the packet to the next network
on its journey
2.

There are many other useful features, but these

allow you to create test benches at a higher level of
abstraction than you are able to achieve with an HDL or
a programming language such as C.
2.2 Svm Verification Component (Svc)
The following subsections describe the components of
an SVC:
Data Item (Transaction)
Driver (BFM)
Sequencer
Monitor(Receiver)
Generator
Environment
The environment is the top-level component of the
SVC. It contains one or more agents, as well as other
components such as a bus monitor. The env contains
configuration properties that enable you to customize
the topology and behaviour and make it reusable. For
example, active agents can be changed into passive
agents when the verification environment is reused in
system verification. Figure 1-2 on page 15 illustrates
the structure of a reusable verification environment.
Notice that an OVC may contain an environment-level
monitor. This bus-level monitor performs checking and
coverage for activities that are not necessarily related to
a single agent. An agents monitors can leverage data
and events collected by the global monitor.

FOUR PORT ROUTER

The router is a Four Port Network Router has a one

input port from which the packet enters. It has three
output ports where the packet is driven out. Packet
contains 3 parts. They are Header, data and frame check
sequence. Packet width is 8 bits and the length of the
packet can be between 1 bytes to 64 bytes. Packet
header contains three fields DAand length.Destination
address (DA) of the packet is of 8 bits. The switch
drives the packet to respective ports based on this
destination address of the packets. Each output port has
8-bit unique port address. If the destination address of
the packet matches the port address, then switch drives
the packet to the output port, Length of the data is of 8
bits and from 0 to 63. Length is measured in terms of
bytes. Data should be in terms of bytes and can take
anything. Frame check sequence contains the security
check of the packet. It is calculated over the header and
data.

The environment class (ovm_env) is architected to

provide a flexible, reusable, and extendable verification
component. The main function of the environment class
is to model behaviour by generating constrainedrandom traffic, monitoring DUT responses, checking
the validity of the protocol activity, and collecting
coverage

2.1 System Verilog

The most valuable benefit of SystemVerilog is that it
allows the user to construct reliable, repeatable
verification environments, in a consistent syntax, that
can be used across multiple projects
Some of the typical features of an HVL that distinguish
it from a Hardware Description Language such as
Verilog or VHDL are
Constrained-random stimulus generation
Functional Coverage
Higher-level structures, especially Object
Oriented Programming
Multi-threading and inter process
communication
Support for HDL types such as Verilogs 8state values
Tight integration with event-simulator for
control of the design

Figure 1. Typical SVC Environments

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ISSN 2278-3083
International Journal of Science and Applied Information Technology (IJSAIT), Vol.5 , No.1, Pages : 14-19 (2016)
Special Issue of ICECT 2016 - Held on February 27, 2016 in Hyderabad Marriot Hotel & Convention Centre, Hyderabad
http://warse.org/IJSAIT/static/pdf/Issue/icect2016sp04.pdf
OVM Factory
The factory method is a classic software
design pattern that is used to create generic code,
deferring to run time the exact specification of the
object that will be created. In functional verification,
introducing class variations is frequently needed. For
example, in many tests you might want to derive from
the generic data item definition and add more
constraints or fields to it; or you might want to use the
new derived class in the entire environment or only in a
single interface; or perhaps you must modify the way
data is sent to the DUT by deriving a new driver. The
factory allows you to substitute the verification
component without having to provide a derived version
of the parent component as well.

modify the environment object structure without

touching multiple classes.
Test Class
The OVM_test class defines the test scenario for the
testbench specified in the test. The test class enables
configuration of the testbench and environment classes
as well as utilities for command-line test selection.
Although IP developers provide default values for
topological and run-time configuration properties, if
require configuration customization, use the
configuration override mechanism provided by the
SystemVerilog OVM Class Library. To provide userdefined sequences in a file or package, which is
included or imported by the test class. A test provides
data and sequence generation and inline constraints.
Test files are typically associated with a single
configuration. Tests in OVM are classes that are
derived from an OVM_test class. Using classes allows
inheritance and reuse of tests.

The SystemVerilog OVM Class Library provides a

built-in central factory that allows:

Controlling object allocation in the entire

environment or for specific objects.

Modifying stimulus data items as well as

infrastructure components (for example, a
driver).

The testbench is the container object that defines the

testbench topology. The testbench instantiates the
reusable verification IP and defines the configuration of
that IP as required by the application. Instantiating the
reusable environment directly inside the tests has
several drawbacks:

Use of the OVM built-in factory reduces the effort of

creating an advanced factory or implementing factory
methods in class definitions. It facilitates reuse and
adjustment of predefined verification IP in the endusers environment. One of the biggest advantages of
the factory is that it is transparent to the test writer and
reduces the object-oriented expertise required from both
developers and users.
Developing Reusable System Verilog Verification
Components (SVCs) This section describes the basic
concepts and components that make up a typical
verification environment. It also shows how to combine
these components using a proven hierarchical
architecture to create reusable OVCs. The sections
follow the same order you should follow when
developing an OVC:
I.
Modeling Data Items for Generation Data
items
II.
Creating the Driver
III.
Creating the Monitor
IV.
Instantiating Components
V.
Creating the Environment

The test writer must know how to

configure the environment.

Changes to the topology require updating

multiple test files, which can turn into a
big task.

The tests are not reusable because they

rely on a specific environment structure.

Ovm Configuration Mechanism

An SVC is created on a per-protocol basis for
general purpose protocol related use. It may support
various features or operation modes that are not
required in a particular project. OVM provides a
standard configuration mechanism which allows you to
define the SVCs configuration to suit the current
projects requirements. The SVC can get the
configuration during run time or during the build
process. Doing this during the build allows you to

Figure 1.1 Complete block diagram of verification

Environment
Router Design Principles
Router is a packet based protocol. Router drives the
incoming packet which comes from the input port to
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ISSN 2278-3083
International Journal of Science and Applied Information Technology (IJSAIT), Vol.5 , No.1, Pages : 14-19 (2016)
Special Issue of ICECT 2016 - Held on February 27, 2016 in Hyderabad Marriot Hotel & Convention Centre, Hyderabad
http://warse.org/IJSAIT/static/pdf/Issue/icect2016sp04.pdf
output ports based on the address contained in the
packet.The router has a one input port from which the
packet enters. It has three output ports where the packet
is driven out. The router has an active low synchronous
input reset which resets the router.

ROUTER INPUT PROTOCOL

The characteristics of the DUV input protocol are as
follows:

Figure 2.2 Router Input Protocol

ROUTER OUTPUT PROTOCOL
Figure 2. Block Diagram of Four Port Router
Data packet moves in to the input channel of one
port of router by which it is forwarded to the output
channel of other port. Each input channel and output
channel has its own decoding logic which increases the
performance of the router. Buffers are present at all
ports to store the data temporarily.The buffering
method used here is store and forward. Control logic is
present to make arbitration decisions. Thus
communication is established between input and output
ports.. According to the destination path of data packet,
control bit lines of FSM are set. The movement of data
from source to destination is called switching
mechanism The packet switching mechanism is used
here, in which the flit size is 8 bits .Thus the packet size
varies from 0 bits to 8 bits. A detailed explanation of
Design is as follow

Figure 2.3 Router output Protocol

Router Architecture
The Four Router Design is done by using of
the three blocks .the blocks are 8-Bit Regiter, Router
controller and output block. the router controller is
design by using FSM design and the output block
consists of three fifos combined together the fifos are
store packet of data and when u want to data that time
the data read from the FIFOs. In this router design has
three outputs that is 8-Bit size and one 8_bit data port it
using to drive the data into router we are using the
global clock and reset signals, and the err signal and
suspended data signals are outputs of the router .the
FSM controller gives the err and suspended_data_in
signals .this functions are discussed clearly in below
FSM description
The router_reg module contains the status,
data and parity registers for the Network
router_1x3.These registers are latched to new status or
input data through the control signals provided by the
fsm_router.There are 3 fifo for each output port, which
stores the data coming from input port based on the
control signals provided by fsm_router module.The
fsm_router block provides the control signals to the
fifo, and router_reg module.

Packet Format
Packet contains 7 parts. They are Header, payload
and parity.
Packet width is 8 bits and the length of the packet can
be between 1 bytes to 67 bytes.

Figure 2.1 Packet format

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ISSN 2278-3083
International Journal of Science and Applied Information Technology (IJSAIT), Vol.5 , No.1, Pages : 14-19 (2016)
Special Issue of ICECT 2016 - Held on February 27, 2016 in Hyderabad Marriot Hotel & Convention Centre, Hyderabad
http://warse.org/IJSAIT/static/pdf/Issue/icect2016sp04.pdf
ii.
iii.
iv.

Read operation
Read and
Write Operation

Figure 3.3 Four port Router FIFO

Figure 3. Four Port Router Architecture

SIMULATION RESULTS
The below figures shows the simulation results
of test cases applied to the DUT. Figure 4.3 shows the
response of the device for the control test case at the
usb interface. Figure 4.2 shows the master transmitter
sending random data to the external slave device.

The Router blocks are

Register
Router controller(FSM)
FIFO Output Block

Figure 3.1 Four Port Router Register

Figure 4. Simulation results of Four Port Router for

Noc
SYNTHESIS REPORT

Figure 3.2 Four port Router Controller State machine

Router Output Block
There are 7 fifos used in the router design.
Each fifo is of 8 bit width and 16 bit depth.
The fifo works on system clock. It has synchronous
input signal reset.If resetn is low then full =0, empty =
1 and data_out = 0
The FIFO has doing 7 deferent operations
i.
Write Operation

Figure 4.1 Coverage report using one test case

18

ISSN 2278-3083
International Journal of Science and Applied Information Technology (IJSAIT), Vol.5 , No.1, Pages : 14-19 (2016)
Special Issue of ICECT 2016 - Held on February 27, 2016 in Hyderabad Marriot Hotel & Convention Centre, Hyderabad
http://warse.org/IJSAIT/static/pdf/Issue/icect2016sp04.pdf
coverage of Router. In this project used one master and
eight slaves to monitor the Router. Thus the functional
coverage of Router was improved.
The results shows that System Verilog
methodology can be used to make reusable test benches
successfully. Large part of the test bench is made
reusable over multiple projects.even though
this
reusablity is limited to the interfaces. A large class of
devices that are build on these inerfaces can be verified
successfully. Once these components are made the
amount of time required to build test benches for other
projects can be reduced a lot.
REFERENCES
[1] Verilog HDL- Digital Design and Synthesis, by
Samir Palnitkar.
[2] M. K. Papamichael, J. C. Hoe, and O. Mutlu, FIST:
A Fast, Lightweight, FPGA-Friendly Packet Latency
Estimator for NoC Modeling in Full-System
Simulations, NOCS, 2011.
[3] Xilinx, LogiCORE IP Processor Local
Bus(PLB)v4.6,http://www.xilinx.com/support/docume
ntation/i pdocumentation/plb v46.pdf .
[4] P. Wolkotte, P. Holzenspies, and G. Smit, Fast,
Accurate and Detailed NoC Simulations, NOCS, 2007.
[5] System Verilog Manuals by Mentor.
[6] LRM, IEEE Standard Hardware Description
Language Based on the Verilog Hardware Description
Language IEEE STD 1364-1995.
[7]
Chris
Spears
SYSTEMVERILOG
FOR
VERIFICATION, Publisher: Springer
[8] Cisco Router OSPF: Design& Implementation
Guide, Publisher: McGraw-Hill

Figure 4.2 Synthesis results of Four Port Router for

Noc.

Figure 4.3 Synthesis results of a FIFO

CONCLUSION
As the functional verification decides the
quality of the silicon, we spend 60% of the design cycle
time only for the verification/simulation. In order to
avoid the delay and meet the TTM, we use the latest
verification methodologies and technologies and
accelerate the verification process. This project helps
one to understand the complete functional verification
process of complex ASICs an SoCs and it gives
opportunity to try the latest verification methodologies,
programming concepts like Object Oriented
Programming of Hardware Verification Languages and
sophisticated EDA tools, for the high quality
verification.
In this Four Port Router project Design and
verified the functionality of Router with the latest
Verification methodology i.e. System Verilog and
observed the code coverage and functional coverage of
Router by using cover points ,cross and different test
cases like constrained, weighted and directed testcases
.By using these testcases improved the functional
19