Propagation losses in undoped and n-doped

polycrystalline silicon wire waveguides

Shiyang Zhu*, Q. Fang, M. B. Yu, G. Q. Lo, and D. L. Kwong
Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 11 Science Park Road, Science
Park-II, Singapore 117685
*zhusy@ime.a-star.edu.sg

Abstract: Polycrystalline silicon (polySi) wire waveguides with width

ranging from 200 to 500 nm are fabricated by solid-phase crystallization
(SPC) of deposited amorphous silicon (a-Si) on SiO2 at a maximum
temperature of 1000C. The propagation loss at 1550 nm decreases from 13.0
to 9.8 dB/cm with the waveguide width shrinking from 500 to 300 nm while
the 200-nm-wide waveguides exhibit quite large loss (>70 dB/cm) mainly due
to the relatively rough sidewall of waveguides induced by the polySi dry etch.
By modifying the process sequence, i.e., first patterning the a-Si layer into
waveguides by dry etch and then SPC, the sidewall roughness is significantly
improved but the polySi crystallinity is degraded, leading to 13.9 dB/cm loss
in the 200-nm-wide waveguides while larger losses in the wider waveguides.
Phosphorus implantation causes an additional loss in the polySi waveguides.
The doping-induced optical loss increases relatively slowly with the
phosphorus concentration increasing up to 1 1018 cm3, whereas the 5 1018
cm3 doped waveguides exhibit large loss due to the dominant free carrier
absorption. For all undoped polySi waveguides, further 12 dB/cm loss
reduction is obtained by a standard forming gas (10%H2 + 90%N2) annealing
owing to the hydrogen passivation of Si dangling bonds present in polySi
waveguides, achieving the lowest loss of 7.9 dB/cm in the 300-nm-wide
polySi waveguides. However, for the phosphorus doped polySi waveguides,
the propagation loss is slightly increased by the forming gas annealing.
2009 Optical Society of America
OCIS codes: (230.7370) Waveguides; (130.3120) Integrated optical devices; (230.3990)
Microstructure devices.

References and links

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1. Introduction
Although most of the major advances in silicon photonics have been based on single-crystalline
silicon-on-insulator (SOI), the demands for polycrystalline silicon (polySi) based photonic
devices are increasing owing to the unique feature of polySi as it can be easily grown on almost
any substrate by standard techniques and simultaneously it has electron mobility of the order of
100 cm2/Vs, making it still capable of being used as electrically active layers. In high-speed
metal-oxide-semiconductor (MOS) capacitor-based silicon optical modulators and in horizontal
slot waveguides for electrical injection [1,2], polySi has been utilized as part of the waveguide
material above a thin oxide layer where the fabrication of a single-crystalline silicon layer is
difficult. More importantly, polySi-based photonics provides a simple solution for multi-level or
three-dimensional (3-D) integration of optical networks in Si integrated circuits. Ring resonators
and electro-optics modulators entirely based on the deposited polySi films have been
demonstrated recently [3,4].
However, polySi-based photonic devices suffer a major limitation a relatively large
propagation loss in polySi waveguides due to light absorption and scattering at the grain
boundaries is present in polySi. Because polySis nature depends strongly on the fabrication
details [5], the losses in polySi waveguides also depend strongly on the detailed fabrication
process. Historically, polySi waveguides fabricated on directly deposited polySi layers exhibit
very large optical loss (>70 dB/cm) mainly because of the rough surface of the polySi layer
and/or the small grain size [6,7]. The loss was reduced to ~34 dB/cm after smoothing the surface
by chemical mechanical polishing (CMP) [7]. On the other hand, polySi waveguides fabricated
by solid-phase crystallization (SRC) of deposited amorphous silicon (a-Si) exhibit a relatively
low loss due to its smooth surface and/or large grain size [8,9]. ~11 dB/cm loss was reported for
the 200-nm-thick polySi waveguides and the loss was further reduced to ~9 dB/cm by remote
electron cyclotron resonance (R-ECR) plasma hydrogenation [8]. By replacing the cladding
material from SiO2 to SiON, ~6.45 dB/cm loss for the TE mode and ~7.11 dB/cm for the TM
mode were reported [9], which approaches its SOI counterparts [10]. However, in all the above
reports [24,8,9], a 1100C/long-time annealing procedure was carried out in order to crystallize
the a-Si into polySi with the maximum grain size. However, such a high thermal budget restricts
the polySi layers to be fabricated before any doping procedure, thus making it difficult to be
implemented in the 3-D integration and even in the MOS-type modulator fabrication because
some doping procedures have to be done before the polySi waveguide fabrication. Thus, it is
extremely important to reduce the thermal budget for the polySi waveguide fabrication without
sacrificing its optical loss property. Moreover, when polySi is used as active layers in photonic
devices, it is usually is doped. However, the doping effect on the optical loss in polySi
waveguides has not been reported yet in literature.
In this work, firstly, the maximum temperature for the polySi waveguide fabrication is
reduced from 1100C to 1000C. Secondly, two fabrication approaches are compared: in one
(normal) approach, the as-deposited a-Si film is first crystallized into polySi and then this polySi
film is patterned into waveguide structures by dry etch; in the other (modified) approach, the asdeposited a-Si film is first patterned into the waveguide structures by dry etch and then
crystallized them into polySi. Thirdly, some polySi waveguides are uniformly doped by
phosphorus with the concentration ranging from 1 1017 to 5 1018 cm3 by ion implantation,
and the doping effect on the propagation loss is evaluated. Finally, a standard forming gas (FG)
annealing is carried out for some wafers and the influence of FG annealing on both undoped and
n-doped polySi waveguides is investigated.
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2. Experimental
~2-m-thick SiO2 layer was deposited on 8-inch, <100>-oriented Si wafers using high-density
plasma (HDP) chemical vapor deposition (CVD) at 700C as the bottom cladding layer. The asdeposited HDP-SiO2 film has quite a smooth surface with the root mean square (RMS) surface
roughness of ~0.13 nm, as measured by atomic force microscope (AFM). The scanning area in
the AFM measurements is kept at 5 m 5 m throughout this paper. A 220-nm-thick a-Si
layer was then deposited by low-pressure CVD (LPCVD) at 540C from SiH4. The surface
roughness of as-deposited a-Si is ~0.34 nm. In the normal approach, the a-Si film was
crystallized into polySi using a two-step annealing procedure in a pure N2 ambient: first at
575C for 15 h and then at 1000C for 0.5 h. The surface roughness after the first and second
annealing step is ~0.38 nm and ~0.39 nm, respectively, in agreement with the previous reports
that the polySi film formed by SPC has quite a smooth surface [8,9]. After a 50-nm-thick
plasma-enhanced CVD (PECVD) SiO2 deposition and photoresist coating, the waveguide
structures were patterned using 248-nm deep UV lithography. The thin SiO2 layer was first dry
etched by CF4 using the photoresist as mask, followed by photoresist stripping by O2 + N2, and
then the polySi layer was dry etched down to the bottom SiO2 layer using the thin SiO2 layer as
the hard mask by the gaseous mixture of Cl2 + He-O2. After wet etching the remaining SiO2 and
depositing a 5-nm-thick screening SiO2, two-energy (30 and 100 keV) phosphorus implantation
was carried out for some wafers, followed by rapid thermal annealing (RTA) at 1030C for 30 s
for dopant activation. The implantation dose was chosen based on the Tsuprem4 simulation to
make a uniform phosphorus distribution in polySi waveguides with concentration of ~1 1017,
~5 1017 cm3, ~1 1018 cm3, and ~5 1018 cm3, respectively. Standard forming gas (10% H2
+ 90% N2) annealing was carried out at 420C for 30 min for some wafers. Then, ~2-m
PECVD SiO2 was deposited at 400C as the upper cladding layer. To form smooth chip facets
for the end-fire coupling, deep trenches were fabricated by dry etch of 4-m-deep SiO2 and
subsequent ~120-m-deep Si, located at the intervals between chips. The wafers were then diced
along the middle of the deep trenches without touching their sidewall. Since the sidewall of the
deep trenches was quite smooth hence there was no need to manually polish the chip facets after
the wafer dicing.
In the modified approach, the a-Si film was first patterned with the waveguide structures
using lithography and dry etched down to the SiO2 layer using a 50-nm-thick SiO2 layer as the
hard mask. The same abovementioned dry etch recipe was used. Then, the a-Si wire waveguides
were crystallized into polySi using the abovementioned two-step annealing procedure. The other
processes are exactly the same as those in the normal approach. For comparison, some chips
taken from the fabricated wafers were additionally annealed at 1100C for 1 h in N2 ambient.
The waveguide patterns have a width of 200, 300, 400, and 500 nm. All waveguides contain
a 200-nm-wide, 200-m-long inverted taper structure at both facets for coupling. The scanning
electron microscopy (SEM) image of a waveguide near the tip area is shown in the inset of Fig.
1. No differences are observed from SEM images in waveguides fabricated by the normal and
modified approaches. There are 7 waveguides with lengths ranging from 0.69 to 2.68 cm for
each width set. Each waveguide contains 10 identical bends with a large bend radius of 20 m
(thus the bend induced loss is negligible [10]). 1550-nm light output from a stabilized laser
source is coupled from a lensed fiber in to the waveguide in one facet and coupled out to another
lensed fiber in the opposite facet. The fibers and the chip under test were mounted on an XYZ
micrometer piezo-stage for precision alignment to search the maximum output power (dBm).
The insertion loss (dB) of waveguide is obtained after subtracting the fiber-to-fiber loss (dBm),
i.e., the maximum output power measured without propagating through the waveguide. The
propagation losses of TE mode were also measured for several samples using a polarizationmaintaining fiber and a polarization controller. The measured loss values are quite close (the
difference is within 1 dB/cm) to those measured without the polarization control, in agreement
to the previous report [9]. Therefore, for simplicity, the loss data reported in this paper were all
measured without polarization control. Figure 1 shows one example of the measured insertion
losses as a function of waveguide length. They exhibit quite good linearity. By linearly fitting

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the experimental points, the propagation loss and the coupling loss are extracted for each
waveguide width. The coupling loss (including two facets) is around 5.56.5 dB for all
waveguide sets. Taking the possible variation of coupling loss among waveguides into account,
the error of propagation loss determined by such a cutback method is estimated to be less than
1.0 dB. However, the linearity of experimental points becomes poorer and the error becomes
larger if the output power becomes very small (e.g., < 50 dBm). Therefore, the propagation
loss in waveguides with very large loss (e.g., >50 dB/cm) cannot be accurately determined.

Fig. 1. Insertion losses of polySi waveguides as a function of the waveguide length for three width
sets. The linear fitting lines are also shown, from which the propagation losses and the coupling
losses are extracted. The inset shows a SEM image of the waveguide near the tip area.

3. Results and discussion

3.1 Effect of waveguide width
Table 1 summarizes the propagation losses at 1550 nm in the undoped polySi wire waveguides
with height of 220 nm and widths of 200, 300, 400, and 500 nm, fabricated using the normal and
the modified approaches. For waveguides fabricated by the normal approach (i.e., first SPC and
then patterning), the propagation losses are 13.0, 11.3, and 9.8 dB/cm for width = 500, 400, and
300 nm, respectively, while the 200-nm-wide waveguides have large loss (>70 dB/cm). It is
well known that the light attenuation in polySi waveguides can be attributed to two main
origins: one relates to the light absorption and scattering at the grain boundaries present in the
waveguides (namely the bulk loss) and the other relates to the light scattering at the
core/cladding interface (namely the interface loss). Because the narrower wire waveguides
contain relatively less grains in the waveguides and they confine light less tightly (i.e., the light
mode spreads more widely in the surrounding SiO2 layer), the bulk loss decreases while the
interface loss increases with the waveguide width shrinking. The results show that the overall
loss decreases with the waveguide width shrinking from 500 to 300 nm, indicating that the bulk
loss dominates in waveguides with the width larger than 300 nm. Because the bulk loss is
determined by the grain size and/or crystalline fraction of polySi, which can be improved by
higher temperature annealing, we can expect that polySi waveguides fabricated at lower
temperature have larger bulk loss. This is seen in the 575C annealed polySi waveguides which
have much larger losses and this loss increases more rapidly with the waveguide width
increasing from 300 to 500 nm (see Table 1). For the 1100C annealed polySi waveguides
reported in [9], on the other hand, the overall loss is relatively small and it decreases (not
increases) slightly with the waveguide width increasing from 300 to 700 nm [9], indicating that
the bulk loss is not the dominant contributor for those waveguides.
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Table 1. Propagation losses at 1550 nm in various undoped polySi wire waveguides,

extracted from the cutback method. The error is estimated to be less than 1.0 dB/cm.

Waveguides fabrication details

First crystallization,
then patterning
First patterning, then
crystallization

575C/15 h
Additional 1100C/1 h
575C/15 h + 1000C/0.5 h
Additional 1100C/1 h
575C/15 h + 1000C/0.5h
Additional 1100C/1 h

200 nm
>70
>70
>70
>70
13.9
13.9

Loss (dB/cm)
300 nm 400 nm
31.0
~54
16.4
10.2
9.8
11.3
10.9
10.0
16.3
18.1
13.1
15.1

500 nm
>70
11.7
13.0
11.1
25.7
20.1

After an additional 1100C/1 h annealing, the losses in the initial 1000C annealed
waveguides become 10.9, 10.0, and 11.1 dB/cm for widths of 300, 400, and 500 nm,
respectively, very close to those reported by Liao et al. where the polySi layers were crystallized
at a maximum temperature of 1100C. We can see that the losses in the 400- and 500-nm-wide
waveguides reduce slightly after the additional annealing, which can be attributed to the
reduction of bulk loss due to the further crystallization of polySi. For the initial 575C annealed
polySi waveguides, as expected, the loss reduction is more significant after the additional
1100C annealing. The 400- and 500-nm-wide waveguides have losses of 10.2 and 11.7 dB/cm,
respectively, very close to those of the initial 1000C annealed waveguides, indicating that the
crystallization of polySi is almost saturated after the 1100C annealing [9]. However, the loss in
the 300-nm-wide waveguides becomes slightly larger after the additional 1100C annealing,
which should be attributed to the increase of interface loss because the higher temperature
annealing may slightly roughen the polySi waveguide interface. The above results indicate that
although the higher temperature annealing (here 1100C) is beneficial for the bulk loss
reduction due to the improvement in crystallinity, its contribution to the overall loss decreases
with the waveguide width shrinking and it may even becomes detrimental to the overall loss as
the interface loss may increase slightly after the higher temperature annealing. For the 300-nm
waveguides, the 1000C anneal is sufficient to reach the lowest overall loss.
3.2 Effect of fabrication approach
The 200-nm-wide waveguides fabricated by the normal approach have a very large loss, which
can be attributed to the large interface loss. Based on simulation of waveguides with identical
interface roughness, it has been known that the interface loss increases with the waveguide
width decreasing, and becomes substantially large for the width narrower than 300 nm [9,11].
Because the polySi waveguides have quite smooth bottom and top interfaces, we deduce that the
loss mainly originates from the relatively rough sidewall induced by the dry etch process. Due to
the lack of suitable measurement tools, e.g., the 3-D AFM tool, we cannot directly measure the
sidewall roughness. Alternatively, the dry etch related surface roughness is estimated using the
following experiments. In one experiment, a 400-nm-thick a-Si film was crystallized into polySi
using the abovementioned two-step annealing method. The surface roughness was measured to
be ~0.7 nm. Then the polySi film was partially etched by ~200 nm using the same recipe as that
was used for the waveguide etch. The roughness of the remaining polySi film became ~4.0 nm.
The relatively rough surface of the partially dry-etched polySi film may be attributed to the nonhomogeneous etch nature of polySi layer because of the presence of grain boundaries and/or
different grain facets in the surface of polySi layer. We suspect that the waveguide sidewall may
have the RMS roughness in the range of ~4.0 nm, close to the other groups estimation [8,12]. In
the other experiment, a 400-nm a-Si film (the surface roughness is ~0.4 nm) was partially etched
by ~300 nm using the same dry etching recipe, the surface roughness of the remaining ~100-nm
a-Si layer was measured to be ~0.4 nm. After crystallization using the abovementioned two-step
annealing process, the roughness of polySi was measured to be ~0.5 nm. The relatively smooth
surface of the partially etched a-Si can be attributed to the homogenous etch nature of a-Si,
which is also partially confirmed by the fact that very low loss a-Si waveguides can be

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fabricated [13]. Our experiment indicates that the partially dry-etched a-Si layer retains the
smooth surface after SPC, just like the as-deposited a-Si layer. We thus suspect that the
waveguides fabricated using the modified approach (i.e., first patterning the a-Si and then
crystallization) may have smooth sidewall with the RMS roughness in the range of ~0.5 nm.
The losses of polySi waveguides fabricated by the modified approach are also listed in Table
1. The losses are 13.9, 16.3, 18.1, and 25.7 dB/cm for the waveguides with widths of 200, 300,
400, and 500 nm, respectively. We see that the 200-nm-wide waveguides have much lower loss
than those fabricated by the normal approach, confirming that these waveguides really have a
reasonable smooth sidewall. However, the wider waveguides have larger loss and the loss
increases with the waveguide width more rapidly than those fabricated by the normal approach.
It indicates that the waveguides fabricated by the modified approach have larger dominant bulk
loss, most probably due to their smaller grain size and/or poorer crystallinity than those
fabricated by the normal approach. Since the same thermal treatment is carried out in both
approaches, it indicates that the crystallization of a-Si may be layout-dependent, namely, the
crystallization of a-Si wire is not as effective as the crystallization of a-Si film under the same
annealing condition. One possible reason may be attributed to the fact that the a-Si wire has a
much larger interface-volume ratio than the a-Si film since the initial nucleation may occur
more easily at the interface and the subsequent grain growth may terminate at the interface, the
grain size in the final polySi wire is smaller (thus containing more grain boundaries) than that in
the final polySi film after the same thermal treatment. Another possible reason is that the grain
growth rate in the a-Si wire may be smaller than that in the a-Si film under the same thermal
treatment, thus leading to a smaller crystalline faction in the final polySi wire waveguides. To
understand this behavior unambiguously, more experimental studies are necessary, such as
refractive index measurement, x-ray diffraction (XRD), and transmission electron microscopy
(TEM), etc. which is still ongoing. After an additional annealing at 1100C for 1 h, as expected,
the losses in waveguides with the width 300 nm are reduced due to further crystallization of
the polySi waveguides, like those fabricated by the normal approach. However, the final losses
in these waveguides (except the 200-nm-wide waveguides) after the additional 1100C/1 h
annealing are not as low as those fabricated by the normal approach, which can also be ascribed
to the insufficient crystallization of polySi wire waveguides. For the 200-nm-wide waveguides,
the loss keeps almost the same after the additional 1100C annealing probably due to the
contrary effects of the additional high-temperature annealing on the bulk loss and the interface
loss.
Nevertheless, the modified approach can significantly improve the sidewall roughness of the
polySi waveguides, which compensates the degradation of its crystallization. This approach can
be used to fabricate very narrow wire waveguides (e.g., 200 nm) where the interface loss
dominates. Furthermore, if the crystallization of a-Si wire can be improved, such as using the
laser annealing technology, very low loss polySi wire waveguides may be expected.
3.3 Effect of phosphorus doping
The doped Si waveguides may have two additional loss origins: one from the free carrier
absorption and the other from the absorption and/or scattering in the possible doping-related
defects. The former is an intrinsic and useful effect in the active photonic devices whereas the
latter should be minimized. Using the well known formula for the 1550-nm wavelength: =
8.5 1018 N + 6.0 1018 P, where (cm1), N (cm3), and P (cm3) are the
absorption-coefficient, the free electron density, and the free hole density, respectively [14], it
can be calculated that the 1 1018 cm3 n-type doping causes ~36 dB/cm bulk loss purely due to
the free-carrier absorption if every dopant contributes a free electron. For the SOI strip
waveguides, we have experimentally measured that the undoped waveguide has a loss of ~1
dB/cm, the 1 1018 cm3 phosphorus doped waveguide has a loss of ~24 dB/cm, and the 1
1019 cm3 phosphorus doped waveguide has a very large loss, roughly in agreement with those
calculated from the above formula taking the waveguide geometry (thus the light mode
confinement factor) into account.
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Fig. 2. The phosphorus-induced additional loss ( = loss of doped waveguide loss of

corresponding undoped waveguide) as a function of phosphorus concentration. The solid symbols
represent those fabricated by the normal approach and the open symbols represent those
fabricated by the modified approach.

Figure 2 shows the additional loss induced by phosphorus doping in polySi waveguides as a
function of the doping concentration. As expected, the additional loss increases with the doping
concentration. The increasing rate depends on both the waveguide size and the fabrication
approach, and is relatively slow for concentration up to 1 1018 cm3, whereas the 5 1018 cm3
doped waveguides have a very large loss due to the domination of the free carrier absorption.
Comparing the 1 1018 cm3 doped polySi and SOI waveguides, we can see that the additional
loss induced by phosphorus doping in the polySi waveguides is smaller than that in the SOI
waveguides, probably because some dopants in polySi waveguides are segregated at the grain
boundaries so that they do not contribute free electrons. The polySi waveguides fabricated by
the modified approach may have more significant phosphorus segregation effect because they
have smaller grain size and/or poorer crystallinity. We can see that these waveguides have even
smaller additional loss induced by the 1 1018 cm3 phosphorus doping. The above results allow
us to draw a conclusion that the phosphorus doping induced addition loss in polySi waveguides
may be still mainly determined by the free carrier absorption, as the SOI counterparts. In other
words, the loss induced by the possible doping-related defects, such as those segregated at the
grain boundaries, is minor.
3.4 Effect of forming gas anneal
It has been known that hydrogen passivation of dangling bonds at the grain boundaries in polySi
waveguides can reduce the propagation loss [8]. It was argued that among various passivation
techniques, the standard forming gas (FG) annealing is not an effective technique to passivate
the dangling bonds in polySi films [5]. However, there was a report that the polySi waveguide
loss is reduced from ~14 to ~11 dB/cm after the FG annealing [12].
Figure 3 shows the FG annealing induced loss variation of our undoped and n-doped polySi
waveguides. For the undoped polySi waveguides fabricated by either the normal approach or the
modified approach, ~1-2 dB/cm loss reduction is obtained after the standard FG annealing, in
agreement to that reported in [11]. The lowest loss is achieved to be 7.9 dB/cm in the 300-nmwide polySi waveguides and the 200-nm-wide polySi waveguides have a loss of 12.8 dB/cm.
The effectiveness of the FG annealing for the loss reduction in undoped polySi waveguides may
be attributed to the fact that the FG annealing is carried out after the waveguide patterning so
that the surface-to-volume ratio is larger than that in the case of poly-Si film. The dangling
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bonds at the polySi waveguide sidewall can be passivated by hydrogen from the FG gas
ambient, unlike in the case of polySi films where the passivation depends on the diffusion of
hydrogen from the surface into the bulk. Several FG annealed chips were re-measured after
storing them at room-temperature for several weeks, the measured propagation losses show no
substantial variation, indicating that the FG annealing induced hydrogen in polySi waveguide is
quite stable at room temperature.

Fig. 3. The forming gas anneal-induced loss variation ( = loss of FG annealed waveguide loss of
corresponding waveguide without the FG anneal) for undoped and doped polySi waveguides. The
solid symbols represent those fabricated by the normal approach and the open symbols represent
those fabricated by the modified approach.

However, for the phosphorus doped polySi waveguides, Fig. 3 shows that the loss increases,
by ~0.14.9 dB/cm, after the FG annealing. The amount of loss increase depends on both the
phosphorus concentration and the waveguide width: slightly larger for the higher phosphorus
concentration. A possible explanation of this phenomenon is that the dangling bonds in the grain
boundaries may already have combined with phosphorus because phosphorus in polySi tends to
segregate at the grain boundaries [5], therefore, during the FG annealing, hydrogen cannot
passivate the dangling bonds, instead, the hydrogen and phosphorus may form a cluster at the
dangling sites during the FG annealing. These clusters may contribute to light absorption and/or
scattering, leading to a slightly enhanced light attenuation in the FG annealed n-type doped
polySi waveguides. More studies are still on-going to fully understand the physics beyond this
phenomenon.
4. Conclusion
The propagation losses in various polySi wire waveguides are measured using the cutback
method. Although a lower crystallization temperature leads to a higher bulk loss, its contribution
to the overall loss decreases as the waveguide width decreases. For the 300-nm-wide
waveguides, the 1000C annealing is sufficient to give the lowest loss. The modified approach,
i.e., patterning the a-Si into waveguides first and then crystallization, can significantly improve
the sidewall roughness of final polySi waveguides but the crystallization property of polySi is
degraded, leading to a relatively low loss in the 200-nm-wide waveguides but lager loss in the
wider waveguides. The additional loss in polySi waveguides due to phosphorus doping is
smaller than that in the corresponding SOI waveguides. This is probably due to the phosphorus
segregation in polySi. The loss due to the possible doping-related defects is minor. For undoped
polySi waveguides, the standard FG annealing can further reduce the loss by 12 dB/cm, while
for the phosphorus-doped polySi waveguides, the losses increase slightly after the FG annealing.
#114418 - $15.00 USD

(C) 2009 OSA

Received 28 Jul 2009; revised 8 Sep 2009; accepted 9 Sep 2009; published 30 Oct 2009

9 November 2009 / Vol. 17, No. 23 / OPTICS EXPRESS 20898

Acknowledgements
The authors would like to thank Ushida-san, Fujikata-san, and Nakamura-san from NEC, Japan,
for useful discussions. The authors would also like to thank the staffs from the SPT Lab for their
assistance in wafer fabrication, Ms. Sandy Wang from MMC Lab for wafer dicing, and Mr.
Joseph Weisheng Ng from IME for English correction.

#114418 - $15.00 USD

(C) 2009 OSA

Received 28 Jul 2009; revised 8 Sep 2009; accepted 9 Sep 2009; published 30 Oct 2009

9 November 2009 / Vol. 17, No. 23 / OPTICS EXPRESS 20899