Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
NANOSCALE CIRCUITS
SEMINAR REPORT
Submitted in partial fulfillment with the requirements for the award of the degree
of
BACHELOR OF TECHNOLOGY
in
ELECTRONICS AND COMMUNICATION ENGINEERING
of
Cochin University of Science and Technology
by
SHILPA SUSAN BIJI
REG.NO: 13131049
Under the guidance of
DEEPA M S
Assistant Professor
ECE Department
November 2015
CERTIFICATE
This is to certify that the report entitled GRAPHENE INTERCONNECT FOR
NANOSCALE CIRCUITS submitted by SHILPA SUSAN BIJI (Reg No:
13131049) in partial fulfillment with the requirements for the award of the Degree
of Bachelor of Technology in Electronics and Communication Engineering of
Cochin University of Science and Technology is a bonafide report of the seminar
presented by her under our supervision.
DEEPA M S
SHANAVAZ K. T
Co-ordinator
ECE Department
Place: Kallooppara
Date:
ECE Department
ACKNOWLEDGEMENT
I take this opportunity to remember and acknowledge the cooperation, goodwill and
support both moral and technical extended by several individuals out of which this technical
seminar has involved. I shall always cherish my association with them.
I am greatly thankful to Dr. Jacob Thomas V, Principal of our college for extending his
help. I shall forever cherish my association with him for his encouragement, perennial
approachability, absolute freedom of thought and action.
I am greatly thankful to Mr. Shanavaz K. T, Head of the Department, Department of
Electronics and Communication Engineering, for his enthusiastic assistance. I have immense
pleasure in expressing my thanks and deep sense of gratitude for his guidance and assistance
offered in an amiable and pleasant manner through my technical seminar.
I hereby take the opportunity to thank our staff members Mrs. Sobhiraj N, and
Mr. Ajesh M.A, Asst.Professor and our seminar coordinator Ms. Deepa M.S, Asst.Professor
Dept. Of Electronics and Communication, College of Engineering Kallooppara, for their valuable
guidance throughout the course of this seminar.
A lot of thanks to other faculty members of the department who gave there valuable
suggestions at different stages of my technical seminar.
I am very much thankful to our parents who helped me with at most friendliness and
warmth always. They kept my spirit flying high and persistently encouraged me to undertake and
complete this technical seminar.
ABSTRACT
The role of interconnect in an integrated circuit is to enable effective passing of clock
and other signals in addition to providing power to various parts of the circuit on a chip. The
advent of sub-quarter-micron IC technologies has forced dramatic changes in the design and
manufacturing methodologies for integrated circuits and systems. The paradigm shift for
interconnect which was once considered just parasitic but can now be a dominant factor for
integrated circuit performance provided the greatest impetus for change of existing
methodologies. Copper, which is presently used as the interconnect material. Cu interconnect
dimensions begin to come into the range of mean free path of electron typically 40nm. This
results in surface and grain boundary scattering. Owing to these scattering phenomena
resistivity, of Cu begins to increase. This limitation of copper interconnects is driving research
for alternative interconnect materials and technologies for next-generation ICs. Nanotubes,
Graphene, and Nanowires and Carbon Nano Tubes are some of the new materials suggested as
an alternate to overcome these problems. Here in this paper we have analyzed the various
properties of graphene to use as an interconnect. Graphene has been attracting wide attention
owing to its superb electronic, thermal and mechanical properties.
Key words - Interconnect, graphene nanoribbon, graphene, carbon nanotube, gate oxide,
IC scaling.
CONTENTS
TITLE
CHAPTER
NO.
1.
PAGE
NO.
CONTENTS
LIST OF FIGURES
iv
INTRODUCTION
4
5
2.
INTERCONNECTS
2.3.2. ELECTROMIGRATION
10
10
3.
11
11
12
13
3.2. GRAPHENE
14
14
3.2.2. STRUCTURE
15
16
4.
17
19
21
22
22
22
23
23
ii
24
24
24
25
25
25
CONCLUSIONS
26
REFERENCES
27
iii
LIST OF FIGURES
FIG NO:
NAME
PAGE NO:
1.1
2.1
2.2(a)
ITRS Roadmap of Cu
10
3.1
13
3.2
16
3.3
Types of GNR
19
3.4
19
3.5
21
4.1
22
4.2
23
4.3
23
4.4
24
4.5
24
4.6
25
4.7
25
iv
CHAPTER 1
INTRODUCTION
Over the past few decades, the increasing progress in most technological areas from
biomedicine to strategic deployment to meteorological forecasting has been largely benefitting
from continuous and massive advances achieved in the field of computational technologies. With
the need for larger quantities of data processing at faster pace within smaller volumes, the
microelectronics industry has so far been steadily downsizing its basic active and passive building
blocks. Those components are currently capable of operating at higher clock-speeds, delivering
higher number of computations per second and, at the same time they occupy less physical space
and consume less power. Nevertheless, the rapid progress towards gigascale miniaturization of
those components faces a number of difficult challenges in terms of materials, architectures,
fabrication and integration of nanoscale active and passive elements with expected performance
in terms of reliability, speed, compatibility, and power consumption. In this scenario, a
fundamental issue of considerable difficulty is the development of the next generation
interconnects for microprocessor units (MPUs). Interconnects are wiring systems which distribute
clock and other signals and provide power and ground, to and among the various circuits and
systems functioning on a chip. As the various active and passive elements of the MPU reduce in
dimension below 100 nm, also the corresponding interconnects will consistently follow. Existing
interconnect technologies involving Cu/low-k lines and theirs evolutionary downsizing for sub100 nm size interconnects face a number of important challenges. As the lateral dimension of
interconnects approaches the mean free path of copper (~40 nm at room temperature ), the impact
of grain boundary scattering, surface scattering, and the presence of a high-resistivity material as
a diffusive barrier layer causes a rapid increase in the overall resistivity.
As integrated circuit feature sizes continue to scale, active device counts are reaching
hundreds of millions. The amount of interconnect among the devices tends to grow super
linearly with the transistor counts, and the chip area is often limited by the physical interconnect
area. The semiconductor industry is confronting an acute problem in the interconnect area as
IC feature sizes continually scale below 32 nm. When the cross sectional dimension of copper
wires approach their mean free path (about 40 nm at room temperature), they suffer significant
size effects because of increasing surface scattering, grain boundary scattering, and the
College of Engineering Kallooppara
presence of a highly resistive diffusion barrier layer, resulting in a sharp rise in copper
resistivity. According to the 2011 International Technology Roadmap for Semiconductors,
coppers resistivity could be more than three times higher than its bulk value at the 22nm
technology node. This steep rise in resistivity will adversely impact both performance and
reliability in terms of circuit delay, chip temperature, and current carrying capacity. This
limitation of copper interconnects is driving research for alternative interconnect materials and
technologies for next generation ICs. Nanotube, Graphene, and Nanowires are some of the
materials suggested as an alternate to overcome these problems. In this paper graphene is
considered as interconnect material. Graphene has been attracting wide attention owing to its
superb electronic, thermal and mechanical properties. With shrinking dimensions of copper
(Cu) interconnects, their resistivity and reliability have become important issues for nanoscale
circuits. Actually, the main requirement in nanoscale interconnects is the reduction in delay.
The delay is a function of interconnect resistance and capacitance. Carbon-based nanomaterials
are a good candidate for new interconnect materials, because of their lower resistivity and
intrinsically higher reliability, i.e. Electro-Migration (EM) tolerance, compared with a
conventional Cu interconnects. GNRs with smooth edges can have smaller resistances
compared with Cu wires. There have been several models developed to describe the resistance
in GNR interconnects. The crosstalk in GNR interconnects is also an important issue which
should be minimum. So, to implement graphene as a mainstream material, the challenges posed
by this material need to be tackled.
1.1.
MOOREs LAW
"Moore's law" is the observation that the number of transistors in a dense integrated
circuit has doubled approximately every two years. The observation is named after Gordon E.
Moore, the co-founder of Intel and Fairchild Semiconductor, whose 1965 paper described
a doubling every year in the number of components per integrated circuit, and projected this rate
of growth would continue for at least another decade. In 1975, looking forward to the next
decade, he revised the forecast to doubling every two years.
Digital electronics have contributed to world economic growth in the late twentieth and
early twenty-first centuries. Moore's law describes a driving force of technological and social
change, productivity, and economic growth The period is often quoted as 18 months because of
Intel executive David House, who predicted that chip performance would double every 18 months
(being a combination of the effect of more transistors and their being faster).
"Moore's law" should be considered an observation or projection and not
a physical or natural law. Although the rate held steady during the last four decades, the rate was
faster during the first decade. Doubts about the validity of extrapolating the historical growth rate
into the indefinite future have been expressed. For example, the 2010 update to the International
Technology Roadmap for Semiconductors predicted that growth would slow around 2013, and
Gordon Moore in 2015 foresaw that the rate of progress would reach saturation: "I see Moores
law dying here in the next decade or so."
Intel confirmed in 2015 that the pace of advancement has slowed, starting at the 22
nm node around 2012 and continuing at 14 nm. Brian Krzanich, CEO of Intel, announced that
Our cadence today is closer to two and a half years than two. This is scheduled to hold through
the 10 nm node in late 2017. He cited Moore's 1975 revision as a precedent for the current
deceleration, which results from technical challenges and is a natural part of the history of
Moore's law.
1.2.
NANOSCALE CIRCUITS
Nanocircuits are electrical circuits operating on the nanometer scale. This is well into
the quantum realm, where quantum mechanical effects become very important. One nanometer is
equal to 109 meters or a row of 10 hydrogen atoms. With such progressively smaller circuits,
more can be fitted on a computer chip. This allows faster and more complex functions using less
power. Even though, the nanocircuit of a processor that is used nowadays will be billion times
smaller, the performance will be moreover the same with perhaps greater efficiency. Thus
hundreds of nanocircuits can be added together to form a high performance and highly efficient
processor.
research
and
development
in
this
direction
resulting
in
some
basic
opening the door to flexible electronic applications such as electronic paper, bendable flat panel
displays, and wide area solar cell
CHAPTER 2
INTERCONNECTS
Interconnects are those feeding lines used in devices for interconnect its components. It
connects renewable energy systems to the power grid. Nano interconnects are considered as
building blocks for next generation of electronics, photonics, sensors and energy applications.
Integrated circuits have their own unique form of wiring to connect together the microminiature components they contain. This consists of extremely thin conducting metal, etched
to form a network of separate strips that create the electrical connections that are needed, called
interconnections.
Local interconnect
Local interconnects consist of very thin lines, connecting gates, and transistors within a
functional block. They usually span only a few gates and occupy first and, sometimes, second
metal layers. Local
interconnect is used for short distance communication delay of less than a clock cycle. Local
interconnects are the first, or lowest, level of interconnects. They usually connect gates, sources
and drains in MOS technology, and emitters, bases, and collectors in bipolar technology.
Semi Global Interconnect
Semi global interconnects are wider and taller than local interconnects in order to provide
lower resistance; intermediate wiring provides clock and signal distribution within a functional
block with typical lengths up to 3 to 4 mm. Semi-Global interconnect is used to connect devices
within a block.
Global Interconnect
Global interconnects provide clock and signal distribution between the functional blocks
and deliver power/ground to all functions. Global interconnects occupy the top one or two
layers, and they are longer than 4 mmas long as half the chip perimeter. It is critical that lowresistivity global interconnects be used as the bias voltage decreases and the total current
consumption of the chip increases Global interconnect which is used for long distance
communication distribute data, clock, power supply and ground across the chip, delay spanning
multiple clock cycles. They often travel over large distances, between different devices and
different parts of the circuit, and therefore are always low resistant metals
interconnections have been sought even in earlier technology generations, for example the
transition from aluminium to copper some years back. The interconnect material is a prime factor
for IC scaling. To improve the scaling efficiency suitable interconnect material is to be select.
Graphene nanoribbons and carbon nano tubes are the advanced technology which offers the best
deals to scale an IC now days
ohmic resistance when making a contact directly to silicon or aluminium layers, did not require
barrier metals on the sides of the metal lines to isolate aluminium from the surrounding silicon
oxide insulators. Figure () shows how the resistivity of copper significantly and rapidly increases
above its bulk value as interconnect lateral dimension shrinks below 100 nm , following which
major degradation of reliability, signal transfer properties and thermal management issues start to
become important. In addition, larger current densities for increasingly small interconnect lines
will lead to an enhanced electro-migration failure. Tightly packed conducting material immersed
in a dielectric environment will further introduce significantly larger parasitic capacitance,
enhancing the delay of the signal propagation and limiting the overall operational bandwidth. This
scenario clearly suggests that any length below 22 nm, which represents the current
microelectronics community standard, copper will reveal to be inadequate for interconnect
applications. Hence, a revolutionary new high-conducting material with higher failure current
density and comparable or better performance metrics (such as specific capacitance and RC delay)
is indeed in need for future copper replacement. Figure 1b represents the cross-sectional schematic
of a typical Integrated Circuit (IC), reproduced from the International Technology Roadmap for
Semiconductors (ITRS) map from 2009. In a typical IC, interconnect structures are scaled into
local, intermediate, and global wiring levels based on optimization of delay, power, and bandwidth
etc.
Figure 2.2 (a) Resistivity of copper as function of the interconnect linewidth; (b) Typical
Cross-section of hierarchical scaling (microprocessor unit (MPU) device) showing different
interconnect scaling levels
College of Engineering Kallooppara
2.3.2 Electromigration
Resistance to electromigration, the process by which a metal conductor changes shape
under the influence of an electric current flowing through it and which eventually leads to the
breaking of the conductor, is significantly better with copper than with aluminium. This
improvement in electromigration resistance allows higher currents to flow through a given size
copper conductor compared to aluminium. The combination of a modest increase in conductivity
along with this improvement in electromigration resistance was to prove highly attractive. The
overall benefits derived from these performance improvements were ultimately enough to drive
full scale investment in copper based technologies and fabrication methods for high performance
semiconductor devices, and copper based processes continue to be the state of the art for the
semiconductor industry today.
10
CHAPTER 3
GRAPHENE NANO RIBBON (GNR)
3.1. CARBON NANOTUBES (CNTS)
Carbon nanotubes (CNTs) are allotropes of carbon with a cylindrical nanostructure.
Nanotubes
have
132,000,000:1
cylindrical
been
constructed
significantly
carbon
molecules
larger
have
with
length-to-diameter
than
for
unusual
any
ratio
other
properties,
of
up
material.
which
are
to
These
valuable
for nanotechnology, electronics, optics and other fields of materials science and technology. In
particular,
owing
to
their
extraordinary
thermal
conductivity
and
mechanical
and electrical properties, carbon nanotubes find applications as additives to various structural
materials. For instance, nanotubes form a tiny portion of the material(s) in some (primarily carbon
fiber) baseball bats, golf clubs, car parts or damascus steel.
Nanotubes are members of the fullerene structural family. Their name is derived from their
long, hollow structure with the walls formed by one-atom-thick sheets of carbon, called graphene.
These sheets are rolled at specific and discrete ("chiral") angles, and the combination of the rolling
angle and radius decides the nanotube properties; for example, whether the individual nanotube
shell is a metal or semiconductor. Nanotubes are categorized as single-walled nanotubes (SWNTs)
and multi-walled nanotubes (MWNTs). Individual nanotubes naturally align themselves into
"ropes" held together by van der Waals forces, more specifically, pi-stacking.
Applied quantum chemistry, specifically, orbital hybridization best describes chemical
bonding in nanotubes. The chemical bonding of nanotubes is composed entirely of sp2 bonds,
similar to those of graphite. These bonds, which are stronger than the sp3 bonds found
in alkanes and diamond, provide nanotubes with their unique strength.
11
Single-wall nanotubes (SWNT) are tubes of graphite that are normally capped at the
ends. They have a single cylindrical wall. The structure of a SWNT can be visualized
as a layer of graphite, a single atom thick, called graphene, which is rolled into a
seamless cylinder.
Most SWNT typically have a diameter of close to 1 nm. The tube length, however, can
be many thousands of times longer.
SWNT are more pliable yet harder to make than MWNT. They can be twisted,
flattened, and bent into small circles or around sharp bends without breaking.
SWNT have unique electronic and mechanical properties which can be used in
numerous applications, such as field-emission displays, nanocomposite materials,
nanosensors, and logic elements. These materials are on the leading-edge of electronic
fabrication, and are expected to play a major role in the next generation of miniaturized
electronics.
The diameters of MWNT are typically in the range of 5 nm to 50 nm. The interlayer
distance in MWNT is close to the distance between graphene layers in graphite.
MWNT are easier to produce in high volume quantities than SWNT. However, the
structure of MWNT is less well understood because of its greater complexity and
variety. Regions of structural imperfection may diminish its desirable material
properties.
12
13
3.2. GRAPHENE
Graphene (/rf.in/)[1][2] is an allotrope of carbon in the form of a two-dimensional,
atomic scale, hexagonal lattice in which one atom forms each vertex. It is the basic structural
element of other allotropes, including graphite, charcoal, carbon nanotubes and fullerenes. It can
also be considered as an indefinitely large aromatic molecule, the limiting case of the family of
flat polycyclic aromatic hydrocarbons.
3.2.1. Properties of Graphene
Graphene has many extraordinary properties. It is about 200 times stronger than steel by
weight, conducts heat and electricity with great efficiency and is nearly transparent. Researchers
have identified the bipolar transistor effect, ballistic transport of charges and large quantum
oscillations in the material. Scientists have theorized about graphene for decades. It is quite likely
College of Engineering Kallooppara
14
that graphene was unwittingly produced in small quantities for centuries through the use of pencils
and other similar applications of graphite, but it was first measurably produced and isolated in the
lab in 2003. Research was informed by existing theoretical descriptions of its composition,
structure and properties. High-quality graphene proved to be surprisingly easy to isolate, making
more research possible. Andre Geim and Konstantin Novoselov at the University of Manchester
won the Nobel Prize in Physics in 2010 "for ground-breaking experiments regarding the twodimensional material graphene."
The global market for graphene is reported to have reached $9 million by 2014 with most
sales in the semiconductor, electronics, battery energy and composites industries. The problem
that prevented graphene from initially being available for developmental research in commercial
uses was that the creation of high quality graphene was a very expensive and complex process (of
chemical vapour disposition) that involved the use of toxic chemicals to grow graphene as a
monolayer by exposing Platinum, Nickel or Titanium Carbide to ethylene or benzene at high
temperatures. Also, it was previously impossible to grow graphene layers on a large scale using
crystalline epitaxy on anything other than a metallic substrate. This severely limited its use in
electronics as it was difficult, at that time, to separate graphene layers from its metallic substrate
without damaging the graphene
3.2.2. Structure
Graphene is a crystalline allotrope of carbon with 2-dimensional properties. Its carbon
atoms are densely packed in a regular atomic-scale chicken wire (hexagonal) pattern. Each atom
has four bonds, one bond with each of its three neighbours and one -bond that is oriented out
of plane. The atoms are about 1.42 apart. Graphene's hexagonal lattice can be regarded as two
interleaving triangular lattices. This perspective was successfully used to calculate the band
structure for a single graphite layer using a tight-binding approximation. Graphene's stability is
due to its tightly packed carbon atoms and a sp2 orbital hybridization a combination of orbitals
s, px and py that constitute the -bond. The final pz electron makes up the -bond. The -bonds
hybridize together to form the -band and -bands. These bands are responsible for most of
graphene's notable electronic properties, via the half-filled band that permits free-moving
electrons. Graphene sheets in solid form usually show evidence in diffraction for graphite's (002)
layering. This is true of some single-walled nanostructures. Suspended graphene also showed
15
"rippling" of the flat sheet, with amplitude of about one nanometer. These ripples may be intrinsic
to the material as a result of the instability of two-dimensional crystals, or may originate from the
ubiquitous dirt seen in all TEM images of graphene. Atomic resolution real-space images of
isolated,
single-
SiO2
substrates
are
available
via
scanning
tunnelling
microscopy. Photoresist residue, which must be removed to obtain atomic-resolution images, may
be the "adsorbates" observed in TEM images, and may explain the observed rippling. Rippling on
SiO2 is caused by conformation of graphene to the underlying SiO2 and is not intrinsic.
16
17
(zero bandgap), in the case of zig-zag edge ribbons (ZGNR), to the Semiconducting for armchair
ribbons (AGNR), where the engineered energy gap varies with the ribbon width and length. The
origin of this energy gap in the band-structure of nanoribbons is attributed to edge roughness. In
addition, first principle calculations suggest that the carbon-carbon interatomic distance in the
vicinity of the edges armchair GNRs is slightly smaller (~3.5%) than the corresponding equivalent
distance in two-dimensional graphene (1.42 ), which can also induce the opening of an energy
gap. This can also be favoured if the spin component of zigzag GNRs is also considered. It has
been recently shown that multilayer armchair GNRs are characterized by different bandgaps,
depending on their width as a result of the interlayer interaction between adjacent layer which
determines the magnetic polarization and band structures.
Let us now discuss the so-called graphene nanoribbons (GNRs), i.e., ribbons obtained by
cutting a graphene layer, characterized by a high aspect-ratio, namely a transverse width, w, much
smaller than the longitudinal ribbon length. Figure 3 shows the two basic shapes for GNRs, namely
nanoribbons with armchair edges and nanoribbons with zigzag edges. These edges have a 30
difference in their orientation within the graphene sheet. We assume that all dangling bonds at
graphene edges are terminated by hydrogen atoms and, thus, do not contribute to the electronic
states near the Fermi level. In the following, we will assume the Fermi energy to be zero. However,
this level may move to values such as 0.20.4 eV, considering the interactions at the
GNR/substrate interface. The width, w, of a graphene nanoribbon is directly related to the integer,
N, indicating the number of dimers (two carbon sites) for the armchair nanoribbons and the number
of zigzag lines for the zigzag nanoribbons. For armchair GNRs, the unit cell has a length T
and a width w = Na/2, whereas for zigzag ones, it is T = a and w
3a
and, thus, the GNR width, w, the energy spectrum of the -electrons can be obtained by slicing
the band structure of graphene. For N =3q 1 (q = 1,2,), there exists a sub-band, , for which
the direct bandgap is zero; hence, the GNR behaves as a metal. For other values, the armchair
GNRs is semiconducting. However, the direct bandgap decreases with w increasing and
approaches zero in the limit of very large w, consistent with the behaviour of the graphene layer.
Therefore, the value of the width (hence, the number, N) determines whether the nanoribbon is
metallic or semiconducting.
18
19
While CNTs are difficult to grow in horizontal directions, GNRs are believed to be more
fabricable compared to CNTs due to their patternability using lithography. In principle, graphene
can be patterned to produce metallic or semiconducting GNRs on demand. Various methods for
fabricating GNRs are being pursued, but difficulties also exist in those methods. Carbon films
have been demonstrated in DRAM trench capacitors using CVD method but the grown films are
not single-crystal graphene with high electrical conductivity. Although the thermal decomposition
of single-crystal SiC makes thin graphene films this approach requires single crystal substrate and
high temperature, which is not suitable for interconnects due to the relatively low backend thermal
budget (400 C) in IC fabrication technologies. Graphene can also be mechanically exfoliated
from graphite and deposited onto an insulating substrate but this approach is uncontrollable for
large-scale fabrication. In graphene is segregated by dissolving carbon in a Ni substrate at high
temperatures, covering with a silicone film, and then transferring to a desired substrate. The Ni
substrate can be subsequently removed to allow GNR wire and contact formation through
patterning. Similarly, graphene can be deposited on copper foils (which can be removed later) and
transferred to insulating substrates.
While these approaches are more suitable for interconnect applications than the previous
three approaches, they still require further investigation. To improve the conductivity of multilayer
GNRs, intercalation doping has been suggested in. The intercalation doping has been known for a
long time in bulk graphite .Generally, graphite can be intercalation doped by exposure to dopant
vapour. Since multilayer GNRs can be considered as patterned bulk graphite, it is implied that the
intercalation doping can be applied to multilayer GNRs. Most recently, Fujitsu has demonstrated
the possibility of building all carbon interconnect structures by combining CNTs and GNRs
using CVD method, where at first, the horizontal GNR layers are grown on a Co film, followed
by vertical CNT growth after the Co film has been desegregated to form nanoparticles during the
CVD process. However, the contacts between CNT bundle and GNR layers in this structure need
more investigation and engineering.
20
Fig shows a schematic representation of a typical RLC model for an MLGNR interconnect
made of Nlayer single GNR layers of the same lengths l and widths W. In this figure, RC, RQ,
and RS represent the equivalent resistances introduced by the imperfect contacts, the quantum
effect, and the carriers scatterings, respectively. One can approximate the quantum contact
resistance as RQ h/2eN, where in h, e, and N are the Planks constant, electron charge, and
number of conducting channels in each GNR. When the length of each GNR is greater than its
carriers mean free path (), the equivalent distributed ohmic resistance (per unit length)
introduced by carrier scatterings with defects, substrate-induced disorders, and phonons can be
written as RS RQ/ [6]. Also shown in Fig, CE W/d and CQ 2e2 /hvF are the per unit length
values of the equivalent capacitances induced by the electrostatic and quantum effects,
respectively, in which and F are the dielectric permittivity and the Fermi velocity in graphite,
respectively. Note that, in order to approximate CE, MLGNR is assumed to be a bundle of ribbons
displaced from a ground plane by the same distance d. Since the separation between any two
subsequent layers is much smaller than d, the effect of the electrostatic capacitances between any
two subsequent GNR layers is negligible.
21
CHAPTER 4
PERFORMANCE ANALYSIS OF
GNR INTERCONNECT
In this paper the GNR important properties such as geometry, ambient, inter layer spacing
and few more material properties have been studied.
22
23
Inter layer spacing as the name defines is the spacing between two consecutive layers
of graphene. Inter layer spacing of graphene interconnect is subjected to change at a range of
GNR resistance increases. Maximum inter layer spacing applicable for nano interconnect is 4A.
It shows that, the resistance of interconnect can be reduced by reducing its inter layer spacing.
24
The Fig.shows when pitch of oxide increases, there are no changes is observed for all
properties of graphene interconnect especially resistivity.
25
CHAPTER 5
CONCLUSIONS
Copper, which is presently used as the interconnect material. Cu interconnect dimensions
begin to come into the range of mean free path of electron typically 40nm. This results in surface
and grain boundary scattering. Owing to these scattering phenomena resistivity, of Cu begins to
increase. This limitation of copper interconnects is driving research for alternative interconnect
materials and technologies for next-generation ICs. Nanotubes, Graphene, and Nanowires and
Carbon Nano Tubes are some of the new materials suggested as an alternate to overcome these
problems From the analysis of GNR it can be concluded that the resistivity of graphene nano
ribbon decreases with increase in its orientation defect, width and Fermi level but it seems
resistance increases with increase in the inter layer spacing and length of the GNR interconnect.
It is find that the number of conduction channels increases with increase in Fermi level. It also
find that when the inter layer spacing increases, it results in decreasing the no. of GNR layers and
no. of conduction channels.
26
REFERENCES
1. P.S. Raja, R. Joseph Daniel, Roopak Mathew Thomas Graphene Interconnect for nano
scale circuits Dept. of E & I Engineering, Annamalai University, Annamalainagar, 608
002, Tamilnadu, India.
2. Mehdi Moussavi Advanced Interconnect schemes towards O.1um 1999 IEEE.
3. ChuanXu, Hong Li and Kaustav Banerjee, Graphene Nano-Ribbon Interconnects: A
Genuine Contender or a Delusive Dream? Department of Electrical and Computer
Engineering, University of California, Santa Barbara, CA 93106, USA.
4. Sandip Bhattacharya, Subhajit Das, Debaprasad Das, Analysis of Stability in Carbon
Nanotube and Graphene Nanoribbon Interconnects, International Journal of Soft
Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-2, Issue-6, January 2013.
5. Kureshi Abdul Kadir and Mohd.Hasan, Analysis of CNT Bundle and its Comparison with
Copper for FPGAs Interconnects, World Academy of Science, Engineering and
Technology 33, 2009.
6. PawanKapur, James P. McVittie, and Krishna C. Saraswat, Technology and Reliability
Constrained Future Copper interconnects Part I: Resistance Modeling,IEEE Transactions
on electron devices, vol. 49, No. 4, April 2002.
7. Hong Li, Wen-Yan Yin, Kaustav Banerjee and Jun-Fa Mao, Circuit Modeling and
Performance Analysis of Multi- Walled Carbon Nanotube Interconnects, IEEE
transactions on electron devices, vol. 55, No. 6, June 2008.
8. P.S.Raja, R.joseph Daniel, Bino.N, Performance analysis of Carbon Nano Tubes, IOSR
Journal of Engineering (IOSRJEN), Volume 2, Issue 8, PP 54-58, (August 2012).
9. P.S. Raja, R. Joseph Daniel, Bino. N, Analysis of Various Parameters of Mixed Carbon
Nanotube Bundle for Interconnect Applications, International Journal of Engineering
Research & Technology (IJERT), Vol. 1 Issue 6, August 2012.
10. www.nanohub.org
27