Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
1. General description
The 74HC163; 74HCT163 is a synchronous presettable binary counter with an internal
look-head carry. Synchronous operation is provided by having all flip-flops clocked
simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the
counters may be preset to a HIGH or LOW. A LOW at the parallel enable input (PE)
disables the counting action. It causes the data at the data inputs (D0 to D3) to be loaded
into the counter on the positive-going edge of the clock. Preset takes place regardless of
the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR)
sets Q0 to Q3 LOW after the next positive-going transition on the clock input (CP). This
action occurs regardless of the levels at input pins PE, CET and CEP. This synchronous
reset feature enables the designer to modify the maximum count with only one external
NAND gate. The look-ahead carry simplifies serial cascading of the counters. Both CEP
and CET must be HIGH to count. The CET input is fed forward to enable the terminal
count output (TC). The TC output thus enabled will produce a HIGH output pulse of a
duration approximately equal to a HIGH output of Q0. This pulse can be used to enable
the next cascaded stage. Inputs include clamp diodes. This enables the use of current
limiting resistors to interface inputs to voltages in excess of VCC.
The CP to TC propagation delay and CEP to CP set-up time determine the maximum
clock frequency for the cascaded counters according to the following formula:
1
f max = ---------------------------------------------------------------------------------------t P max CPtoTC + t SU CEPtoCP
74HC163; 74HCT163
NXP Semiconductors
3. Ordering information
Table 1.
Ordering information
Type number
74HC163N
Package
Temperature
range
Name
Description
Version
40 C to +125 C
DIP16
SOT38-4
40 C to +125 C
SO16
SOT109-1
40 C to +125 C
SSOP16
SOT338-1
40 C to +125 C
TSSOP16
SOT403-1
74HCT163N
74HC163D
74HCT163D
74HC163DB
74HCT163DB
74HC163PW
74HCT163PW
4. Functional diagram
'
'
'
'
'
'
'
3(
3$5$//(/
/2$'&,5&8,75<
05
3( '
&(3
&(7
&(3
&3
05
'
,1+
&3
&3
4
Fig 1.
7&
%,1$5<
&2817(5
4
4
&(7
7&
4 4 4 4
4
DDD
Functional diagram
5
DDD
Fig 2.
Logic symbol
&75
0
*
*
&
'
&7
DDD
Fig 3.
74HC_HCT163
2 of 24
'
NXP Semiconductors
74HC_HCT163
'
'
&(7
&(3
05
'
'
&3
))
4
'
&3
4
'
&3
4
3 of 24
4
))
4
&3
4
4
))
4
4
4
4
7&
DDD
Fig 4.
Logic diagram
74HC163; 74HCT163
&3
))
4
3(
74HC163; 74HCT163
NXP Semiconductors
5. Pinning information
5.1 Pinning
+&
+&7
+&
+&7
05
9&&
05
9&&
&3
7&
&3
7&
'
'
'
'
'
4
'
4
'
4
'
4
&(3
&(7
*1'
3(
'
4
'
4
&(3
&(7
*1'
DDD
Fig 5.
3(
+&
+&7
05
9&&
&3
7&
'
'
'
4
'
4
'
4
&(3
&(7
*1'
Fig 6.
3(
DDD
DDD
Fig 7.
Pin description
Symbol
Pin
Description
MR
CP
3, 4, 5, 6
data input
CEP
GND
ground (0 V)
PE
CET
10
flip-flop output
TC
15
VCC
16
supply voltage
74HC_HCT163
4 of 24
74HC163; 74HCT163
NXP Semiconductors
6. Functional description
Table 3.
Function table[1]
Operating mode
Inputs
Outputs
MR
CP
CEP
CET
PE
Dn
Qn
TC
Reset (clear)
Parallel load
Count
count
qn
qn
[1]
The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH);
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
q = lower case letters indicate the state of the referenced output one set-up time prior to the
LOW-to-HIGH CP transition;
X = dont care;
= LOW-to-HIGH clock transition.
DDD
Fig 8.
State diagram
74HC_HCT163
5 of 24
74HC163; 74HCT163
NXP Semiconductors
05
3(
'
'
'
'
&3
&(3
&(7
4
4
4
4
7&
UHVHW SUHVHW
FRXQW
LQKLELW
DDD
Sequence
reset outputs to zero; preset to binary 12; count to 13, 14, 15, zero, one and two; inhibit.
Fig 9.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
0.5
+7.0
IIK
20
mA
IOK
20
mA
IO
output current
25
mA
ICC
supply current
50
mA
IGND
ground current
50
mA
Tstg
storage temperature
total power dissipation
Ptot
[1]
65
+150
DIP16 package
[1]
750
mW
SO16 package
[1]
500
mW
(T)SSOP16 package
[1]
500
mW
For DIP16 packages: above 70 C the value of Ptot derates linearly at 12 mW/K.
For SO16 packages: above 70 C the value of Ptot derates linearly at 8 mW/K.
For (T)SSOP16 packages: above 60 C the value of Ptot derates linearly at 5.5 mW/K.
74HC_HCT163
6 of 24
74HC163; 74HCT163
NXP Semiconductors
Conditions
74HC163
Min
74HCT163
Typ
Max
Min
Unit
Typ
Max
VCC
supply voltage
2.0
5.0
6.0
4.5
5.0
5.5
VI
input voltage
VCC
VCC
VO
output voltage
VCC
VCC
Tamb
ambient temperature
40
+25
+125
40
+25
+125
t/V
VCC = 2.0 V
625
ns/V
VCC = 4.5 V
1.67
139
1.67
139
ns/V
VCC = 6.0 V
83
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
Min
Typ
VCC = 2.0 V
1.5
VCC = 4.5 V
3.15
VCC = 6.0 V
4.2
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Min
Max
Min
Max
1.2
1.5
1.5
2.4
3.15
3.15
3.2
4.2
4.2
0.8
0.5
0.5
0.5
2.1
1.35
1.35
1.35
2.8
1.8
1.8
1.8
HIGH-level
VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
1.9
2.0
1.9
1.9
IO = 20 A; VCC = 4.5 V
4.4
4.5
4.4
4.4
IO = 20 A; VCC = 6.0 V
5.9
6.0
5.9
5.9
3.98
4.32
3.84
3.7
5.48
5.81
5.34
5.2
LOW-level
VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
0.1
0.1
0.1
IO = 20 A; VCC = 4.5 V
0.1
0.1
0.1
IO = 20 A; VCC = 6.0 V
0.1
0.1
0.1
0.15
0.26
0.33
0.4
0.16
0.26
0.33
0.4
0.1
1.0
1.0
8.0
80.0
160.0
74HC163
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
II
input leakage
current
ICC
74HC_HCT163
7 of 24
74HC163; 74HCT163
NXP Semiconductors
Table 6.
Static characteristics continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
Min
CI
input
capacitance
Typ
Min
Max
Min
Max
3.5
pF
74HCT163
VIH
HIGH-level
input voltage
2.0
1.6
2.0
2.0
VIL
LOW-level
input voltage
1.2
0.8
0.8
0.8
VOH
HIGH-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = 20 A
4.4
4.5
4.4
4.4
3.98
4.32
3.84
3.7
0.1
0.1
0.1
0.15
0.26
0.33
0.4
0.1
1.0
1.0
8.0
80.0
160.0
pin MR
95
342
427.5
465.5
IO = 4.0 mA
VOL
LOW-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = 20 A
IO = 4.0 mA
II
input leakage
current
ICC
ICC
additional
per input pin; VI = VCC 2.1 V;
supply current other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO = 0 A
CI
input
capacitance
74HC_HCT163
pin CP
110
396
495
539
25
90
112.5
122.5
pin CET
75
270
337.5
367.5
pin PE
30
108
135
147
3.5
pF
8 of 24
74HC163; 74HCT163
NXP Semiconductors
25 C
Conditions
Min
Typ
Max
Min
Max
Min
Max
55
185
230
280
ns
20
37
46
56
ns
74HC163
tpd
[1]
VCC = 5.0 V; CL = 15 pF
17
ns
VCC = 6.0 V
16
31
39
48
ns
VCC = 2.0 V
69
215
270
320
ns
VCC = 4.5 V
25
43
54
65
ns
VCC = 5.0 V; CL = 15 pF
21
ns
VCC = 6.0 V
20
37
46
55
ns
36
120
150
180
ns
VCC = 4.5 V
13
24
30
36
ns
VCC = 5.0 V; CL = 15 pF
11
ns
10
20
26
31
ns
VCC = 2.0 V
19
75
95
110
ns
VCC = 4.5 V
15
19
22
ns
VCC = 6.0 V
13
16
19
ns
VCC = 2.0 V
80
17
100
120
ns
VCC = 4.5 V
16
20
24
ns
VCC = 6.0 V
14
17
20
ns
VCC = 6.0 V
tt
tW
transition
time
pulse width
74HC_HCT163
[2]
9 of 24
74HC163; 74HCT163
NXP Semiconductors
Table 7.
Dynamic characteristics continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 15.
Symbol Parameter
tsu
set-up time
25 C
Conditions
Min
Typ
Max
Min
Max
Min
Max
VCC = 2.0 V
80
17
100
120
ns
VCC = 4.5 V
16
20
24
ns
VCC = 6.0 V
14
17
20
ns
VCC = 2.0 V
80
22
100
120
ns
VCC = 4.5 V
16
20
24
ns
VCC = 6.0 V
14
17
20
ns
VCC = 2.0 V
175
58
220
265
ns
VCC = 4.5 V
35
21
44
53
ns
VCC = 6.0 V
30
17
37
45
ns
th
fmax
hold time
maximum
frequency
14
ns
VCC = 4.5 V
ns
VCC = 6.0 V
ns
VCC = 2.0 V
15
MHz
VCC = 4.5 V
27
46
22
18
MHz
51
MHz
32
55
26
21
MHz
33
pF
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
CPD
power
VI = GND to VCC; VCC = 5 V;
dissipation fi = 1 MHz
capacitance
74HC_HCT163
[3]
10 of 24
74HC163; 74HCT163
NXP Semiconductors
Table 7.
Dynamic characteristics continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 15.
Symbol Parameter
25 C
Conditions
Min
Typ
Max
Min
Max
Min
Max
23
39
49
59
ns
20
ns
VCC = 4.5 V
29
49
61
74
ns
VCC = 5.0 V; CL = 15 pF
25
ns
17
32
44
48
ns
14
ns
15
19
22
ns
20
25
30
ns
20
25
30
ns
20
11
25
30
ns
40
24
50
60
ns
ns
26
45
21
17
MHz
50
MHz
74HCT193
tpd
[1]
transition
time
pulse width
VCC = 4.5 V
VCC = 4.5 V
tsu
set-up time
[2]
th
hold time
fmax
maximum
frequency
74HC_HCT163
11 of 24
74HC163; 74HCT163
NXP Semiconductors
Table 7.
Dynamic characteristics continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 15.
Symbol Parameter
power
VI = GND to VCC 1.5 V;
dissipation VCC = 5 V; fi = 1 MHz
capacitance
CPD
[1]
25 C
Conditions
[3]
Min
Typ
Max
Min
Max
Min
Max
35
pF
[2]
[3]
11. Waveforms
IPD[
9,
&3LQSXW
90
*1'
W:
W3+/
92+
4Q7&
RXWSXW
W3/+
90
92/
W7+/
W7/+
DDD
Fig 10. The clock (CP) to outputs (Qn, TC) propagation delays, pulse width, output transition times and maximum
frequency
74HC_HCT163
12 of 24
74HC163; 74HCT163
NXP Semiconductors
9,
&(7LQSXW
90
*1'
W3/+
W3+/
92+
7&RXWSXW
90
92/
W7/+
W7+/
DDD
Fig 11. The count enable carry input (CET) to terminal count output (TC) propagation delays and output
transition times
9,
90
3(LQSXW
*1'
WVX
WVX
WK
WK
9,
90
&3LQSXW
*1'
WVX
WVX
WK
9,
WK
90
'QLQSXW
*1'
DDD
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8.
Fig 12. The data input (Dn) and parallel enable input (PE) set-up and hold times
74HC_HCT163
13 of 24
74HC163; 74HCT163
NXP Semiconductors
9,
90
05LQSXW
*1'
WVX
WVX
WK
9,
&3LQSXW
WK
90
*1'
DDD
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8.
Fig 13. The master reset (MR) set-up and hold times
9,
&(3&(7
LQSXW
90
*1'
9,
&3LQSXW
WVX
WVX
WK
WK
90
*1'
DDD
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8.
Fig 14. The count enable input (CEP) and count enable carry input (CET) set-up and hold times
Table 8.
Measurement points
Type
Input
Output
VM
VI
VM
74HC163
0.5 VCC
GND to VCC
0.5 VCC
74HCT163
1.3 V
GND to 3 V
1.3 V
74HC_HCT163
14 of 24
74HC163; 74HCT163
NXP Semiconductors
9,
W:
QHJDWLYH
SXOVH
90
9
9,
WI
WU
WU
WI
SRVLWLYH
SXOVH
9
90
90
90
W:
9&&
9&&
9,
92
5/
6
RSHQ
'87
&/
57
DDG
Test data
Type
Input
VI
tr, tf
CL
RL
tPHL, tPLH
74HC163
VCC
6 ns
15 pF, 50 pF
1 k
open
74HCT163
3V
6 ns
15 pF, 50 pF
1 k
open
74HC_HCT163
Load
S1 position
15 of 24
74HC163; 74HCT163
NXP Semiconductors
RWKHU
LQSXWV
4
4
RXWSXW
4
4
UHVHW
DDD
RWKHU
LQSXWV
4
4
4
RXWSXW
4
UHVHW
DDD
74HC_HCT163
16 of 24
74HC163; 74HCT163
NXP Semiconductors
627
0(
VHDWLQJSODQH
'
$
$
$
/
F
H
=
Z 0
E
E
H
E
0+
SLQLQGH[
(
PP
VFDOH
',0(16,216LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV
81,7
$
PD[
$
PLQ
$
PD[
E
E
E
F
'
(
H
H
/
0(
0+
Z
=
PD[
PP
LQFKHV
1RWH
3ODVWLFRUPHWDOSURWUXVLRQVRIPPLQFKPD[LPXPSHUVLGHDUHQRWLQFOXGHG
5()(5(1&(6
287/,1(
9(56,21
,(&
-('(&
627
-(,7$
(8523($1
352-(&7,21
,668('$7(
17 of 24
74HC163; 74HCT163
NXP Semiconductors
62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP
627
'
(
$
;
F
\
+(
Y 0 $
=
4
$
$
$
$
SLQLQGH[
/S
/
H
Z 0
ES
GHWDLO;
PP
VFDOH
',0(16,216LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV
81,7
$
PD[
$
$
$
ES
F
'
(
H
+(
/
/S
4
Y
Z
\
=
PP
LQFKHV
R
R
1RWH
3ODVWLFRUPHWDOSURWUXVLRQVRIPPLQFKPD[LPXPSHUVLGHDUHQRWLQFOXGHG
5()(5(1&(6
287/,1(
9(56,21
,(&
-('(&
627
(
06
-(,7$
(8523($1
352-(&7,21
,668('$7(
18 of 24
74HC163; 74HCT163
NXP Semiconductors
6623SODVWLFVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP
'
627
(
$
;
F
\
+(
Y 0 $
=
4
$
$
$
$
SLQLQGH[
/S
/
GHWDLO;
Z 0
ES
H
PP
VFDOH
',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV
81,7
$
PD[
$
$
$
ES
F
'
(
H
+(
/
/S
4
Y
Z
\
=
PP
R
R
1RWH
3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG
287/,1(
9(56,21
627
5()(5(1&(6
,(&
-('(&
-(,7$
(8523($1
352-(&7,21
,668('$7(
02
19 of 24
74HC163; 74HCT163
NXP Semiconductors
76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP
'
627
(
$
;
F
\
+(
Y 0 $
=
4
$
SLQLQGH[
$
$
$
/S
/
H
GHWDLO;
Z 0
ES
PP
VFDOH
',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV
81,7
$
PD[
$
$
$
ES
F
'
(
H
+(
/
/S
4
Y
Z
\
=
PP
R
R
1RWHV
3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG
3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG
287/,1(
9(56,21
627
5()(5(1&(6
,(&
-('(&
-(,7$
(8523($1
352-(&7,21
,668('$7(
02
20 of 24
74HC163; 74HCT163
NXP Semiconductors
14. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CMOS
DUT
ESD
ElectroStatic Discharge
HBM
LSTTL
MM
Machine Model
TTL
Transistor-Transistor Logic
Revision history
Document ID
Release date
Change notice
Supersedes
74HC_HCT163 v.3
20140602
74HC_HCT163_CNV v.2
Modifications:
74HC_HCT163_CNV v.2
74HC_HCT163
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
19930927
Product specification
21 of 24
74HC163; 74HCT163
NXP Semiconductors
Product status[3]
Definition
Development
This document contains data from the objective specification for product development.
Qualification
Production
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT163
22 of 24
74HC163; 74HCT163
NXP Semiconductors
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
74HC_HCT163
23 of 24
74HC163; 74HCT163
NXP Semiconductors
18. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Application information. . . . . . . . . . . . . . . . . . 16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21
Legal information. . . . . . . . . . . . . . . . . . . . . . . 22
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Contact information. . . . . . . . . . . . . . . . . . . . . 23
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section Legal information.