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The following questions are practice problems associated with the lecture material on the
subject of Decoders and Multiplexers.
1.
7 Construct a 2-bit counter with a sequence of states 00, 01, 11, and 10 using D flip-flops
and NAND gates
8.You have invented a new type of flip-flop that you have called MY flip-flop. The two
inputs are M and Y, the outputs are Q and Q'. The truth table of your flip-flop is given
below.
MY
Q+
00
01
10
Q'
11
a.
b.
c.
d.
Q.1 What will be the output of Q if J is HIGH, PS and CLR are HIGH, and
the
clock
is
going
negative?
Q.2 Assume that K goes HIGH and J goes LOW; when will the FF reset?
Q.3 What logic levels must exist for the FF to be toggled by the clock?
Q.4 What two inputs to a J-K FF will override the other inputs?
Q.5 How is the J-K FF affected if PS and CLR are both LOW?
10. Give the circuit symbol ,the excitation table and the characteristic equation of each of the following flipflops:
R-S flip-flop.
D flip-flop.
J-K flip-flop.
T flip-flop.
11. A set dominate flip-flop has a set and a reset input. It differs from a conventional R-S flip-flop in that an
attempt to
simultaneously set and reset results in setting the flip-flop.
Obtain the characteristic table and characteristic equation for such a flip-flop.
Obtain a logic diagram for an asynchronous set-dominate flip-flop.
12. Beginning with an R-S flip-flop show how to get
D flip-flop.
J-K flip-flop.
T flip-flop.
13. Beginning with an D flip-flop show how to get
J-K flip-flop.
T flip-flop.
14. Beginning with an J-K flip-flop show how to get
D flip-flop.
T flip-flop.
15. Beginning with an T flip-flop show how to get
D flip-flop.
J-K flip-flop.
16.Implement a new flip-flop type, called X-Y flip-flop, that has the following truth table
X Y Q(t+1)
0 0 Reset
0 1 Q(t)
1 0 Q'(t)
1 1 Set