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3, MARCH 2006
507
I. INTRODUCTION
HE DEVICE dimensions in CMOS technology, the dominant technology for integrated circuits (ICs), have been
scaled for quite some time now to achieve improved performance, particularly in terms of speed of operation, dynamic
power dissipation etc., in addition to increasing the packing density. In conformity with this, scaling of the power supply voltages is also necessary which, in turn, demands a reduction of
the threshold voltage. This, however, gives rise to a significant
increase in leakage current due to subthreshold conduction that
must be modeled accurately for robust circuit design. Modeling
of the leakage current is also important for dynamic circuits as
it determines the holding time of such circuits. Moreover, design of both digital and analog systems in which the devices
are operated in the subthreshold regime has evinced a lot of interest [1][10] due to the tremendous market demand for ex-
Manuscript received July 28, 2005; revised December 2, 2005. This work was
supported in part by the Department of Science and Technology, Government of
India, under Grant SR/S3/EECE/67/2004-SERC-Engg and in part by the Center
for Nanoscience and Technology, Jadavpur University, India. The review of this
paper was arranged by Editor C. McAndrew.
S. Baishya is with the Department of Electronics and Telecommunication
Engineering, Jadavpur University, Kolkata 700 032, India, on leave from the
National Institute of Technology, Silchar, India, under the Q.I.P. Programme
(e-mail: baishya_s@rediffmail.com).
A. Mallik is with the Department of Electronics and Communication Engineering, Kalyani Government Engineering College, Kalyani 741 235, India
(e-mail: abhijit_mallik1965@yahoo.co.in).
C. K. Sarkar is with the Department of Electronics and Telecommunication
Engineering, Jadavpur University, Kolkata 700 032, India.
Digital Object Identifier 10.1109/TED.2005.864364
508
Fig. 1.
MOSFET structure.
channel/pocket implanted device have been reported in the literature [1], [3], [18], [19] that assume a constant depletion layer
thickness in some of which the nonuniformity of the channel depletion layer depth is accounted for by using a fitting parameter.
In this paper, we present a subthreshold surface potential
model for MOS devices in which the effect of varying channel
depletion layer thickness is incorporated. The dependence of
the surface potential on the channel depletion layer around the
source and drain junctions has been incorporated in this model.
A pseudo 2-D analysis applying Gausss law on the surface is
used. The model can successfully generate the subthreshold
surface potential profiles for short channel MOSFET for wide
range of technology parameter values and bias potentials. The
usability of this model is not only limited to the short channel
devices, but can also be applied to long-channel devices.
II. MODEL DESCRIPTION
The MOSFET structure shown in Fig. 1 is used to develop
and implement the model. Applying Gausss law and neglecting
mobile charge carriers to a rectangular box in the channel depletion region of the MOSFET, the following equation can be
derived [3], [18]:
(1)
where
is the surface pois
tential with respect to interior of the substrate bulk,
is the source-to-body voltage,
the gate-to-source voltage,
[20] is the flat-band voltage,
is the gate oxide thickness,
is the oxide
is the channel doping density,
capacitance per unit area,
is the depletion layer depth, and
and
are the dielectric
permitivities of Si and SiO respectively.
If the channel is sufficiently long, then the source-channel and
the drain-channel junction depletion layers constitute a negligible portion of the entire channel length, and the surface potential profile over the channel outside the junction depletion layers
is sufficient to compute any quantity which depends on it. With
this consideration, when the device is in the weak inversion, the
surface potential profile may be considered to remain constant at
[14] and is dependent
only on the gate-to-body bias
, where
is the body effect coefficient and
is the thermal
voltage. However, for short-channel MOSFETs, the contribution of the two junction regions is no longer negligible and the
In reality, in the vicinity of the two ends of the channel, a significant portion of the field lines emanating from source/drain
are mapped onto the space charges below the source/drain (outside the Gaussian box in the channel) and hence a reduced value
of the contribution to the surface integration (Gauss law) by the
two side walls needs to be considered. However, as we move
away from the two ends, this effect diminishes and finally, for a
typical long-channel device, it reduces to zero where
(central portion of the channel). In our analysis, this variation is modeled by considering a reduced value of the height of
and
). Further, this efthe side walls at the two ends (
fect becomes more prominent for higher source/drain bias. The
best fit of the model surface potential profile with ISE TCAD
is found for the bias dependent fitting parameter
for the source side and
for
the drain side. In other words, while computing and we use
and
, instead of,
and
respectively. Note that such a function for the fitting parameter is logical in the sense that it is dimensionally correct and also when
, exactly a symmetrical surface potential profile between the source and drain is produced.
in (1) we get
Using
(3)
The complete solution of (3) is given by
(4)
where is a substituted parameter defined as
and
are the two end values of the parameter in the given
region,
and
and
are the boundary
conditions.
Differentiation of (4) gives
(5)
As mentioned earlier, the channel in general, is required to be
divided into three regions with three different sets of parameters
and . However, at any point over the channel, the surface
potential and its derivative are continuous. Based on the channel
length, doping concentration and applied potentials, following
two cases for the three regions are required to be considered.
: This case arises when the channel
Case-1:
is sufficiently large.
509
Region-I:
: The corresponding
and
.
values of are
The end potentials are
and
to be evaluated.
: Here the depletion
Region-II:
. The end potentials
layer thickness is constant and equal to
and
at both the ends are to be evaluated.
Region-III:
: The corresponding values
and
. The end
are
to be evaluated and
.
potentials are
: In general, this case arises when
Case-2:
the source and the drain regions are close to each other. The tips
of the two depletion layers (curve 1 and 3) due to source and
drain cross each other as shown in Fig. 3 and the DIBL comes
into effect. The crossing point is simply obtained by equating
,
the two corresponding equations as
and
correspond to the
where the parameters
the
curve 1 and 3 respectively. It is assumed that upto
depletion layer thickness is controlled by the source side and
beyond this it is affected by the drain side and nowhere in the
channel the thickness is constant in contrast to the long-channel
devices. This is nothing but short channel effect. Note that this
case may be treated by dividing the channel into two regions
only. However, to enable the use of the same set of solutions,
we divide the channel into three regions for this case as well.
This is done by either dividing the first part (0 to ) or second
part ( to ) arbitrarily into two regions. In our analysis we
have divided the first part into two regions as follows:
: The corresponding
Region-I:
values are
and
with
and
to be evaluated.
the end potentials
Region-II:
: The corresponding and the
end potential values are same as in region-I.
: The corresponding values
Region-III:
and
with the
are
end potentials
to be evaluated and
.
The complete solution needs to be obtained in all the three
regions. However, it may be noted that, if in a region
is constant, the corresponding parameters are
and
. But then,
becomes
indeterminate. Such a situation is handled by considering the
limiting values of the following product terms:
and
The general division of the channel into the following three
regions leads to the values of the various parameters, boundary
values and
as
510
Region-I:
Region-II:
in all the
III. RESULTS
:
Region-III:
:
Using (5) and applying the continuity of derivative of the potentials at the interface between the region-I and the region-II
we get
(6)
where
and
511
TABLE I
OXIDE THICKNESS AND JUNCTION DEPTH FOR MOSFETS
OF DIFFERENT TECHNOLOGY NODES
decreases. The reason for this is that, as expected, the error of assuming a constant channel depletion layer neglecting the effect
of source/drain junction on it becomes more and more severe
as one reduces the channel length. The success of our model
lies in the fact that even if a wide range of parameter variations
including the junction depth is made, the accuracy of the profile generated by our model as compared to DESSIS remains
unaltered.
Our model is also verified for variation of different technology parameters like the substrate concentration, channel
length and gate oxide thickness. This is done by varying these
512
Fig. 6.
= 100 nm, N = 6 2 10 cm
= 1 V.
and V
L
Fig. 7. Surface potential profiles for a long-channel device with L = 700 nm,
= 10 cm ; t = 50 nm, X = 250 nm, and V = V = 0 V.
N
Profiles generated by the model for V = 2 V when L is changed to 1500 and
2000 nm are also shown.
(9)
nm and
V, other device parameters and bias potentials remaining the same. As the proximity of the source and
drain is reduced, that is, as the channel length is increased, the
decrease in the minimum value of the subthreshold surface po. For
tential due to DIBL effect starts reducing for a given
sufficiently long-channel length, no reduction in this minimum
value, that is, no DIBL occurs. This is clearly demonstrated by
the plots of our model. The excellent agreement of our model
with the device simulator DESSIS for all these variations prove
that the model is accurate enough for wide ranges of device dimensions, technology parameters and applied bias voltages.
513
REFERENCES
Fig. 8.
6 2 10
cm
Vs
514
[19] Z.-H. Liu, C. Hu, J.-H. Huang, T.-Y. Chan, M.-C. Jeng, P. K. Ko, and
Y. C. Cheng, Threshold voltage model for deep-submicrometer MOSFETs, IEEE Trans. Electron Devices, vol. 40, no. 1, pp. 8695, Jan.
1993.
[20] Y. Tour and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998.
[21] ISE-TCAD Manuals, 2001. Release 6.1 ed..
[22] International Technology Roadmap for Semiconductors. 1999 and 2001
ed.
[23] K. Goel, M. Saxena, M. Gupta, and R. S. Gupta, Two-dimensional analytical threshold voltage model for DMG epi-MOSFET, IEEE Trans.
Electron Devices, vol. 52, no. 1, pp. 2329, Jan. 2005.