Vlsi Program - Reference

//-----------------------------------------------------
// Design Name : 8 bit adder using parameter

// File Name : nbitadder.v
// Function : two binary numbers addition
//----------------------------------------------------N bit adder program
module nBitAdder(f, cout, a, b, cIn);
parameter n = 7;
output reg [n:0] f;
output reg cout;
input [n:0] a;
input [n:0] b;
input cIn;
always @(a, b, cIn)
{cout, f} = a + b + cIn;
endmodule
// test bench coding starts here
module nbitadder_tb();
parameter n = 7;
//declare o/p's as wire
wire [n:0] f_t;
wire cout_t;
//declare i/p's as reg
reg [n:0] a_t;
reg [n:0] b_t;
reg cIn_t;
nBitAdder dut_test(f_t, cout_t, a_t, b_t, cIn_t); //portmapping
from design to testbench
initial
begin
// inputs
cIn_t<=1'b0;
a_t<= 8'b00001111;
b_t<=8'b00011111;
#100; // delay
// inputs
cIn_t <=1'b0;
a_t<= 8'b00001111;
b_t<=8'b00011111;
#100; // delay
// inputs
cIn_t<=1'b0;
a_t<= 8'b00111111;
b_t<=8'b10011111;
#100; // delay
// inputs
cIn_t<=1'b0;
a_t<= 8'b01111111;
b_t<=8'b00011111;
#100; // delay
// inputs
cIn_t <=1'b0;
a_t<= 8'b11111111;
b_t<=8'b00000000;
#100; // delay
// inputs
cIn_t<=1'b0;
a_t<= 8'b11111111;
b_t<=8'b11111111;
#100; // delay
// inputs
cIn_t<=1'b1;
a_t<= 8'b00001111;
b_t<=8'b00011111;
#100; // delay
// inputs
cIn_t <=1'b1;
a_t<= 8'b00001111;
b_t<=8'b00011111;
#100; // delay
// inputs
cIn_t <=1'b1;
a_t<= 8'b00111111;
b_t<=8'b10011111;
#100; // delay
// inputs
cIn_t <=1'b1;
a_t<= 8'b01111111;
b_t<=8'b00011111;
#100; // delay
// inputs
cIn_t <=1'b1;
a_t<= 8'b11111111;
b_t<=8'b00000000;
#100; // delay
// inputs
cIn_t <=1'b1;
a_t<= 8'b11111111;
b_t<=8'b11111111;
#100; // delay
end
endmodule
O/P Wave form for test bench
4 bit decoder
//----------------------------------------------------// Design Name : decoder_using_case
// File Name : decoder_using_case.v
// Function : decoder using case
//----------------------------------------------------module decoder_using_case (
binary_in , // 4 bit binary input
decoder_out , // 16-bit out
enable
// Enable for the decoder
);
input [3:0] binary_in ;
input enable ;
output [15:0] decoder_out ;
reg [15:0] decoder_out ;
always @ (enable or binary_in)
begin
decoder_out = 0;
if (enable) begin
case (binary_in)
4'h0 : decoder_out = 16'h0001;
4'hA : decoder_out = 16'h0400;
4'hB : decoder_out = 16'h0800;
4'hC : decoder_out = 16'h1000;
4'hD : decoder_out = 16'h2000;
4'hE : decoder_out = 16'h4000;
4'hF : decoder_out = 16'h8000;
endcase
end
end
endmodule
// Test Bench Code starts here
module decoder_using_case_tb ();
reg [3:0] binary_in_t ;
reg enable_t ;
wire [15:0] decoder_out_t ;
decoder_using_case dut_test(binary_in_t ,decoder_out_t ,
enable_t );
initial
begin
// Inputs
// ENABLE LOW
enable_t =1'b0;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
= 4'h1;
= 4'h2;
= 4'h3;
= 4'h4;
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
= 4'h5;
= 4'h6;
= 4'h7;
= 4'h8;
= 4'h9;
= 4'hA;
= 4'hB;
= 4'hC;
= 4'hD;
= 4'hE;
= 4'hF;
// ENABLE HIGH
#100;
enable_t =1'b1;
binary_in_t = 4'h1;
#100;
binary_in_t = 4'h2;
#100;
binary_in_t = 4'h3;
#100;
binary_in_t = 4'h4;
#100;
binary_in_t = 4'h5;
#100;
binary_in_t = 4'h6;
#100;
binary_in_t = 4'h7;
#100;
binary_in_t = 4'h8;
#100;
binary_in_t = 4'h9;
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
= 4'hA;
= 4'hB;
= 4'hC;
= 4'hD;
= 4'hE;
= 4'hF;
// ENABLE LOW
#100;
enable_t =1'b0;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
#100;
binary_in_t
#100;
= 4'h1;
= 4'h2;
= 4'h3;
= 4'h4;
= 4'h5;
= 4'h6;
= 4'h7;
= 4'h8;
= 4'h9;
= 4'hA;
= 4'hB;
= 4'hC;
= 4'hD;
= 4'hE;
binary_in_t = 4'hF;
end
endmodule
Test Bench O/P
//----------------------------------------------------// Design Name : MULTIPLXER

// File Name : MUX.v
// Function : 4:1 MUX
//----------------------------------------------------4:1 MUX without default
module mux (a,b,c,d,sel,y);
input a, b, c, d;
input [1:0] sel;
output y;
reg y;
always @ (a or b or c or d or sel)
case (sel)
0 : y = a;
1 : y = b;
2 : y = c;
3 : y = d;
default : $display("Error in SEL");
endcase
endmodule
// Test bench starts here
module mux_tb ();
reg a_t, b_t, c_t, d_t;
reg [1:0] sel_t;
wire y_t;
mux dut_test(a_t, b_t, c_t, d_t,sel_t,y_t);
initial
begin
// Inputs
a_t<=1'b0;
b_t<=1'b1;
c_t<=1'b0;
d_t<=1'b1;
// selections
sel_t <= 2'd1;
#100;
sel_t <= 2'd2;
#100;
sel_t <= 2'd3;
#100;
sel_t <= 2'd4;
#100;
sel_t <= 2'd1;
// Inputs
a_t<=1'b1;
b_t<=1'b1;
c_t<=1'b1;
d_t<=1'b1;
// selections
sel_t <= 2'd1;
#100;
sel_t <= 2'd2;
#100;
sel_t <= 2'd3;
#100;
sel_t <= 2'd4;

#100;
sel_t <= 2'd1;
// Inputs
a_t<=1'b1;
b_t<=1'b0;
c_t<=1'b1;
d_t<=1'b0;
// selections
sel_t <= 2'd1;
#100;
sel_t <= 2'd2;
#100;
sel_t <= 2'd3;
#100;
sel_t <= 2'd4;
#100;
sel_t <= 2'd1;
// Inputs
a_t<=1'b0;
b_t<=1'b1;
c_t<=1'b0;
d_t<=1'b1;
// selections
sel_t <= 2'd1;
#100;
sel_t <= 2'd2;
#100;
sel_t <= 2'd3;
#100;
sel_t <= 2'd4;
#100;
sel_t <= 2'd1;
end
endmodule
O/P Wave form
/----------------------------------------------------// Design Name : Unsigned Multiplier and Accumulator

// File Name : Multiplier_Accumulator.v
// Function
: Accumulator
//----------------------------------------------------module unsig_altmult_accum
(
input [7:0] dataa,
input [7:0] datab,
input clk, aclr, clken, sload,
output reg [15:0] adder_out
);
// Declare registers and wires
reg [15:0] dataa_reg, datab_reg;
reg sload_reg;
reg
[15:0] old_result;
wire [15:0] multa;
// Store the results of the operations on the current data
assign multa = dataa_reg * datab_reg;
// Store the value of the accumulation (or clear it)
always @ (adder_out, sload_reg)
begin
if (sload_reg)
old_result <= 0;
else
old_result <= adder_out;
end
// Clear or update data, as appropriate

always @ (posedge clk or posedge aclr)
begin
if (aclr)
begin
dataa_reg <= 0;
datab_reg <= 0;
sload_reg <= 0;
adder_out <= 0;
end
else if (clken)
begin
dataa_reg <= dataa;
datab_reg <= datab;
sload_reg <= sload;
adder_out <= old_result + multa;
end
end
endmodule
module unsig_altmult_accum_tb();
reg [7:0] dataa_t;
reg [7:0] datab_t;
reg clk_t, aclr_t, clken_t, sload_t;
wire [15:0] adder_out_t;
unsig_altmult_accum dut_test(dataa_t,datab_t,clk_t, aclr_t, clken_t,
sload_t,adder_out_t);
initial
begin
sload_t<=1'b1;
aclr_t<=1'b1;
clken_t<=1'b0;
dataa_t<=8'd5;
datab_t<=8'd3;
#100;
sload_t<=1'b0;
aclr_t<=1'b0;
clken_t<=1'b1;
dataa_t<=8'd5;
datab_t<=8'd3;
#100;
dataa_t<=8'd5;
datab_t<=8'd5;
#100;
dataa_t<=8'd1;
datab_t<=8'd3;
#100;
dataa_t<=8'd2;
datab_t<=8'd3;
#100;
dataa_t<=8'd4;
datab_t<=8'd3;
#100;
dataa_t<=8'd5;
datab_t<=8'd3;
#100;
dataa_t<=8'd6;
datab_t<=8'd3;
$stop();
end
initial
clk_t = 1'b0;
always #10 clk_t = ~clk_t;
endmodule
O/P Wave form
4 bit counter
module counter (clk, s, q);
input
clk, s;
output [3:0] q;
reg [3:0] q;
always @(posedge clk)
begin
if (s)
q <= 4'b0000;
else
q <= q + 1'b1;
end
//assign q = tmp;
endmodule
// Test bench Starts here
module counter_tb();
reg
clk_t, s_t;
wire [3:0] q_t;

counter dut_test(clk_t, s_t, q_t);
initial
begin
clk_t=1'b0;
s_t<=1'b1;
#100;
s_t<=1'b0;
#100;
s_t<=1'b0;
#100;
s_t<=1'b0;
#100;
s_t<=1'b0;
#100;
s_t<=1'b0;
#100;
s_t<=1'b0;
#100;
s_t<=1'b0;
#100;
s_t<=1'b0;
#100;
s_t<=1'b0;
#100;
s_t<=1'b0;
#100;
s_t<=1'b0;
#100;
s_t<=1'b0;
#100;
s_t<=1'b0;
#100;
s_t<=1'b0;
#100;
s_t<=1'b0;
#100;
s_t<=1'b0;
$stop();
end
always #5 clk_t= ~clk_t;
endmodule
4 bit multiplier
module multiplier (a, b, out);
input [3:0] a;
input [3:0] b;
output [7:0] out;
wire [7:0] out;
assign out = a * b;
endmodule
module multiplier_tb ();

reg [3:0] a_t;
reg [3:0] b_t;
wire [7:0] out_t;
multiplier dut_test(a_t, b_t, out_t);
initial
begin
a_t<=4'd1;
b_t<=4'd2;
#100;
a_t<=4'd5;
b_t<=4'd2;
#100;
a_t<=4'd6;
b_t<=4'd2;
#100;
a_t<=4'd1;
b_t<=4'd5;
#100;
a_t<=4'd1;
b_t<=4'd8;
#100;
a_t<=4'd9;
b_t<=4'd15;
#100;
a_t<=4'd22;
b_t<=4'd33;
#100;
a_t<=4'd11;
b_t<=4'd2;
#100;
a_t<=4'd2;
b_t<=4'd2;
#100;
a_t<=4'd5;
b_t<=4'd2;
#100;
a_t<=4'd1;
b_t<=4'd9;
#100;
a_t<=4'd1;
b_t<=4'd2;
#100;
$stop();
end
endmodule
Test bench O/P
PRBS Generator
module prbs (rand, clk, reset);
input clk, reset;
output rand;
wire rand;
reg [3:0] temp;
always @ (posedge reset) begin
temp <= 4'hf;
end
always @ (posedge clk) begin

if (~reset) begin
temp <= {temp[0]^temp[1],temp[3],temp[2],temp[1]};
end
end
assign rand = temp[0];
endmodule
module prbs_t;
reg clk_t, reset_t;
wire rand_t;
prbs pr (rand_t, clk_t, reset_t);
initial begin
forever begin
clk_t <= 0;
#5
clk_t <= 1;
#5
clk_t <= 0;
end
end
initial begin
reset_t =
#12
reset_t =
#90
reset_t =
#12
reset_t =
#10;
reset_t =
#12
reset_t =
#90
reset_t =
#12
reset_t =
1;
0;
1;
0;
1;
0;
1;
0;
$stop();
end
endmodule
Test bench O/P
Adder/Subtractor
addSub.v
module addSub(A, B, sel, Result);
input sel;
input [3:0] A,B;
output [3:0] Result;
wire [3:0] Result;
assign Result = (sel)? A + B : A - B;
endmodule
testAS.v
module main;
reg [3:0] A, B;
reg sel;
wire [3:0] Result;
addSub as1(A, B, sel, Result);
initial begin
A = 4'b0001;
B = 4'b1010;
end
initial begin
forever begin
#10
A = A + 1'b1;
B = B + 1'b2;
end
end
initial begin
sel = 1;
#200
sel = 0;
end
endmodule
/----------------------------------------------------// Design Name : encoder_using_case
// File Name : encoder_using_case.v
// Function : Encoder using Case
----------------------------------------------------module encoder_using_case(
binary_out , // 4 bit binary Output
encoder_in , // 16-bit Input
enable
// Enable for the encoder
);
output [3:0] binary_out ;
input enable ;
input [15:0] encoder_in ;
reg [3:0] binary_out ;

always @ (enable or encoder_in)
begin
binary_out = 0;
if (enable) begin
case (encoder_in)
16'h0002 : binary_out = 1;
16'h0004 : binary_out = 2;
16'h0008 : binary_out = 3;
16'h0010 : binary_out = 4;
16'h0020 : binary_out = 5;
16'h0040 : binary_out = 6;
16'h0080 : binary_out = 7;
16'h0100 : binary_out = 8;
16'h0200 : binary_out = 9;
16'h0400 : binary_out = 10;
16'h0800 : binary_out = 11;
16'h1000 : binary_out = 12;
16'h2000 : binary_out = 13;
16'h4000 : binary_out = 14;
16'h8000 : binary_out = 15;
endcase
end
end
endmodule
//----------------------------------------------------// Design Name : pri_encoder_using_if

// File Name : pri_encoder_using_if.v
// Function : Pri Encoder using If
----------------------------------------------------module pri_encoder_using_if (
binary_out , // 4 bit binary output
encoder_in , // 16-bit input
enable
);
input enable ;
reg [3:0] binary_out ;
always @ (enable or encoder_in)

begin
binary_out = 0;
if (enable) begin
if (encoder_in == {{14{1'bx}},1'b1,{1{1'b0}}}) begin
binary_out = 1;
end else if (encoder_in == {{13{1'bx}},1'b1,{2{1'b0}}}) begin
binary_out = 2;
binary_out = 3;
binary_out = 4;
binary_out = 5;
binary_out = 6;
binary_out = 7;
binary_out = 8;
binary_out = 9;
binary_out = 10;
binary_out = 11;
binary_out = 12;
binary_out = 13;
binary_out = 14;
end else if (encoder_in == {1'b1,{15{1'b0}}}) begin
binary_out = 15;
end
end
end
endmodule
/----------------------------------------------------// Design Name : pri_encoder_using_assign
// File Name : pri_encoder_using_assign.v
// Function : Pri Encoder using assign
//----------------------------------------------------module pri_encoder_using_assign (
binary_out , // 4 bit binary output
encoder_in , // 16-bit input
enable
);
input enable ;
wire [3:0] binary_out ;
assign binary_out = (!enable) ? 0 : (
(encoder_in == 16'bxxxx_xxxx_xxxx_xxx1) ? 0 :
(encoder_in == 16'bxxxx_xxxx_xxxx_xx10) ? 1 :
(encoder_in == 16'bxxxx_xxxx_xxxx_x100) ? 2 :
(encoder_in == 16'bxxxx_xxxx_xxxx_1000) ? 3 :
(encoder_in == 16'bxxxx_xxxx_xxx1_0000) ? 4 :
(encoder_in == 16'bxxxx_xxxx_xx10_0000) ? 5 :
(encoder_in == 16'bxxxx_xxxx_x100_0000) ? 6 :
(encoder_in == 16'bxxxx_xxxx_1000_0000) ? 7 :
(encoder_in == 16'bxxxx_xxx1_0000_0000) ? 8 :
(encoder_in == 16'bxxxx_xx10_0000_0000) ? 9 :
(encoder_in == 16'bxxxx_x100_0000_0000) ? 10 :
(encoder_in == 16'bxxxx_1000_0000_0000) ? 11 :
(encoder_in == 16'bxxx1_0000_0000_0000) ? 12 :
(encoder_in == 16'bxx10_0000_0000_0000) ? 13 :
(encoder_in == 16'bx100_0000_0000_0000) ? 14 : 15);
endmodule
//----------------------------------------------------// Design Name : decoder_using_case
// File Name : decoder_using_case.v
----------------------------------------------------module decoder (
enable
);
input enable ;
reg [15:0] decoder_out ;

always @ (enable or binary_in)
begin
decoder_out = 0;
if (enable) begin
case (binary_in)
4'hA : decoder_out = 16'h0400;
4'hB : decoder_out = 16'h0800;
4'hC : decoder_out = 16'h1000;
4'hD : decoder_out = 16'h2000;
4'hE : decoder_out = 16'h4000;
4'hF : decoder_out = 16'h8000;
endcase
end
end
endmodule
//----------------------------------------------------// Design Name : decoder_using_assign
// File Name : decoder_using_assign.v
// Function : decoder using assign
//----------------------------------------------------module decoder_using_assign (
enable
);
input enable ;
wire [15:0] decoder_out ;
assign decoder_out = (enable) ? (1 << binary_in) : 16'b0 ;
endmodule
//*********************************************************
module Test_decoder_2to4;
//*********************************************************
wire Y3, Y2, Y1, Y0;
reg A, B;
reg en;
// Instantiate the Decoder (named DUT {device under test})
Decoder (Y3, Y2, Y1, Y0, A, B, en);
initial begin
$timeformat(-9, 1, " ns", 6); #1;
A = 1'b0; // time = 0
B = 1'b0;
en = 1'b0;
#9;
en = 1'b1; // time = 10
#10;
A = 1'b0;
B = 1'b1; // time = 20
#10;
A = 1'b1;
B = 1'b0; // time = 30
#10;
A = 1'b1;
B = 1'b1; // time = 40
#5;
en = 1'b0; // time = 45
#5;
end
always @(A or B or en)
#1 $display("t=%t",$time," en=%b",en," A=%b",A," B=%b",B," Y=%b%b%b
%b",Y3,Y2,Y1,Y0);
endmodule
module mux1( select, d, q );

input[1:0] select;
input[3:0] d;
output
q;
wire
q;
wire[1:0] select;
wire[3:0] d;
assign q = d[select];
endmodule
// Verilog testbench for 4 to 1 Multiplexer
module mux_tb;
reg[3:0] d;
reg[1:0] select;
wire q;
integer i;
mux1 my_mux( select, d, q );
initial
begin
#1 $monitor("d = %b", d, " | select = ", select, " | q = ", q );
for( i = 0; i <= 15; i = i + 1)
begin
d = i;
select = 0; #1;
select = 1; #1;
select = 2; #1;
select = 3; #1;
$display("-----------------------------------------");
end
end
endmodule
// Verilog code for Multiplexer implementation using case statement.

input[1:0] select;
input[3:0] d;
output q;
reg
q;
wire[1:0] select;
wire[3:0] d;
always @( select or d )
begin
case( select )
0 : q = d[0];
1 : q = d[1];
2 : q = d[2];
3 : q = d[3];
endcase
end
endmodule
/ Verilog code for Multiplexer implementation using conditional statement.

input[1:0] select;
input[3:0] d;
output q;
wire q;
wire[1:0] select;
wire[3:0] d;
assign q = ( select == 0 )? d[0] : ( select == 1 )? d[1] : ( select == 2 )? d[2] :
d[3];
endmodule
//----------------------------------------------------// Design Name : dff_async_reset
// File Name : dff_async_reset.v
// Function : D flip-flop async reset
//----------------------------------------------------module dff_async_reset (
data , // Data Input
clk , // Clock Input
reset , // Reset input
q
// Q output
);
//-----------Input Ports--------------input data, clk, reset ;
//-----------Output Ports--------------output q;
//------------Internal Variables-------reg q;
//-------------Code Starts Here--------always @ ( posedge clk or negedge reset)
if (~reset) begin
q <= 1'b0;
end else begin
q <= data;
end
endmodule //End Of Module dff_async_reset

//----------------------------------------------------// Design Name : dff_sync_reset
// File Name : dff_sync_reset.v
// Function : D flip-flop sync reset
//----------------------------------------------------module dff_sync_reset (
q
// Q output
);
//-------------Code Starts Here--------always @ ( posedge clk)
if (~reset) begin
q <= 1'b0;
end else begin
q <= data;
end
endmodule //End Of Module dff_sync_reset
//----------------------------------------------------// Design Name : tff_async_reset
// File Name : tff_async_reset.v
// Function : T flip-flop async reset
//----------------------------------------------------module tff_async_reset (
q
// Q output
);
//-------------Code Starts Here--------always @ ( posedge clk or negedge reset)
if (~reset) begin
q <= 1'b0;
end else if (data) begin
q <= !q;
end
endmodule //End Of Module tff_async_reset
//----------------------------------------------------// Design Name : dlatch_reset
// File Name : dlatch_reset.v
// Function : DLATCH async reset
//----------------------------------------------------module dlatch_reset (
en , // LatchInput
q
// Q output
);
//-----------Input Ports--------------input data, en, reset ;
//-------------Code Starts Here--------always @ ( en or reset or data)
if (~reset) begin
q <= 1'b0;
end else if (en) begin
q <= data;
end
endmodule //End Of Module dlatch_reset
module dflipflop (d, clk, reset,

q);
input d, clk, reset;
output q;
reg q;
always @ (posedge clk or posedge
reset) begin
if (reset) begin
q <= 0;
end
else begin
q <= `TICK d;
end
end
endmodule
module main;
reg d, clk, rst;
wire q;
dflipflop dff (d, clk, rst, q);
//Always at rising edge of clock
display the signals
always @(posedge clk)begin
$display("d=%b, clk=%b, rst=%b,
q=%b\n", d, clk, rst, q);
end
//Module to generate clock with

period 10 time units
initial begin
forever begin
clk=0;
#5
clk=1;
#5
clk=0;
end
end
initial begin
d=0; rst=1;
#4
d=1; rst=0;
#50
d=1; rst=1;
#20
d=0; rst=0;
end
endmodule
// Design Name : up_counter
// File Name : up_counter.v
// Function : Up counter
//----------------------------------------------------module up_counter (
out , // Output of the counter
enable , // enable for counter
clk , // clock Input

reset
// reset Input
);
//----------Output Ports-------------output [7:0] out;
//------------Input Ports-------------input enable, clk, reset;
//------------Internal Variables-------reg [7:0] out;
//-------------Code Starts Here------always @(posedge clk)
if (reset) begin
out <= 8'b0 ;
end else if (enable) begin
out <= out + 1;
end
endmodule
Half adder:
module
halfadder(a,b,sum,carry);
input a,b;
output sum, carry;
wire sum, carry;
assign sum = a^b; // sum bit
assign carry = (a&b) ;
//carry bit
Endmodule
module main;
reg a, b;
wire sum, carry;
halfadder add(a,b,sum,carry);
always @(sum or carry)

begin
$display("time=%d:%b + %b = %b,
carry = %b\n",$time,a,b,sum,carry);
end
initial
begin
a = 0; b = 0;
#5
a = 0; b = 1;
#5
a = 1; b = 0;
#5
a = 1; b = 1;
end
endmodule
\\fulladder.v
module fulladder(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
wire sum,carry;
assign sum=a^b^c; // sum bit
assign carry=((a&b) | (b&c) | (a&c)); //carry bit
endmodule
\\\testfulladder.v
module main;
reg a, b, c;
wire sum, carry;
fulladder add(a,b,c,sum,carry);
always @(sum or carry)
begin
$display("time=%d:%b + %b + %b = %b, carry =
%b\n",$time,a,b,c,sum,carry);
end
initial
begin
a = 0; b = 0; c = 0;
#5
a = 0; b = 1; c = 0;
#5
a = 1; b = 0; c = 1;
#5
a = 1; b = 1; c = 1;
end
endmodule
//----------------------------------------------------// Design Name : up_counter_load

// File Name : up_counter_load.v
// Function : Up counter with load
//----------------------------------------------------module up_counter_load (
out
, // Output of the counter
data , // Parallel load for the counter
load , // Parallel load enable
enable , // Enable counting
clk
, // clock input
reset
// reset input
);
//------------Input Ports-------------input [7:0] data;
input load, enable, clk, reset;
if (reset) begin
out <= 8'b0 ;
end else if (load) begin
out <= data;
out <= out + 1;
end
endmodule
/----------------------------------------------------// Design Name : up_down_counter

// File Name : up_down_counter.v
// Function : Up down counter
//----------------------------------------------------module up_down_counter (
out
up_down , // up_down control for counter
clk
, // clock input
reset
// reset input
);
input up_down, clk, reset;
if (reset) begin // active high reset
out <= 8'b0 ;

end else if (up_down) begin
out <= out + 1;
end else begin
out <= out - 1;
end
endmodule
Random counter:
//----------------------------------------------------// Design Name : lfsr
// File Name : lfsr.v
// Function : Linear feedback shift register
//----------------------------------------------------module lfsr (
out
enable
, // Enable for counter
clk
, // clock input
reset
// reset input
);
input enable, clk, reset;
wire
linear_feedback;
//-------------Code Starts Here------assign linear_feedback = !(out[7] ^ out[3]);
if (reset) begin // active high reset
out <= 8'b0 ;
out <= {out[6],out[5],
out[4],out[3],
out[2],out[1],
out[0], linear_feedback};
end
endmodule // End Of Module counter

LFSR UPDOWN COUNTER
`define WIDTH 8
module lfsr_updown (
clk
, // Clock input
enable , // Enable input
up_down , // Up Down input
count , // Count output
overflow
// Overflow output
);
input clk;
input reset;
input enable;
input up_down;
output [`WIDTH-1 : 0] count;
output overflow;
reg [`WIDTH-1 : 0] count;
assign overflow = (up_down) ? (count == {{`WIDTH-1{1'b0}}, 1'b1}) :
(count == {1'b1, {`WIDTH-1{1'b0}}}) ;
if (reset)
count <= {`WIDTH{1'b0}};
else if (enable) begin
if (up_down) begin
count <= {~(^(count & `WIDTH'b01100011)),count[`WIDTH-1:1]};
end else begin
count <= {count[`WIDTH-2:0],~(^(count & `WIDTH'b10110001))};
end
end
endmodule
TEST BENCH:
module tb();
reg clk;
reg reset;
reg enable;
reg up_down;
wire [`WIDTH-1 : 0] count;
wire overflow;
initial begin
$monitor("rst %b en %b updown %b cnt %b overflow %b",
reset,enable,up_down,count, overflow);
clk = 0;
reset = 1;
enable = 0;
up_down = 0;
#10 reset = 0;
#1 enable = 1;
#20 up_down = 1;
#30 $finish;
end
always #1 clk = ~clk;
lfsr_updown U(
.clk
( clk
),
.reset ( reset ),
.enable ( enable ),
.up_down ( up_down ),
.count ( count ),
.overflow ( overflow )
);
endmodule

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//-----------------------------------------------------

// Design Name : 8 bit adder using parameter

Test Bench O/P

//----------------------------------------------------// Design Name : MULTIPLXER

sel_t <= 2'd4;

/----------------------------------------------------// Design Name : Unsigned Multiplier and Accumulator

// Clear or update data, as appropriate

O/P Wave form

wire [3:0] q_t;

module multiplier_tb ();

Test bench O/P

always @ (posedge clk) begin

reg [3:0] binary_out ;

//----------------------------------------------------// Design Name : pri_encoder_using_if

always @ (enable or encoder_in)

reg [15:0] decoder_out ;

module mux1( select, d, q );

// Verilog code for Multiplexer implementation using case statement.

/ Verilog code for Multiplexer implementation using conditional statement.

endmodule //End Of Module dff_async_reset

module dflipflop (d, clk, reset,

//Module to generate clock with

clk , // clock Input

always @(sum or carry)

//----------------------------------------------------// Design Name : up_counter_load

/----------------------------------------------------// Design Name : up_down_counter

out <= 8'b0 ;

endmodule // End Of Module counter

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