ECE301

Version No.:
Course
Prerequisites :

VLSI System Design

L T P C
3 0 2 4

3.00
ECE103 Digital Logic Design /
ECE101 Electron Devices and Circuits

Objectives :
To illustrate the basic concepts of modern VLSI circuit design.
Describe the fundamental principles underlying digital design using CMOS logic and analyze
the performance characteristics of these digital circuits.
Discuss the basic concepts of Verilog HDL and use it to describe combinational and
sequential circuits HDL at different abstraction levels.
Design the synthesizable digital sub-system components using Verilog HDL.
Verify that a design meets its functionality, timing constraints, both manually and through
the use of computer-aided design tools.
Develop problem-solving skills in order to be able to successfully approach a digital design
project of medium to high complexity in the final semester.
Expected Outcome :
1. apply knowledge of mathematics, science, and engineering in the design, and analysis and
modeling of digital integrated circuits.
2. design and analyze the performance (Speed, Power) of CMOS digital integrated circuits for
different design specifications.
3. identify and interpret the design towards realizing digital IC design.
4. describe digital design using a hardware description language.
5. design and conduct experiments in digital design using Verilog HDL and able to illustrate the
outcome of the design.
6. use modern EDA tools to simulate and synthesize the digital designs.
CMOS Logic Design
Unit 1
Introduction to VLSI Design. Review of MOS Transistor Theory: nMOS, pMOS Enhancement
Transistor, ideal I-V characteristics, C-V characteristics, Non-ideal I-V effects. CMOS logic:
Basic gates, Complex Gates, Multiplexer and Flip-flop.
Circuit characterization and performance estimation
Unit 2
DC transfer Characteristics of CMOS inverter, Circuit characterization and performance
estimation: Delay estimation, Logical effort and Transistor Sizing. Power Dissipation: Static &
Dynamic Power Dissipation.
Stick Diagram and Layout Techniques
Unit 3
CMOS nwell, pwell process, stick diagram for Boolean functions using euler theorem. Layout
basics and techniques for Inverter, NAND and NOR gate.
Introduction to Timing Analysis
Unit 4
Introduction to Static timing analysis. Setup Time, Hold Time. Calculation of critical path, slack,
setup and hold time violations.

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Sub-System Design
Unit 5
Arithmetic Circuits in CMOS VLSI. Design of Adders (RCA, CSA, CLA), Multipliers (both
signed and Unsigned Booth, Baugh wooley), Barrel shifter.
Textbooks
1. Neil H Weste, Harris, A Banerjee, CMOS VLSI Design, 3/e, Pearson Education, Singapore,
2006.
2. John P. Uyemura, CMOS Logic Circuit Design , Springer International Edition.2005.

Reference Books
1. Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, Digital Integrated Circuits: A Design
Perspective, Prentice Hall India, 2nd Ed, 2002.
2. S. Ramachandran, Digital VLSI Systems Design, Springer, 2007.
Mode of Evaluation :

CAT- I & II, Quiz, Lab based Assignments/Mini-project, Term End

Examination.

ECE301

VLSI System Design Lab

List of Experiments

Study of VLSI CAD Tools (Working environment, Introduction to Linux and vi editor,
Cadence Virtuoso ADE with Spectre simuulator/Mentor graphics Design Architect with
Eldo simulator)
Applying MOS I-V equations and small-signal models to MOS circuits
Analyzing switching characteristics and power consumption of the inverter
Analyzing and designing complex CMOS gates for speed
Designing an inverter chain to drive off-chip loads
Physical Design of Analog and Digital cells (layout, DRC,LVS, RCX, Post-layout
simulation)
D FF setup and hold timing analysis

Proceedings of the 29th Academic Council [26.4.2013]

351