ECE 120

Lecture 36

November 30, 2015

Design of the LC-3 datapath

Lecture Topics

Control signals
Instruction cycle

Reading assignments

FL15

Textbook 5.6
Textbook Appendix C.1 - C.3

V. Kindratenko

ECE 120

Lecture 36

November 30, 2015

Datapath, control word

o
o
o

At the high level, LC-3 consists of a datapath, memory, and a control unit
LC-3 datapath includes functional units, registers, and busses
Datapath is controlled by 37 control signals generated by the control unit
o For now we will only consider a simplified version of LC-3 without interrupts and
exceptions support. This architecture requires only 25 control signals
o Put together, 25 control signals form a control word
The figure below shows the datapath and all the control signals necessary to control it
o 25 bits of control signals, No Interrupt or Exception Control signals

LC-3 datapath control signals are listed below

Control Signal
GateXX
LD.XX
xxMUX
ALUK
MIO.EN
R.W

FL15

# of Signals
4
7
6
1
1
1

Total Number of Bits for Control Signals

4
7
10
2
1
1

V. Kindratenko

ECE 120

FL15

Lecture 36

November 30, 2015

7 LD.X signals: LD.BEN, LD.MAR, LD.MDR, LD.IR, LD.PC, LD.REG, LD.CC

o These are all load signals, load inputs to the registers. If LD.X = 1, then register X is
loaded. If LD.X = 0, then register X is not loaded (it retains its current value).
o Usage: Set all LD.X signals to 0, except for any register(s) you need to load. No LD.X
signal is a don't care: we don't want to load 'garbage' into register X. (Even if the
garbage would not be a problem for the current microinstruction, it could cause a
problem for future instructions.)
4 GateX signals: GateMARMUX, GateMDR, GateALU, GatePC
o There are 4 values that can be gated onto the bus: the PC, the ALU output, the MDR
value, and the output of the MARMUX (the value of which can come from the IR or ...).
These are the 4 signals which gate values onto the bus.
o If a value needs to be put onto the bus, one of these GateX signals will be 1. All other
GateX signals must be 0. Never allow more than one GateX value to be 1.
Note: It is permissible to allow 'garbage' onto the bus, since that would only be a
problem if this garbage were to be used. Hence, be careful: if the bus is not used by a
microinstruction and you know three of the GateX values are 0, then the fourth GateX
value can be a don't care.
2 memory signals: MIO.EN, R.W
o These control signals are for use with the memory. If MIO.EN = 1, then the memory is
enabled. If MIO.EN = 0, then the memory is disabled. So if you wish to do a memory
read operation, then MIO.EN = 1 and R.W = 0. If you wish to do a memory write
operation, then MIO.EN = 1 and R.W = 1. If you are not performing a memory operation,

V. Kindratenko

ECE 120

Lecture 36

November 30, 2015

then MIO.EN = 0 and R.W = x; i.e., if the memory is disabled, then the read/write signal
is ignored, and so it does not matter whether the read/write signal is 0 or 1.
1 ALU signal: ALUK (2 bits)
o If we need to perform an ADD, AND, or NOT operation, then the ALU will do it for us:
ALUK inputs need to be set to 00, 01, or 10, respectively. If we need to pass data
through the ALU then ALUK = 11. If the ALU is not being used, then ALUK = xx.
6 MUX select signals: MARMUX, PCMUX (2 bits), ADDR1MUX, ADDR2MUX (2 bits), DRMUX (2
bits), SR1MUX (2 bits)
o Specifying the mux select inputs corresponds to determining the path used for the given
microinstruction. Set the select lines so that the data follows the appropriate path. If the
microinstruction does not use a part of the datapath, then we don't care what those
mux select line values are.

Instruction cycle

LC-3 instruction cycle consists of 3 main phases:

o Fetch Phase: Fetch word from memory into instruction register (IR)
o Decode Phase: Decode word in IR as instruction
o Execute Phase: Execute instruction, Store results
MAR PC
PC PC+1

MDR M[MAR]

FETCH

DECODE
ADD

FL15

State 33

IR MDR

State 35

[opcode]

State 32

LDR

JMP

First state after

DECODE for
ADD instruction

First state after

DECODE LDR
instruction

First state after

DECODE for JMP
instruction

Last state
to carry out ADD
instruction

Last state
to carry out
LDR instruction

PC <- Register

To state 1
18

To state 18
1

To state 1
18

State 18
1

Instruction FETCH and DECODE phase consists of shared states which are identical for all
instructions
Execute phase follows a sequence of states unique for each instruction
LC-3 state machine shows all the states implementing different instructions and transitions
between them
o States correspond to individual RTL statements necessary to implement an instruction
o Some states are shared between multiple instructions
o Other states are unique to individual instructions
o States are numbered with state #18 being the starting state for all the instructions

V. Kindratenko

ECE 120

FL15

Lecture 36

November 30, 2015

Operands in LC-3 Instructions

o DR register address, if present, is stored in IR[11:9] or IR[11:9]
o SR1 register address, if present, is stored in IR[8:6]
o SR2 register address, if present, is stored in IR[2:0]
o Immediate mode operands are stored in lower bits

V. Kindratenko

ECE 120

FL15

Lecture 36

November 30, 2015

Fetch Phase: fetch word from memory into IR

o Its function can be described using 4 RTL statements:
State 18: MAR PC; PC PC+1
GateXX:
xxMUX:
o GatePC=1
o SR1MUX = xx
o GateMARMUX = 0
o DRMUX = xx
o GateMDR = 0
o MARMUX =x
o GateALU = 0
o PCMUX =00
o ADDR1MUX =x
LD.XX:
o ADDR2MUX=xx
o LD.PC=1
o LD.BEN = 0
Other Control Signals
o LD.MAR = 1
o ALUK = xx
o LD.MDR = 0
o MIO.EN =0
o LD.IR=0
o RW =x
o LD.REG =0
o LD.CC = 0

V. Kindratenko

ECE 120

Lecture 36
State 33: MDR M[MAR]
GateXX:
o GatePC=0
o GateMARMUX = 0
o GateMDR = 0
o GateALU = 0
LD.XX:
o LD.PC=0
o LD.BEN = 0
o LD.MAR = 0
o LD.MDR = 1
o LD.IR=0
o LD.REG =0
o LD.CC = 0
State 35: IR MDR
GateXX:
o GatePC=0
o GateMARMUX = 0
o GateMDR = 1
o GateALU = 0
LD.XX:
o LD.PC=0
o LD.BEN = 0
o LD.MAR = 0
o LD.MDR = 0
o LD.IR=1
o LD.REG =0
o LD.CC = 0

xxMUX:
o SR1MUX = xx
o DRMUX = xx
o MARMUX =x
o PCMUX =xx
o ADDR1MUX =x
o ADDR2MUX=xx
Other Control Signals
o ALUK = xx
o MIO.EN =1
o RW = 0

xxMUX:
o SR1MUX = xx
o DRMUX = xx
o MARMUX =x
o PCMUX =xx
o ADDR1MUX =x
o ADDR2MUX=xx
Other Control Signals
o ALUK = xx
o MIO.EN =0
o RW =x

LD.BEN

LD.MAR

LD.MDR

LD.IR

LD.PC

LD.REG

LD.CC

GateMARMUX

GateMDR

GateALU

GatePC

MARMUX

PCMUX

ADDR1MUX

ADDR2MUX

DRMUX

SR1MUX

ALUK

MIO.EN

R.W

Corresponding Control Words:

state

November 30, 2015

010010
100001
100011

0
0
0

1
0
0

0
1
0

0
0
1

1
0
0

0
0
0

0
0
0

0
0
0

0
0
1

0
0
0

1
0
0

x
x
x

00
xx
xx

x
x
x

xx
xx
xx

xx
xx
xx

xx
xx
xx

xx
xx
xx

0
1
0

x
1
x

FL15

Decode Phase: decode word in IR as instruction

o Use opcode to determine next state of control unit
Execute Phase: execute instruction
o Decoding Register Operands
SR2 input: IR[2:0]
SR1 input: IR[11:9] or IR[8:6] or 110 (Need MUX)
DR input: IR[11:9] or 111 or 110 (Need MUX)

V. Kindratenko

ECE 120

Lecture 36

o
o
o
o
o

FL15

November 30, 2015

Notes: R6 (110) ~ stack pointer; R7 (111) ~ used for subroutine calls

Evaluating address/Fetching operands

LD/ST: MAR PC+SEXT(PCoffset9)
LDR/STR: MAR BaseR+SEXT(PCoffset6)
LDI/STI: MAR PC+SEXT(PCoffset9)
Move data across data path to function unit
Activate function unit
Set status bits (condition codes)
Store results
ADD Operation (in register mode) Execute Phase example
State 1: DR SR1 + SR2, Load NZP
GateXX:
xxMUX:
o GatePC=0
o SR1MUX = 01 (IR[8:6])
o GateMARMUX = 0
o DRMUX = 00 (IR[11:9])
o GateMDR = 0
o MARMUX =x
o GateALU = 1
o PCMUX =x
o ADDR1MUX =x
LD.XX:
o ADDR2MUX=x
o LD.PC=0
o LD.BEN = 0
Other Control Signals
o LD.MAR = 0
o ALUK = 00
o LD.MDR = 0
o MIO.EN =0
o LD.IR=0
o RW =x
o LD.REG =1
o LD.CC = 1

V. Kindratenko