20141018roorkee Cas Ws

Synthesis of opamp and phase-locked loop
topologies from first principles

IEEE CAS SBC Workshop on
Advanced Topics in VLSI Circuit Design
Roorkee, India
Nagendra Krishnapura
Department of Electrical Engineering
Indian Institute of Technology, Madras
Chennai, 600036, India
18 October 2014
1 / 135
Motivation
Intuition before full blown analysis

Synthesis instead of ad-hoc introduction
Time domain reasoning/analysis
More intuitive
Exact analysis difficult for complex systems
Frequency domain analysis
More abstract
Can handle complex systems easily
2 / 135
Outline
Negative feedback with integrator as the central element

Synthesis of opamp topologies
Synthesis of phase locked loop topologies
Conclusions
3 / 135
Negative feedback with integrator as the central

element
4 / 135
Outline
Traditional introduction to negative feedback systems

Integrator as controller in a negative feedback system
Intuition and analysis in the time domain
Pedagogical advantages of the proposed introduction
Conclusions
5 / 135
Traditional introduction to negative feedback systems
Vi
+-
Vo
Algebraic systemcannot explain evolution over time

Unstable with arbitrarily small loop delay
Ideal delay Td in the loop oscillations with a period 2Td
Real systems have non-zero delay and dont respond
instantaneously
6 / 135
Intuitive understanding of negative feedback systems
target
(e.g. speed)
+-
controller: change the output

until error goes to zero
error
controller
output
sensor
(e.g. speedometer)
sensor output
(e.g. speedometer reading)
Compare the sensed output to the target (desired output)
Continuously change the output until the output
approaches the target

7 / 135
Example: Driving a car at a given target speed

controller: accelerate or brake
until speed error goes to zero
target
speed
+-
speed
error
controller
output
speedometer
speedometer reading
Compare the sensed speed to the target
Speedometer reading to desired speed
Compute (mentally) the difference
Look at the speedometer!
Keep accelerating (or braking) until error goes to zero
8 / 135
Example: Driving a car at a given target speed

controller: accelerate or brake
until speed error goes to zero
target
speed
+-
speed
error
controller
output
speedometer
speedometer reading
You dont know how much to press the accelerator or the
brake to obtain the desired speed

You keep on doing it until the sensed speed is the same as
the target
9 / 135
Other examples
Driving a car
Controlling the volume: Keep turning the volume knob until
the sensed volume (what your hear) matches target

volume (that you find comfortable)
10 / 135
Nature of the controller

target
(e.g. speed)
+-
constant
error
controller
output
stuck sensor
(e.g. speedometer)
large error
output
error
sensor output stuck
small error
t
large error
small error
t
Controller integrates the error

11 / 135
Negative feedback system with an integrator
target
(e.g. speed)
+-
integrator: change the output

error
dt
output
sensor
(e.g. speedometer)
sensor output
(e.g. speedometer reading)
12 / 135
Negative feedback amplifier
+-
Ve
Vo
u dt
(k-1)R
Vi
computing
the error
Vfb
sensing
the output
Need the output Vo to be gain k times the input Vi

Compare Vo /k to Vi and integrate the error
Steady state when Vo = kVi for constant Vi
13 / 135
Integrator in the negative feedback amplifier
Vo [V]
4
Ve
u dt
Vo = u Ve dt
Ve=1V
u = 109 rad/s
2
u = 2.5x108 rad/s
1
1 2
3 4
t [ns]
Proportionality constant u
Slope of the output = u Ve
14 / 135
Integrator: Frequency domain

|u/j|
-20dB/decade
Ve(s)
u
s
Vo(s) =
u V (s)
e
s
107
<u/j
107
/2
108
108
u=109 rad/s
u=2.5x108 rad/s
109
(log)
[rad/s]
109
(log)
[rad/s]
Described by a single parameter u

u : unity gain frequency
Higher u higher gain magnitude for all frequencies
15 / 135
Integrator: Summary
Vo [V]
4
Ve
u dt
Vo = u Ve dt
Ve=1V
u = 109 rad/s
2
u = 2.5x108 rad/s
1
1 2
t [ns]
3 4
|u/j|
Ve(s)
u
s
Vo(s) =
u V (s)
e
s
-20dB/decade
107
108
109
(log)
[rad/s]
16 / 135
Negative feedback amplifier with constant input
Negative feedback amplifier, k=4, =109 rad/s
Input V
4.5
4.5
Feedback V
Error Ve
3.5
3.5
3
Volts
Volts
3
2.5
2.5
1.5
1.5
0.5
0.5
0
0
3
time [ns]
0
0
Ideal output 4Vi

Actual output Vo
1
3
time [ns]
Error reduces as feedback Vf ramps up

Reduced error slows the rate of output ramp
17 / 135
Negative feedback amplifier with constant input

u
5
4.5
4
+
-
Ve
Vf
u dt
Vo
(k-1)R
R
3.5
3
Volts
Vi
2.5
2
Input Vi
1.5
Ideal output 4Vi
Initial condition=0V
0.5
0
0
3
time [ns]

Vo
= u Vi
k

u
u
Vo (t) = kVi 1 exp( t) + Vo (0) exp( t)
k
k
dVo
dt
(1)
(2)
18 / 135
Negative feedback amplifierSteady state
Vi
+-
Ve=0
u dt
Vo
(k-1)R
Vfb = Vi
R
Zero state error for a constant input Vi (Vo = kVi )

19 / 135
Opamp for implementing a negative feedback amplifier
u dt
(k-1)R
Vfb
+
Ve
-
Vo
Vfb
computing
the error
Vo
+-
Ve
(k-1)R
Vi
Vi
20 / 135
Time domain behavior with constant/step inputs
u dt
Vo
(k-1)R
+-
Ve
Vfb
+
Ve
-
Vo
(k-1)R
Vi
Vi
Vfb
computing
the error
1 dVo
u dt
Vo
= Vi
k

u
Vo (t) = kVp 1 exp t
k
Time constant k /u
Asymptotically reaches Vo = kVi or Vfb = Vi
21 / 135
Relation to frequency domain analysis

Loop gain L(s) =
u,loop
u
=
ks
s
Frequency domain:
Unity loop gain frequency u,loop
Significant negative feedback up to u,loop nearly ideal
behavior up to u,loop (Closed loop Bandwidth)

loop =
1
u,loop
Time domain:
Unit step response of the loop gain
= t/(1/u,loop ) = t/loop
Closed loop response time constant = 1/u,loop = loop
22 / 135
Advantages of this formulation
Not instantaneous-unrealistic anyway

Time evolution naturally built in
Synthesis from common experience of negative feedback
based adjustment in the time domain-amplifier not

arbitrarily thrown in
Intuition and key results obtained from time domain
reasoning
Exponential settling
23 / 135
Controlled sources using an opamp
Our opamp compares voltages; Therefore, voltages have to be

compared for all controlled sources; opamps that compare
currents can also be used
VCVS: Vo = kVi ; Compare Vo /k to Vi
CCVS: Vo = Rf Ii ; Compare Vo Rf Ii to 0
VCCS: Io = Gm Vi ; Compare Io /Gm to Vi
VCVS: Io = kIi ; Compare Io R kIi R to 0
24 / 135
Voltage controlled voltage source

Vi
+
Vo
(k-1)R
Vfb = Vi
R
VCVS: Vo = kVi
Compare Vo /k to Vi and drive the output with the integral
of the error
For constant Vi , Vo = kVi in steady state
25 / 135
Current controlled voltage source

0
+
Vo
Ii
Rf
Vo-IiRf
VCVS: Vo = Rf Ii
Compare Vo Rf Ii to 0 and drive the output with the
integral of the error

For constant Ii , Vo = Rf Ii in steady state
26 / 135
Voltage controlled current source

Vi
Vopa
Io
load
+ V
opa
Io
Io/Gm
R=1/Gm
VCCS: Io = Gm Vi
Compare Io /Gm to Vi and drive the output with the integral
of the error
For constant Vi , Io = Gm Vi in steady state
27 / 135
Current controlled current source

0
Ii
Io
Vopa
(k-1)R
load
+ V
opa
Io
IoR-kIiR
Ii
CCCS: Io = kIi
Compare (Io kIi )R to 0 and drive the output with the
integral of the error

For constant Ii , Io = kIi in steady state
28 / 135
Negative feedback amplifier with delay

target
+-
error
sensed output
controller

output
sensor
(delay Td)
target
+-
error
sensed output
controller
output
sensor
delay Td
Delay is inherent in negative feedback loops. e.g.
Speedometers delay in computing speed

Excess delays can occur in any part of the
system-modeled in the feedback path
29 / 135
Effect of delay on negative feedback

3
target
output
feedback
error
2.5
2
1.5
1
0.5
0
0.5
1
1.5
2
0
Dont know that we have already reached the target

Overshoot the target and then start falling
The process repeats on the other sideringing or
oscillation
30 / 135
Effect of delay on negative feedback

2.5
target
output
feedback
error
2
1.5
1
0.5
0
0.5
1
1.5
0
10
Dont know that we have already reached the target

Overshoot the target and then start falling
The process repeats on the other sideringing or
oscillation
31 / 135
Negative feedback amplifier with delay-Intuition
A small delay doesnt matterHow small?

If there is a long delay, integrate more slowly to avoid
overshootHow slowly?
32 / 135
Negative feedback amplifier with delay in the loop
+-
Ve
Vo
delay Td
R
Vfb
u dt
(k-1)R
Vi
Td /loop 1/e(= 0.367): No overshoot

1/e < Td /loop < /2: Overshoot + ringing
/2 < Td /loop : Unstable
In practice we need a well behaved response (limited

overshoot)
33 / 135

2
1.8
Vo [normalized to kVi]
1.6
1.4
1.2
1
0.8
Td/(k/u) = 0
0.6
T /(k/ ) = 1/e
d
d
Td/(k/u) = 1.0
0.2
T /(k/ ) = 1.5
d
0
0
T /(k/ ) = 0.5
0.4
4
6
time [normalized to k/ ]
u
10
34 / 135
Td /loop
1/e
(0.367)
0.445
0.465
0.5
0.585
0.695
35 / 135
Eliminating instability in presence of delay
Stability governed by the ratio of Td to loop

Reduce Td : Faster circuit/technology
Increase loop Decrease u,loop : Slower integration
36 / 135
Delays in circuit implementationparasitic poles and zeros

QM
u,loop
(1 + s/zk )
QNk =1
Loop gain L(s) =
s
| {z } | k =2 (1{z+ s/pk )}
Ideal
Parasitic
slope=u,loop
slope=u,loop
Td
Td
Unit step response of L(s) is a ramp of slope u,loop (same as

P
PM
ideal) with a delay Td = N
k =1 1/pk
k =1 1/zk
37 / 135
Closed loop response with equivalent delay
38 / 135
Not instantaneous-unrealistic anyway

Time evolution naturally built in
Synthesis from common experience of negative feedback
based adjustment in the time domain-amplifier not

arbitrarily thrown in
Intuition and key results obtained from time domain
reasoning
Exponential settling
Possibility of ringing, overshoot, and instability
39 / 135
Traditional viewpoint
Memoryless amplifier (loop gain) in the ideal case
Frequency dependence as non-ideal feature
Proposed viewpoint
Integrator in the ideal case ( dc gain)
Finite dc gain due to non-ideal implementation
As easy as the gain model to convert to ideal opamps
40 / 135
|Vout/Vd| (dB)
Opamp models
finite dc gain model: A0

first order model: A0/(1+s/d)
integrator model: u/s
full model: A0/(1+s/d)(1+s/p2)(1+s/p3) ...
A0
p2 p3
d
41 / 135
u,loop more fundamental characteristic of the negative
feedback loop than dc loop gain

Increasing u,loop requires higher power
Increasing dc loop gain indirectly influences power
42 / 135
Loop gain of all feedback systems has integrator-like
behavior over some frequency range

Nyquist plot should enter the unity circle near the negative
imaginary axis
Bode plot should have 20 dB/decade slope near the unity
gain frequency
43 / 135
Clear why fastest negative feedback systems are slower
than fastest open loop systems

Clear why max. speed of negative feedback systems
increases with technology
44 / 135
Leads directly to opamp and phase locked loop topologies
45 / 135
References
Adel S. Sedra and Kenneth C. Smith, Microelectronic Circuits, 6th ed., Oxford University Press 2009.
Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer, Analysis and Design of Analog Integrated
Circuits, 5th ed., Wiley 2009.
Nagendra Krishnapura, Introducing Negative Feedback with an Integrator as the Central Element, Proc.
2012 IEEE ISCAS, May 2012.
Nagendra Krishnapura, Synthesis Based Introduction to Opamps and Phase Locked Loops, Proc. 2012
IEEE ISCAS, May 2012.
Karl J. Astrom and Richard M. Murray, Feedback Systems: An Introduction for Scientists and Engineers,
Available:
http://www.cds.caltech.edu/murray/amwiki/index.php/Main_Page
Barrie Gilbert, Opamp myths, Available: http://pe2bz.philpem.me.uk/
Parts-Active/IC-Analog/OpAmps/OpAmpMyths/c007-OpAmpMyths.htm
Hal Smith, An Introduction to Delay Differential Equations with Applications to the Life Sciences, 1st ed.,
Springer 2010.
Nagendra Krishnapura, EE5390: Analog Integrated Circuit Design, Available:
http://www.ee.iitm.ac.in/nagendra/videolectures
46 / 135
Synthesis of opamp topologies
47 / 135
Opamp (integrator) realization

+
Ve
-
Gm1
Igm
Vout
Vout,buf
C1
Z
Gm1
Ve dt
C1
Z
= u Ve dt
Vo =
(3)
(4)
(5)
Gm C integrator
u = Gm1 /C1
48 / 135
Opamp (integrator) realizationFinite dc gain
+
Ve
-
Igm
Vout
Gm1
Ro1
Vout,buf
C1
Finite Ro1 Finite dc gain Steady state error
49 / 135
Steady state error due to finite dc gain

Step response
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
Ideal
Ao=10
0.1
0
0
10
t/
50 / 135
Opamp (integrator) realization
+
Ve
-
Igm
Vout
Gm1
Ro1
Vout,buf
C1
Simplest realization: Single stage opamp

Enhanced Ro1 : Cascode opamp (But, same u )
51 / 135
Transimpedance amplifier for better I-V conversion

part of IGm(=Vo/Rout)
IGm
Ro1
Zc
52 / 135
Transimpedance amplifier for better I-V conversion

part of IGm(=Vo/Rout)
IGm
Ro1
Zc
smaller part of
IGm(=Vx/Rout) Vo-IGmZc
IGm
Zc
Ro1
+
Vx
-
Vo
53 / 135
Improved I-V conversionTwo stage opamp
+
Ve
-
Igm
Gm1
Ro1
C1
54 / 135

C1
Ve=Vo-IGmZc
+
Ve
-
Igm
+
Ve
-
Gm1
Ro1
C1
integrator
Igm
u2 dt
+
Gm1
Vo
Ro1
monitors Ve and
continuously adjusts
Vo until Ve0
55 / 135

C1
Ve=Vo-IGmZc
+
Ve
-
Igm
+
Ve
-
Gm1
Ro1
C1
integrator
Igm
u2 dt
+
Gm1
Ro1
monitors Ve and
Vo until Ve0
C1
+
Ve
-
Vo
Igm
+
Gm1
+
Ro1
Gm2
Ro2
C2
56 / 135
Negative feedback amplifier: Frequency domain
u/s
|A(j)|
loop gain
Vi
+
-
Ve
Vf
u dt
Vo
(k-1)R
|Vo/Vi|
R
u/k
(log)
ideal over this band
k
u/k
(log)
Desired behavior in the region where loop gain is high
57 / 135
Negative feedback amplifier: Frequency domain

9
Magnitude
0.8
0.6
0.4
10
0.2
10
10
10
10
10
0
0.2
Pole at 250Mrad/s
0.4
Phase
[Grad/s]
10
0.6
50
0.8
1
1
0.5
0
[Grad/s]
0.5
100 2
10
10
10
10
[Grad/s]
Vo (s) =
u
s
Vo (s)
Vi (s)
k
1 + us/k
Vo
Vi
k
(6)
(7)
First order response; DC gain = k , pole at u /k

58 / 135
Negative feedback amplifier: Sinusoidal input
Vo (j)
Vi (j)

Vo (j)
k

V (j) = r

2
i
1 + u/k
=
;
k
1+
j
u /k
(8)
Vo (j)
= tan1
(9)
Vi (j)
u /k
dc gain: k (= desired value)

3 dB bandwidth: u /k
59 / 135
Negative feedback amplifier: Low frequency input

u
4
input
ideal output
actual output
3
2
Volts
0
1
2

Vo (j)

V (j) =
i
Vo (j)
Vi (j)
1+
k

= tan1
(10)
2
u /k
(11)
u /k
(12)
Input at 0.1u/k
3
4
0
50
100
150
time [ns]
200
250
Nearly ideal behavior

Gain k , delay k /u
60 / 135
Negative feedback amplifier: High frequency input
Negative feedback amplifier, k=4, u=10 rad/s

4
input
ideal output
actual output
3
2
Volts

Vo (j)

V (j) =
i
Vo (j)
Vi (j)
1+
k

= tan1
1
2
(13)
2
u /k
(14)
u /k
(15)
Input at 10u/k
3
4
0
0.5
1.5
time [ns]
2.5
Attenuated output
Nearly 90 phase lag
61 / 135
Intuition about two stage opamp constraints
I-V conversion bandwidth unity loop gain frequency

u,desired < u,inner
G
Gm1
< m2
C
C2
Bias current determined by Gm
Higher bias current in the second stage
62 / 135
Further improved I-V conversionThree stage opamp

C1
Ve=Vo-IGmZc
+
Ve
-
Igm
+
Ve
-
Gm1
Ro1
C1
integrator
Igm
u2 dt
+
Gm1
Vo
Ro1
monitors Ve and
Vo until Ve0
63 / 135

C1
Ve=Vo-IGmZc
+
Ve
-
Igm
+
Ve
-
Gm1
Ro1
Vo
u2 dt
+
Gm1
C1
integrator
Igm
Ro1
C1
monitors Ve and
Vo until Ve0
C2
+
Ve
-
Igm
+
Gm1
Ro1
Vout
+
Gm2
Ro2
Gm3
Ro3
C3
two stage opamp

64 / 135

C1
C2
+
Ve
-
Igm
+
Gm1
Ro1
Vout
+
Gm2
Ro2
Gm3
Ro3
C3
two stage opamp
65 / 135
Intuition about three stage opamp constraints
I-V conversion bandwidth unity loop gain frequency

u,desired < u,inner
G
G
Gm1
< m2 < m3
C
C2
C3
Bias current determined by Gm
Higher bias currents in the third stage, second stage
66 / 135
Follow up in the frequency domain

Analyze in frequency domain and relate to time domain results
and intuition
Two stage opamp
DC gain
Pole locations, pole splitting (with load)
Stability constraints
RHP zero and its cancellation
Three stage opamp
DC gain
Pole locations
Stability constraints
Zero pair and their optimization
67 / 135
Opamp (integrator) realizationFinite dc gain
Vi
+
+
Ve -
Igm
Gm1
Ro1
C1
68 / 135
Opamp realizationSupply extra current from another

source
monitor Ve and
continuously adjust
Ioff until Ve=0
Vi
+
+
Ve -
Vi
Igm
Gm1
Ro1
C1
+
+
Ve -
Ioff
Igm
Gm1
Ro1
C1
69 / 135
Opamp realizationAdditional negative feedback control
integrator
Kpd,I dt
Gm2a
Vi
+
Ve +
-
Ioff
Igm
Vo
Gm1
Ro1
C1
70 / 135
Opamp realizationAdditional negative feedback control
integrator
Kpd,I dt
Gm2a
Vi
+
Ve +
-
Gm2
Ioff
Igm
Vo
Gm1
Ro1
C1
Vi
Ro2 C2
Gm2a
opamp
Ve +
-
Ioff
Igm
Gm1
Vo
Ro1
C1
71 / 135
Two stage feedforward opamp

+
Gm2
Vi
Ro2 C2
Gm2a
opamp
Ve +
-
Ioff
Igm
Gm1
Ro1
C1
72 / 135
Intuition about feedforward opamp constraints
Additional path operates on steady state error of the first stage

Additional path slower than main path
Doesnt contribute to extra power consumption
73 / 135
Feedforward opamp settling
Additional path operates on steady state error of the first stage

Additional path too fast
Overshoot, instability
Additional path too slow
Initial settling to low accuracy
Creeps up to high accuracy
Pole-zero doublet problem
Not suitable for step-like outputs
Lower power consumption for smoother outputs
74 / 135
Feedforward opamp settling

Step response
1
0.9
0.8
0.7
0.99
0.6
0.98
0.5
0.97
0.4
0.96
45
46
47
48
49
50
0.3
0.2
Single stage opamp, A =100

o
Single stage opamp, A =10

o
0.1
Feedforward opamp, A =100, 10

o
0
0
10
20
30
40
50
t/
75 / 135
Three stage feedforward opamp

+
Gm3
Ro3 C3
Gm3a
+
two stage
feedforward opamp
Vi
Ve +
-
Gm2
Ro2 C2
Gm2a
+
Ioff
Igm
Vo
Gm1
Ro1
C1
76 / 135
Follow up in the frequency domain
Analyze in frequency domain and relate to time domain results

and intuition
Two stage feedforward opamp
Closed loop response
Zero location
Pole-zero doublet
Three stage opamp
Closed loop response
Location of zeros
Poles and zeros
77 / 135
Easy derivation of actual implementation of opamps

Mysterious looking steps leading to stabilization are
removed
Intuitive understanding of constraints in Miller and
feedforward opamps
78 / 135
Synthesis of phase locked loop topologies
79 / 135
Outline
Phase locked loop (PLL) requirements
PLL frequency multiplier
Derivation
Phase model
Type-I PLL
Practical phase detectors
Type-I PLL limitations
Type-II PLL
Feedback systems and stability
Type-II PLL
LC oscillator
Programmable frequency divider
80 / 135
Phase locked loops
Frequency synthesizers in radios for local oscillators

Frequency multiplication for reference clock generation
Phase alignment
81 / 135
Local oscillator requirements

10kHz interchannel spacing
Broadcast AM band
channel
spacing
bandwidth
0.15MHz
Broadcast FM band
GSM uplink band
0.2MHz
GSM downlink band
960MHz
channel
spacing
915MHz
890MHz
890.2MHz
0.2MHz
935MHz
channel
spacing
108MHz
88MHz
935.2MHz
5kHz
1610kHz
530kHz
fc
88.2MHz
0.2MHz
Tuned to the desired channel frequency plus an
intermediate frequency (IF)

Generate equally spaced frequencies from a reference
frequency
82 / 135
Frequency divider
Vref
R(N-1)
Vref/N
fref
fref/N
frequency
divider
Digital frequency divider can generate multiple frequencies

Frequencies not equally spaced
Reference frequency higher than output frequencies
83 / 135
Frequency multiplication analogous to voltage amplification
frequency
error
Vi
+
-
Ve
Vf
u dt
Vo
(k-1)R
R
fref
input + frequency
fout/N
fe
u dt
fout
output
frequency
1/N
84 / 135
Frequency multiplication
frequency difference
input
signal
at fref
zero, at steady state

frequency
measure
fref
fout = ffree+KvcoVctl
Vctl
+
-
dt
VCO
fout/N
frequency
measure
output
signal
at fout
N
frequency
divider
85 / 135
Phase and frequency
Sinusoid: cos((t))
Phase: (t)
Instantaneous frequency: fi =
1 d(t)
2 dt
Typically expressed as fi = fo + fe (t)

fo : average frequency
fe : instantaneous frequency error
Phase (t) = 2fo t + o + 2 fe (t)dt

Phase (t) = 2fo t + o + (t)
o : phase offset-ideal ramp versus time
(t): instantaneous phase
86 / 135
Phase error
70
60
ideal phase
error
phase with error
50
40
30
20
10
0
10
0
10
87 / 135
Integrate frequency difference Phase difference
input
signal
at fref
measure
frequency
Vctl
dt +
VCO
measure phase
dt
measure phase difference
measure
frequency
measure phase
output
signal
at fout
N
frequency
divider
88 / 135
Type-I phase locked loop
input signal at fref
phase
detector
Vctl
VCO
output signal
at fout
N
frequency
divider
Phase detector and VCO in a loop
89 / 135
Voltage controlled oscillator

slope = Kvco
fout
Vctl
fout=KvcoVctl+fo
fo
Vctl
2fot
Vctl
2Kvco
dt
vco
fvco = fo + Kvco Vctl

fo : Free running frequency
vco = 2fo t + 2Kvco
Vctl dt
Kvco : VCO gain in Hz/V

90 / 135
Phase detector
1
2
phase
detector
Kpd(1-2)
Kpd : Phase detector gain in V/radian

Ideal phase detector: assumed to have an output
Vpd = Kpd (1 2 )
91 / 135

input signal
at fref
= ref-out/N
In steady state,
output signal at fout

(fout=Nfref at
steady state)
In steady state,
Vctl = (fout-ffree)/Kvco
Kpd
Vctl
Kpd
VCO
phase
detector
N
= (fout-ffree)/KvcoKpd
frequency
divider
Phase offset = (fout ffree )/Kvco Kpd between input and
feedback signals
|| limited to n due to periodic nature of phase
Limited lock range |fout ffree |
92 / 135
Phase locked loop model

2fot
2freft+ref
Vctl
+
-
Kpd
2Kvco
dt
2fout t+out
2fout/N t+vco/N
1/N
Vctl = 2(fref-fout/N)t + ref - out/N
At steady state, fref=fout/N;
Vctl = ref - out/N
Modelled in terms of phases of signals

At steady state (lock), Vctl is a constant fref = fout /N
The loop locks with
Vctl = Kpd (ref out /N) = (Nfref fo )/Kvco This is the

operating point of the circuit
93 / 135
Phase locked loop model
2fot
2freft+ref+ref
+
-
Vctl+vctl
Kpd
2fout/N t+out/N+out/N
2Kvco
dt
2fout t+out+out
1/N
An increment ref in the input phase causes increments
out , vctl
94 / 135
Phase locked loop modelincremental picture

ref
out
vctl
+
-
Kpd
2Kvco
dt
out/N
1/N
An increment ref in the input phase causes increments
out , vctl
Type-I loopOne integrator in the loop
Phase model of the PLL
95 / 135
Phase locked loop modelfrequency domain

ref(s)
+
-
vctl(s)
Kpd
2Kvco
out(s)
out(s)/N
1/N
Loop gain L(s) = 2Kpd Kvco /Ns
Transfer function
out (s)/ref (s) = N/(1 + Ns/(2Kpd Kvco ))

Type-I loopOne integrator in the loop
Closed loop bandwidth (= unity loop gain frequency)
= 2Kpd Kvco /N rad/s

96 / 135
Type-I PLLlimitations
Phase error when locked (fout = Nfref ):

ref out /N = (Nfref fo )/Kvco Kpd
dc value of Kpd matters; We have a constant Kpd
|ref out /N| < 2 |fout fo | < 2Kpd Kvco
Lock range limited by periodicity of phase detector
Period of all phase detectors not necessarily 2
Commonly used three state phase detector periodic with
2
Kpd Kvco large for wide lock range
97 / 135
Phase detector
Frequency divider output has a varying duty cycle

Phase detector should sensitive to duty cycle
XOR gate etc. are not preferable
Phase detector should be sensitive only to rising edges (or
only to falling edges) of inputs
98 / 135
Tri-state phase detector

A
A
ref
-1
+1
QA
RST
A
B
div
RST
D
QB
output=QA-QB
Output +1, 1, 0
+1 if reference leads divider output
1 if reference lags divider output
0 if reference coincides with divider output
99 / 135
Tri-state phase detector-waveforms

Tref
Tref
+1
A
B
QA
QB
+1
-1
+1
-1
+1
-1
-1
+1
+1
QA
+1
QB
ref-div
A leading B
+1
div-ref
A lagging B
Flip flops assumed to be reset instantaneously
100 / 135
Tri-state phase detector-frequency difference between inputs

A
A
A
ref
-1
+1
QA
RST
A
B
div
RST
D
QB
output=QA-QB
fA > fB : Eventually get two consecutive edges of A

Circulates between 0 and +1 states: Average output > 0
Similarly, average output > 0 for fA < fB
This detector is a phase/frequency detector (PFD)
101 / 135
Tri-state phase detector output

Tref
+1
reference
-1
reference
divider o/p
+1
divider o/p
-1
pdout
+1
-1
Tri-state
phase
detector
pdout
Average value = /
Tref
Output periodic at fref
= ref-div

X
n
Vout (f ) =
sinc
(f nfref )
2 n=
2
X
+
sinc
Vout (t) =
2
n=1
n
2
cos(2nfref t)
102 / 135
Tri-state phase detector

Output average value = /2
Kpd = 1/2
Phase detector offset = 0
Loop locks with = ref out /N = 0 for Nfref = fo
Input range = 2
PLL lock range = fo 2Kpd Kvco < fout < fo + 2Kpd Kvco
Output contains fref and its harmonics
Output = 1/2 ( +
an cos(2nfref t))
Periodic signal in addition to Kpd
All real phase detectors have a periodic error in addition to the

dc term proportional to phase error
103 / 135
Phase detector-Output spectrum

=/2
0.6
0.4
0.2
0
0.2
0
10
10
=/8
0.5
0.5
0
f/f
ref
104 / 135
PLL with tri-state phase detectorperiodic error

n ancos(2nfreft) ("error")
ref
+
-
+
+
out
vctl
Kpd
2Kvco
dt
vco/N
1/N
Error e(t) added to the input of the phase detector
Disturbances in the VCO output phase out (t) even with a
perfect reference (ref (t) = 0)

VCO output: cos(2Nfref t + Nref + out (t))
VCO output not periodic at Nfref
105 / 135
Phase error
70
60
ideal phase
error
phase with error
50
40
30
20
10
0
10
0
10
106 / 135
PLL with tri-state phase detectorfrequency domain

E(s)
ref(s)
+
-
+
+
E(j2f) = n an/2 (fnfref)

vctl(s)
Kpd
2Kvco
out(s)
vco(s)/N
1/N
ref(s) = 0 for a perfectly periodic reference
Transfer function from the error to the output
out (s)/E(s) = out (s)/ref (s) = N/(1 + Ns/(2Kpd Kvco ))

P
E(j2f ) = n (an /2)(f nfref )
107 / 135
Type-I PLL
out (s)
E(s)
out (s)
ref (s)
2Kpd Kvco /Ns
= N
1 + 2Kpd Kvco /Ns
1
= N
1 + sN/2Kpd Kvco
=
(16)
(17)
(18)
(19)
Loop gain
L(s) =
2Kpd Kvco
Ns
(20)
Kpd Kvco
N
(21)
Closed loop bandwidth (Hz)

f3dB =
108 / 135
Type-I PLL
dB
loop gain |L|
2KpdKvco/N
L/(1+L)
|out/ref|
dB
20log(N)
2KpdKvco/N
(loop bandwidth)
109 / 135
Feedback system
In our system,
out (s)
E(s)
= N
2Kpd Kvco /Ns

1 + 2Kpd Kvco /Ns
(22)
In general, in a feedback system with a loop gain L(s)

Hclosedloop (s) = Hideal (s)
L(s)
1 + L(s)
(23)
(24)
Where Hideal (s) is the ideal closed loop gain (with L = ). This
can be approximated as
Hclosedloop (s) = Hideal (s)L(s)
= Hideal (s)
|L| 1
|L| 1
(25)
(26)
110 / 135
PLL with tri-state phase detectorOutput signal

Considering only the term at fref , and b1 1
Vout (t) = cos(2Nfref t + b1 sin(2fref t))
= cos(2Nfref t) cos(b1 sin(2fref t))
sin(2Nfref t) sin(b1 sin(2fref t))
(27)
(28)
(29)
cos(2Nfref t) b1 sin(2fref t) sin(2Nfref t)(30)

= cos(2Nfref t)
(31)
b1 /2 cos(2(N 1)fref t)
(32)
b1 /2 cos(2(N + 1)fref t)
(33)
Spurious tones in the output at a spacing of fref from the
desired frequencyReference feedthrough

In general, spurious tones will be present at nfref from the
desired PLL output

111 / 135
Reference feedthrough
b1 = a1 |H(j2fref )|

Kpd Kvco /jNfref

= a1 N
1 + Kpd Kvco /jNfref

Kpd Kvco

a1 N

jNf
(34)
(35)
(36)
ref
= 2
Nf3dB
sinc
fref
2
(37)
Maximum value of b1 = 4Kpd Kvco when =
112 / 135
Reference feedthroughexample
To generate 1 GHz from 1 MHz reference
b1 /2 = 102 (spurious tones at (N 1)fref 40 dB below the
fundamental output at Nfref )
N = 103
= (locked with a phase shift of )
f3dB /fref = 5 106 f3dB = 5 Hz
Lock range = 2Nf3dB 10 kHz
Lock range is too small; Cant switch to the next channel
which is 1 MHz away!

May not be able to lock for any value of N, unless the free
running frequency happens to be Nfref for some N
113 / 135
input signal
at fref
= ref-out/N
In steady state,
= (fout-ffree)/KvcoKpd

(fout=Nfref at
steady state)
In steady state,
Vctl = (fout-ffree)/Kvco
Kpd
Vctl
Kpd
VCO
phase
detector
N
frequency
divider
= 0 if fout happens to be equal to fref . Zero spurs!
114 / 135
Changing the free running frequency of a VCO
Voff
Vctl
(ffree+KvcoVoff)+KvcoVctl
Vctl
ffree+KvcoVctl
VCO
VCO
ffree = ffree+KvcoVoff
Add a bias to the input to change the free running
frequency
115 / 135
Slowly change the bias until = 0

monitor and
continuously adjust
Voff until =0
input signal
at fref
= ref-out/N

(fout=Nfref at
steady state)
Voff
Kpd
Kpd
phase
detector
ffree
VCO
N
frequency
divider
Slowly change the bias Voff until = 0
116 / 135
Slowly change the bias until = 0

integral
phase
detector
In steady state,
Voff = (fout-ffree)/KvcoKpd
Kpd,I dt
Kpd,I dt
input signal
at fref
= ref-out/N
In steady state,
= 0

(fout=Nfref at
steady state)
Voff
Kpd
Kpd
phase
detector
ffree
VCO
N
frequency
divider
Measure and integrate it to control Voff

117 / 135
Type-II phase locked loop

phase detector + loop filter
integral
phase
detector
Kpd,I dt
input signal
at fref
= ref-out/N
Kpd,I dt
proportional
phase
detector
Kpd
Kpd

(fout=Nfref at
steady state)
VCO
In steady state,
= 0
Proportional + integral loop filter
118 / 135
Type-II PLL with a tri-state phase detector
Lock range is not limited by the phase detector

Loop locks with zero phase difference between reference
and feedback signals

tri-state phase detector output is zero for zero input phase
difference No reference feedthrough!

Reference feedthrough does exist in reality due to
mismatches
119 / 135
Type-II PLLphase model

zero at
steady state
2fot
Kpd,I
dt
2freft+ref
+ Vctl
+
-
2Kvco
dt
2fout t+out
Kpd
2fout/N t+out/N
1/N
dVctl/dt 2(fref-fout/N)t + ref - out/N
ref - out/N = 0;
120 / 135
Type-II PLLincremental model

zero at
steady state
Kpd,I
dt
2freft+ref
+ Vctl
+
-
2fout t+out
2Kvco
dt
Kpd
2fout/N t+out/N
1/N
dVctl/dt 2(fref-fout/N)t + ref - out/N
ref - out/N = 0;
121 / 135
Type-II PLLincremental model

Kpd,I
s
ref(s)
+
-
vctl(s)
2Kvco
out(s)
Kpd
out(s)/N
1/N
122 / 135
Type-II PLLFrequency domain
p1 > 2KpdKvco/N
more poles can be used
Kpd,I
s
ref(s)
+ vctl(s)
Vctl
1
1+s/p1
+
+
-
2Kvco
out(s)
Kpd
out(s)/N
1/N
123 / 135
Type-II PLLImplementation
Tref
reference
+1
reference
divider o/p
-1
divider o/p
+1
tri-state
phase
detector
R1 proportional
iout
R1
reference
divider o/p
tri-state
phase
detector
C1
iout
+
proportional
+ integral
output
C1 integral
output
proportional +IcpR
output
-IcpR
integral
output
divider o/p
tri-state
phase
detector
output
+Icp
-Icp
reference
= ref-div
-1
pdout
iout
slope=Icp/C
Phase detector with a current output (Icp )

Integral term Kpd,I /s: Current flowing into a capacitor C1
Proportional term Kpd : Current flowing into a resistor R1
Series RC to obtain the sum
Kpd = Icp R1 /2; Kpd,I = Icp C1 /2
124 / 135
Tri-state phase detector with charge pump

Vdd
Icp
1
A
ref
QA (UP)
iout
RST
+
B
div
R1
RST
QB (DN)
proportional
+ integral
output
C1
Icp
QA and QB drive a charge pump

Charge driven into the loop filter Icp Tref /2
125 / 135
Noise sources in a PLL

Kpd,I
vco
vnc
s
ref
+
-
2Kvco
s
out
Kpd
out/N
1/N
Noise can be added as ref (reference phase noise,
charge-pump noise, divider output phase noise) or

vnc (loop filter noise) or vco (VCO phase noise)
Need to compute transfer functions from each of these
noise sources to out

126 / 135
Type-II PLL: transfer functions
L(s) =
u,loop =
z1 =
out (s)
ref (s)
out (s)
Vnc (s)
out (s)
vco (s)
=
=
=

u,loop z1
s
1+
s
s
z1
2Kpd Kvco
Icp RKvco
=
N
N
Kpd,I
1
=
Kpd
RC
1 + s/z1
N
1 + s/z1 + s2 /z1 u,loop
s/z1
N
Kpd 1 + s/z1 + s2 /z1 u,loop
s2 /z1 u,loop
1 + s/z1 + s2 /z1 u,loop
(38)
(39)
(40)
(41)
(42)
(43)
127 / 135

L(s)
1 + L(s)
1 + s/z1
1 + s/z1 + s2 /z1 u,loop
(44)
Two poles and a zero

Zero z1 = Kpd,I /Kpd
p
2Kpd,I Kvco /N
p
p
Quality factor Q = z1 /u,loop = NKpd,I /2Kvco /Kpd
p
Damping factor = 1/2Q = 1/2 u,loop /z1
Natural frequency n =
For well separated (real) poles (z1 u,loop ),
p1 z1 + z12 /u,loop z1 , p2 u,loop z1 ,

Pole zero doublet {p1 , z1 }; p1 at a slightly higher frequency
than z1
128 / 135

5
5
2
10
1/N|
out
ref
/ | [dB]
1
0
15
20
25 3
10
1 3
10
10
10
10
=4.08
=0.3162
=1
2
10
10
/
10
10
u,loop
out (s)
ref (s)
= N
1 + s/z1
1 + s/z1 + s2 /z1 u,loop
(45)
Peaking in |out /ref | because of the zero

Damping factor 1 to avoid peaking slow settling
129 / 135

PLL transfer functions
30
20
Magnitude response [dB]
10
0
10
20
30
40
out/ref
50
70 2
10
/v *1V
out nc
60
out/vco
1
10
10
f/f
10
10
u,loop
(Example parameters:
N = 10, z1 = 0.1u,loop , N/Kpd = 2Kvco /u,loop = 25 V1 )
|out /ref |: Lowpass with a dc gain N
|out /vnc |: Bandpass with peak gain N/Kpd = 25 V1
|out /vco |: Highpass with a high frequency gain of 1
130 / 135
Type-II PLL phase noise example

PLL phase noise components
20
40
60
dBc/Hz
80
100
120
140
160
180 2
10
reference
ref. contribution to PLL
VCO
VCO contribution to PLL
Total
1
10
10
f/f
10
10
u,loop
(Example parameters:
N = 10, z1 = 0.1u,loop , N/Kpd = 2Kvco /u,loop = 25 V1 )
Reference contribution dominant below 0.1u,loop
VCO contribution dominant above 0.1u,loop
VCO contribution reduced by the loop upto u,loop
Charge pump and loop filter noise ignored in the above
131 / 135
Intuition about the Phase locked loop
Reason for using a phase detector for frequency synthesis

Reason for an additional integrator in the loop filter
Integral path for adjusting Voff slower than the main
path (type-I)
PLL bandwidth (unity loop gain frequency) is the same as in
the type-I loop

Presence of a zero before the PLL bandwidth (unity loop
gain frequency)
Integral path influences the phase transfer functions only
well below the PLL bandwidth
132 / 135
Analysis of type-II phase locked loop
Pole zero locations

Phase (jitter) transfer functions
Higher order loop filter for higher spur suppression
133 / 135
Conclusions
Negative feedback: Continuous adjustment to reduce error

Integrator is the key element of the negative feedback loop
Implementing a voltage integrator and seeking to improve
its performance leads to commonly used opamp topologies

Implementing a negative feedback frequency multiplier and
seeking to improve its performance leads to type-I and II

phase locked loops
Valuable intuition gained before embarking on analysis
134 / 135
References
Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer, Analysis and Design of Analog Integrated
Circuits, 5th ed., Wiley 2009.
R. D. Middlebrook, Methods of design-oriented analysis: Low-entropy expressions, New Approaches to
Undergraduate Education IV, Santa Barbara, 26-31 July 1992.
Nagendra Krishnapura, Introducing negative feedback with an integrator as the central element, Proc. 2012
IEEE ISCAS, May 2012.
Shanthi Pavan, EC201: Analog Circuits, Available:
Floyd M. Gardner, Phaselock Techniques, 3rd ed., Wiley-Interscience 2005.
Roland Best, Phase Locked Loops: Design, Simulation and Applications, 5th ed., McGraw-Hill 2007.
Stanley Goldman, Phase Locked Loop Engineering Handbook for Integrated Circuits, Artech House 2007.
Behzad Razavi, Design of Analog CMOS Integrated Circuits, 1st edition, McGraw-Hill, 2000.
Nagendra Krishnapura, EE5390: Analog Integrated Circuit Design, Available:
135 / 135

20141018roorkee Cas Ws

Caricato da

Informazioni sul documento

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

20141018roorkee Cas Ws

Caricato da

Copyright:

Formati disponibili

Synthesis of opamp and phase-locked loop

topologies from first principles

Intuition before full blown analysis

Negative feedback with integrator as the central element

Negative feedback with integrator as the central

Traditional introduction to negative feedback systems

Traditional introduction to negative feedback systems

Algebraic systemcannot explain evolution over time

Intuitive understanding of negative feedback systems

controller: change the output

approaches the target

Example: Driving a car at a given target speed

Example: Driving a car at a given target speed

brake to obtain the desired speed

the sensed volume (what your hear) matches target

Nature of the controller

sensor output stuck

Controller integrates the error

Negative feedback system with an integrator

integrator: change the output

Negative feedback amplifier

Need the output Vo to be gain k times the input Vi

Integrator in the negative feedback amplifier

Integrator: Frequency domain

Described by a single parameter u

Negative feedback amplifier with constant input

Negative feedback amplifier, k=4, =109 rad/s

Negative feedback amplifier, k=4, =109 rad/s

Ideal output 4Vi

Error reduces as feedback Vf ramps up

Negative feedback amplifier with constant input

Ideal output 4Vi

Negative feedback amplifierSteady state

Zero state error for a constant input Vi (Vo = kVi )

Opamp for implementing a negative feedback amplifier

Time domain behavior with constant/step inputs

Relation to frequency domain analysis

behavior up to u,loop (Closed loop Bandwidth)

Advantages of this formulation

Not instantaneous-unrealistic anyway

based adjustment in the time domain-amplifier not

Controlled sources using an opamp

Our opamp compares voltages; Therefore, voltages have to be

Voltage controlled voltage source

Current controlled voltage source

integral of the error

Voltage controlled current source

Current controlled current source

integral of the error

Negative feedback amplifier with delay

controller: change the output

controller: change the output

Delay is inherent in negative feedback loops. e.g.

Speedometers delay in computing speed

system-modeled in the feedback path

Effect of delay on negative feedback

Dont know that we have already reached the target

Effect of delay on negative feedback

Dont know that we have already reached the target

Negative feedback amplifier with delay-Intuition

A small delay doesnt matterHow small?

Negative feedback amplifier with delay in the loop

Td /loop 1/e(= 0.367): No overshoot

In practice we need a well behaved response (limited