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50

Part I

Semiconductor Devices and Basic Applications

Power transformer
,-­
+
AC
voltage
source
~

Figure 2.1

Diode

rectifier

Filter

- f-­

-

f-­

~

Voltage

regulator

c---"

Block diagram of an electronic power supply

power source. We will use the piecewise linear approach to analyze this circuit, assuming that the diode forward resistance rf = 0 when the diode is "on." Figure 2.2(b) shows the voltage transfer characteristics, Vo versus v I, for the circuit. For VI < 0, the diode is reverse biased, which means that the current is zero and the output voltage is zero. As long as VI < V y , the diode

will be nonconducting, so the output voltage will remain zero. When VI

the diode becomes forward biased and a current is induced in the circuit. In this case, we can write

>

V r

and

.

tv

Vo

For VI

=

VI - R V y

= ivR

V

>

y ,

=

 (2.1(a) ) VI - Vy (2.1(b»

the slope of the transfer curve is 1.

+

"v

- +
R

(a) 1'0

(b)

Figure 2.2

characteristics

Diode in series with ac power source: (a) circuit and (b) voltage transfer

If VI is a sinusoidal signal, as shown in Figure 2.3(a), the output voltage can be found using the voltage transfer curve in Figure 2.2(b). For VI :::; V. the output voltage is zero; for VI > V y , the output is given by Equation (2.1(b)), or

Vo

=

VI

-

V y

and

alternates polarity and has a time-average value of zero, the output voltage Vo is unidirectional and has an average value that is not zero. The input signal is therefore rectified. Also, since the output voltage appears only during the positive cycle of the input signal, the circuit is called a half-wave rectifier.

is shown

in Figure 2.3(b). We can see that while the

input signal ('I

Chapter 2

Diode Circuits

55 N I :N z
3
5
+
• +
vI
Vs
0

(a)

4

2

Ivsl

+ (b) v

2T

t

(c)

Figure 2.7

inputcycle, (b) current direction for a negative input cycle, and (c) input and output voltage waveforms

A full-wave bridge rectifier (a) circuit showing the current direction for a positive

\'0 is as shown in Figure 2.7(a). During the negative half-cycle of the input voltage. Vs is negative, and D 3 and D 4 are forward biased. The direction of the current, shown in Figure 2.7(b), produces the same output voltage polarity as before. Figure 2.7(c) shows the sinusoidal voltage Vs and the rectified output voltage \'0' Because two diodes are in series in the conduction path, the magnitude of Vo is two diode drops less than the magnitude of vs.

Example 2.2 Objective: Compare voltages and the transformer turns ratio in two full-wave rectifier circuits. Consider the rectifier circuits shown in Figures 2.6(a) and 2.7(a). Assume the

input voltage is from a 120 V (rms), 60 Hz ac source. The desired peak output voltage

II) is 9 V. and the

diode cut-in voltage is assumed to be V, = 0.7 V.

Solution: For the center-tapped transformer circuit shown in Figure 2.6(a), a peak voltage of I'ot max) = 9 V means that the peak value of vs is

Is(max) = va(max) +

V,

=

9

+ 0.7

=

9.7 V

For a sinusoidal signal, this produces a rms value of

I'S.frm =

9.7 ----;= = 6,86 V

\/2

The: t urn, ratio of the primary to each secondary winding

:"""':'=---=17')

.\"~

6,86

\

1"')()

must then be

For the bridge circuit shown in Figure 2.7(a), a peak voltage of va (max) = means that the peak value of vs is

vs(max) =

va(max) + 2V, =

9 + 2(0.7)

=

10.4 V

9 V

Chapter 2

Diode Circu its

55

0

+

v/ N] N 2
3
• +
Vs

(a)

4

2

IVsI

+ (c) 2T

I

(b)

Figure 2.7 A full-wave bridge rectifier (a) circuit s howing the current direction for a positive input cycle , (b) current direction for a negative input cycle, and (c) input and outp ut voltag e waveforms

\' 0 is as shown in Figure 2.7(a) . During th e negative half-cycle o f th e input volt age. Vs is negative, and D 3 and D 4 a re forward biased. The direction o f the current, sh own in Figure 2.7(b), produces the same output volt age polarity as before. Figure 2.7(c) shows the sinusoida l voltage Vs and the rectified output vol tage \ ' 0' Because tw o diodes ar e in series in th e condu ction path . th e magnitude of Vo is two di od e drops less than the ma gnitude o f vs.

Example 2.2 Objective: Co m pare vo ltages and th e t ran sform er turn s ratio in two full-wave recti fier c ircuits. Consider th e re ctifier circ uits shown in Figur es 2.6(a) and 2.7(a). Assume th e

 in put vo ltage is fro m a 120 V ( rms), 60 H z ac so u rce . T he d esired peak o u tput vo ltage I ' f) is 9 V. an d t he di od e cut -in vo ltage is ass umed to b e V, = 0.7 V. Solution: For th e ce nte r-tappe d transformer circuit sho wn in Figure 2 .6(a), a peak

voltage of ,'o ( max) = 9 V me an s that the pe ak

value o f vs is

I's( max) =

vo( max) +

V,

=

9

+ 0 .7

=

9 .7 V

Fo r a sinuso ida l sig nal. this

I

Sf ",

'

=

9; = 6 .86 V

\' 2

pr oduces a rm s value of

T he

tu rn s

ratio o f th e prim ary to

each seco nda ry windin g mu st th en be

\

<== 6 .86 = 17 . 5

1::'0

For th e brid ge circuit sho w n

in

me an s that th e pe ak

value of vs is

vs(max) = vo( max) + 2V,

=

9

Fi gure

2 .7( a) , a

pe ak

+ 2(0 .7)

=

lOA V

vo ltage o f vo( max) =

9 V

Chapter 2

Diode Circuits

57

v, \
\
\ I

I

I

-,

\

Vo

\

\

I

I

I

-,

\

\

\

T'

Figure 2.9

Output voltage of a full-wave rectifier with an RC filter

Th e smallest output voltage is

V =

L

VM e-TIR C

(2.3)

where T' is the discharge time , as indicated in the figure . Th e ripple voltage V, is defined as the difference between and is determined by

V r =

V M

-

V L

=

V <\.f(J

-

e- T ' IRC)

V~l and

V L .

(2.4)

to be sm all compared to

the time constant , or T' ~ RC. Expanding the exponential in a se ries and

keeping only the linear terms of

th at expansion, we hav e th e approximation

Normally, we will want the di scharge time T'

e- r 'IRC == 1 -

T'

­

RC

(2.5)

Th e ripple volt age can now be written a s

V-V (T)

r

=

,l/

RC

(2.6)

Sin ce the discharge time T' dep end s on the RC

so that

time con stant, Equat ion

then as an

(2,6) is difficult to solve . However , if the ripple e ffect is sm all.

approxim ation. we can let T' = T",

v

,\1 II. (!'L)

==

RC

(2.7)

where T; is the tim e between peak

wave rectifier, T; is one-half the to the signal frequency ,

valu es of the o utp ut voltage . For a full­

can relate T

"

signal period . Therefore. we

1

f =2 T

p

The rippl e voltage is then

V=~

r

2fRe

(2.8)

period (not a

half period) of the signa l,

Equ ation (2.8) can be used to determine the ca pacito r value required for a particular ripple voltage.

so the fa ctor 2 doe s not appear in Equ ation (2.8).

For a half-wave rectifier, the

time T p corresponds to a full

Chapter 2

Diode Circuits

69

D2.7 Design a parallel-b ased clipp er th at will yield the volt age transfer fun ction

shown in Figure 2.25 . Assume diode cut-in voltages o f V

2.20(a) , V 2 =

2.8 Repeat Example 2.6 if the dir ection of the di ode is reversed . (Ans. Output is a

square wave between - 2 V a nd +6 V )

volt age Vo for the circu it shown in Figure

2.26(a ), if the input is as sho wn in Figure 2.26(b). A ssum e the di od e cut- in voltage is

2.9 Determine the ste ady-sta te output

= 0.7 V. (A ns. Using Figure

r

4.3 V, V I

=

1.8 V, and

R 1 =

2R 2 )

V y = O. (A ns. Output is a squa re wave between

+ 5 V

a nd

+35 V )

C= I/lF

+-----1[--;----------0

+ +

VB=5 v czz:

(a)

Figure 2.26

T= I ms-j

+ 10

Of- -+--+----i­-

- 20

(b)

-+----+-­

Figure for Exercise 2.9

-+­-

-

2.3 ZENER DIODE CIRCUITS

In Ch apter 1, we saw that th e br eakdow n volt age of a Ze ne r d iode was nearl y consta nt over a wide ran ge of rev erse-bias curre nts. T his mak es th e Z en er diod e useful in a voltage regulator, or a constant-voltage reference circuit. In

e ffects

this ch apt er, we will look a t a n ideal voltage reference circuit, and the of including a non ideal Zener resistance.

2.3.1 Ideal Voltage Reference Circuit

Figure 2.27 sho ws a Zener vo ltag e regul at or circuit. For thi s circ uit, the o utp ut voltage should rem ain constant, eve n when th e out put load resistance varies ove r a fairl y wide ran ge , and wh en the input vo ltage va ries over a specific range .

R, +

Figure 2.27

A Zener diode voltage regulator circuit

We determin e , initially, the proper input resistan ce R i . T he resistance R, limit s the current through the Ze ne r d iode and drop s the "e xcess" voltage

Chapter 2

Diode Circuits

71

 Design Example 2.7 Objective: D esign a volt age reg ula tor, usin g th e ci rcuit show n in Figure 2.27 . Ass ume th at th e Z en e r d iode has a break down vo ltage of Vz = 10 Y, th e pow er

s upply is in

500 n. D ete rm ine R, a nd

ran ge 20

th e

:S

V ps :S

2 4

Y,

a nd

va ries fr o m 100 to

the re qu ire d pow e r ra ting of the

Z en e r diode .

Solution : T he m aximum a nd m inimum lo ad c ur ren ts are

Idm ax ) = R d

V z

10

mi n) = Q.1 = 100 rnA

and

.

Idm tn )

=

R d

V z

m ax )

10

= -=20mA

0.5

Usi ng E qu at ion (2 .27), th e ma ximum Zene r diode

curre nt is

1_(

z

.) =

ma x

(100) ' [24 -

10] -

(20)' [20 -10 ] = 140

20 _ 0.9(10) _ 0. 1(24)

m

A

T he maximum pow er d issipa tio n in the Z en er diode is

P z (m ax) =

Iz (m ax ) V z

= (0 .14)(10) = 1.4 W

Fro m E q ua tion (2 25(b)), the va lue o f th e inp ut re sist ance

R, is

 R, = Vps( m ax) - V z = 24 - 10 =) 87 .5 n Iz (m ax ) + Id mtn ) 140 + 20

Comment:

the diode

Iz :S Iz (m ax ). as th e des ign specified .

By c o nsideri ng variou s co mbina tio ns of V ps a nd R L , we ca n det erm ine that

140 m A , o r O.lI z (max) :S

cu rre nt r em a ins wi thin the ran ge of

14

:S

l z

:S 2.3.2 Zener Resistance and Percent Regulation

zero. In actu al Zen er d iodes,

th e o utp ut vo ltage is a function

of the Z en er d iod e cu rre nt or the load curre nt. Figure 2.28 sh ows th e equ ivalent circuit of th e vol tage regulator in Figur e 2.27. Becau se of th e Ze ner res istance, th e output voltage will not remain co nsta nt. We ca n de ter m ine the m inimum a nd maximum va lues of o utput voltage . A figure of me rit fo r a vol tage reg ulato r is called the percent regula-

In the ideal Ze ner diode, the Z ener resist ance

however. this is not

is

th e case. The result is that

R,

\ PS -=-

I ,

I z~

+ t Id

r z

V z

~

R L

+

v

L 84
+
+
D
R
Vo

Figure P2.2

Pa rt I

Semicond uctor

Devices and Basic Appl ication s

2.2 For th e circu it shown in Figure P2.2, show that for 1', :2: O. th e output vo ltage

is a pproxi ma te ly give n by

Va

=

v i

:

V Tln (~~)

2.3 A ssume th e input to th e circuit shown in Figure P2.2 is a triangular wave of

20 V peak-t o-p eak a mplitude with a zer o tim e-aver age valu e. Le t R = 1 kfl a nd ass ume

piecew ise linear diode param et ers voltage versus tim e over on e cycle

02.4 Th e input signa l voltage to th e full-wave rectifier circ uit show n in Figure 2.7(a)

in th e tex t is 1', = 160 sin[2rr(60)1] V. A ssume V y = 0.7 V for each d iod e. Det erm ine th e required turns ratio of th e trans former to produce a peak output volt age of (a)

25 V. and

02.5 T he o utput res ista nce

text is R = 150 fl. A filter ca pacitor is connected in par allel with R. As sume V y =

0.7 V. Th e peak out put

th an 0.5 V. T he input frequ en cy is 60 H z. (a) Det ermine the requ ired rm s va lue o f I's . (b) D etermin e th e re quire d filter capacitance va lue. (c) Determ ine the peak current th rough each diod e.

02.6 Rep eat Pr o blem 2.5 fo r a half- wave rectifier ; th

from th e circuit show n in Figure 2.7(a)

2.7 Th e circuit shown in Fig ure P2.7 is a co mpleme nta ry output recti fier. If I' s =

of V y = 0.6 V and r f = 20 fl . Sketch th e output and label all appro pr iate voltages.

(b)

100 v.

o f th e full-wave rec tifier shown in Figure 2.7(a) in th e

be

24 V a nd

the

rip ple volt age is to

be

no mor e

volt age is to

at is D 3 and D 4 a re e limina ted

 26 s in [2rr(60) 1] V, ske tch th e o utp ut w avef orm s v; a nd v; ve rs us t ime , ass uming V y = 0.6 V for eac h di od e .

~

J I/ o
,. s
R
,
I'
R
,.­
0

• +

• +

Figure P2.7

 02.8 th at eq ua l filter ca pac ito rs are co nnec ted in para llel with eac h load resis to r A ss ume R in the cir cuit d escribed in P roblem 2.7. If R = 100 fl a nd the ripp le vo ltage is to be no more th an V, = ] V, det ermine th e value of C required. *02.9 A full-w ave rectifier a nd a n input volt age are shown in F igure P2.9. T he cut­

in voltage of ea ch d iode is V y =

T he ave rage pow er d issipa te d in R L

valu e

0 .6 V . (a)

to

is

of R L .

Sketch th e o utput volt age vers us time. (b)

be

P L

=

]0 0 rnW. Det ermin e the correct

+ +;~h

I

:rv r. »--~- "o

Figure P2 .9

Chapter 2

Diode Circuits

85

*2.10

Sk et ch

Va ve rs us time

show n. A ssume V y = O.

fo r

th e

ci rcui t give n In

Fig ure

'

+40

-40

~

+

Vi Figure P2 .10

n. lO wit h the

inp ut +

Figure P2.11

Ske tch Va

a

of th e o utp ut vo ltage.

*2.11

(a)

ve rsus time fo r th e circuit show n in Figu re P2.l l. The in put is

e rm ine th e rms val ue

sine wave give n by Vi

=

10 si nwt V. Ass ume V y =

O. (b)

D et

Section 2.2

Clipper and Clam per Circuits

2.12 (a) Co nsi der th e circ ui t s how n in Figu re P2.12

ou tput vo ltage Re peat part (a)

in p ut is a sine wave

ve rs us tim e

if

V y

if th e

= 0.7 V .

a nd ass ume

wi th a

V y = O. Ske tch the

10 V.

(b)

pea k valu e of

R = I kO +SV

Figure P2 .12

I H2 I

kO

2kn

,.-'l/v'Vlr--4--'WV\r-- +

15 V

Figure P2 .13

2.13 Fo r

th e

ci rcuit

VI

S

I S V. Ass ume V,

=

shown

0.7 V. Ind icat e a ll b rea kpo ints .

in

Figure

P2 .13,

p lot

V a

ve rsus

VI

for

0

s

2.14

V o

a nd

*2.15

v,

A ssum e

i o

V y

= 0.6 V

for

the di ode in th e circ uit giv e n in Fig ur e P2.l 4. Ske tch V.

s i n w l

has piecew ise line ar pa rame ­

If th e

versu s time if VI

=

5

The d iode s hown in the circ uit o f Figure P2 .15( a)

=

0.7 V

a nd

Tf

=

10 D . (a)

Plot Va

versus

ters

trian gul a r wave . s how n in Figu re P2. 15( b) , is applied, plot th e o ut put vers us t ime .

VI for -30

.s

VI

S

30 V . (b)

+

I ' U

-

R = 2.2 U2

"/~

;:

1

---l +

0 -==-- :2 V

I

Figure P2.14

"~

R = 100n 30 V
"
-=-
10 V
I
­

(a)

(b)

Figure P2.15

\

\

I