University of Toronto

Final Exam
Date - Dec 16, 2013
Duration: 2.5 hrs
ECE331 Electronic Circuits
Lecturer - D. Johns
ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY
1.

Equation sheet is on last page of test.

2.

Unless otherwise stated, use transistor parameters on equation sheet and assume g m r o 1 .

3.

Non-programmable calculator allowed; No other aids allowed

4.

Grading indicated by [ ]. Attempt all questions since a blank answer will certainly get 0.

Question

Mark

1
2
3
4

Last Name:

5
6

First Name:

Total

(max grade = 36)

Student #:

page 1 of 10

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[6] Question 1: Consider the circuit below where all transistors are in the active region. The
numbers beside the transistors indicate the transistor width (in m ).
V DD = 3V
All L = 0.18m
RS
vs
8
10k
vo
20A
1

a) Find the small-signal gain v o v s

vo vs =

b) Estimate the 3db frequency cutoff, f 3dB . For C db values assume V db = 0 .

f 3dB =

page 2 of 10

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[6] Question 2:
3 n V ov
- assuming C gs C gd and the overlap coma) For a Mosfet transistor, show that f t ----------------2
4L
ponent of C gs is negligibly small.

b) Consider the circuit below, only consider the capacitors C gs and C gd .

V DD

R D = 50k
RS
vs

vo

v1

for each transistor

g m = 1 mA/V
C gs = C gd = 1 pF
ro

200k
V SS

Find the pole due to the node v 1 and also find the pole due to the node v o .
p1 =
p2 =

page 3 of 10

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[6] Question 3: Consider the transistor below where it is biased such that V ov = 0.2V . Including
the effects of C gs and C gd , find the frequency, f 45 , where the impedance has a phase angle

of 45 (in Hz). Ignore r o .

Z i(s)

V ov = 0.2V
W = 3um
L = 0.3um
ro

page 4 of 10

f 45 =

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[6] Question 4: Consider the circuit shown below.

g m1 = g m2 = 100uA/V
A cl v O i S
V DD
r o1 = r o2 = 100k
R f = 100k
M2
R in
Rf
vO
Hint: transconductance gm1 is parallel to gm2
iS

M 1 R out

a) Find L , A and d .
L =
A =
d =

page 5 of 10

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b) Find v o i s , R in and R out .

vo is =

R in =
R out =

page 6 of 10

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[6] Question 5: Assume the loop gain for a feedback system is found to be the following.
4

1
6
9
5 10
L(s) = ----------------------------------------------------------------------------------------where p1 = 10 , p2 = 10 , p3 = 10 .
( 1 + s p1 ) ( 1 + s p2 ) ( 1 + s p3 )
a) Sketch the Bode plot for the above loop gain (both mag and phase)
Mag

Phase

page 7 of 10

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b) Estimate the phase-margin (PM) for the above loop gain. Hint, the unity gain freq is much
greater than p1 and much less than p3 .
PM =

c) Estimate the time-constant for the settling behaviour of this feedback system (assuming it
can be modeled as a first-order system).
=

page 8 of 10

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[6] Question 6: Consider a class AB BJT output stage shown below. Assume transistors Q n and
Q p are matched with I s = 10
amplitude of 10V.

13

A , is large, and the output is sinusoidal with a maximum

Assume V T = 25mV

+12V
V BB
vS

Qn

vO
Qp

R L = 50

12V
a) Find the value of V BB such that the quiescent current is 5% of the maximum load current.
V BB =

b) For an output voltage of -5V , estimate i n , i p , and v S .

in =
ip =
vS =

page 9 of 10

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Analog Electronics
23

Equation Sheet

19

Constants: k = 1.38 10
JK ; q = 1.602 10
C ; V T = kT q 26mV at 300 K ;
12
F/m ; k ox = 3.9 ; C ox = ( k ox 0 ) t ox
0 = 8.854 10
NMOS: k n = n C ox ( W L ) ; V tn > 0 ; v DS 0 ; v ov = v GS V tn
2
(triode) v DS v ov (or v D < v G V tn ) ; i D = k n ( ( v ov )v DS ( v DS 2 ) )
(active) v DS v ov ;

; g m = k n V ov = 2I D V ov =

i D = 0.5k n v ov ( 1 + v DS )

2k n I D ; r s = 1 g m ; r o = L ( I D )

PMOS: k p = p C ox ( W L ) ; V tp < 0 ; v SD 0 ; v ov = v SG V tp
2
(triode) v SD v ov (or ( v D > v G + V tp )) ; i D = k p ( ( v ov )v SD ( v SD 2 ) )
2

; g m = k p V ov = 2I D V ov =

(active) v DS v ov ; i D = 0.5k p v ov ( 1 + v SD )
( v BE VT )

2k p I D ; r s = 1 g m ; r o = L ( I D )

( 1 + ( v CE V A ) ) ; g m = r e = I C V T ; r e = V T I E ; r = g m ; r o = V A I C
(active) i C = I S e
=
( + 1 )i B ; = ( + 1 ) ; i C = i E ; R b = ( + 1 ) ( r e + R E ) ; R e = ( R B + r ) ( + 1 )
i
;
i C = i B E
vo
R x 1 gm + R D ( gm ro )
R x ( 1 + g m R S )r o
v
Cascode: i
v o v i g m ( r o || R D )
v
1
R D v oc v i
RD
i sc ( 1 g m + R S ) v i i
RS
vi
( Approx due to g m r o 1 )
Diff Pair: A d = g m R D ; A CM = ( R D ( 2R SS ) ) ( ( R D ) R D ) ; A CM = ( R D ( 2R SS ) ) ( ( g m ) g m )
BJT:

V os = V t ; V os = ( V ov 2 ) ( ( R D ) R D ) ; V os = ( V ov 2 ) ( ( ( W L ) ) ( W L ) )
AM
t
step response y(t) = Y ( Y Y 0+ )e
unity gain freq for T ( s ) = --------------------------1st order:
1 + s 3dB
( 1 + s z 1 ) ( 1 + s z 2 ) ( 1 + s z m )
for real axis poles/zeros T ( s ) = k dc ---------------------------------------------------------------------------------------Freq:
( 1 + s 1 ) ( 1 + s 2 ) ( 1 + s n )
OTC estimate f H = 1 ( 2 i ) ;
dominant pole estimate f H = 1 ( 2 max )
Miller:

Z1 = Z ( 1 K ) ;

f t A M 3dB when A M 1

Z2 = Z ( 1 1 K )

Mos caps: C gs = ( 2 3 )WLC ox + WL ov C ox ; C gd = WL ov C ox ; C db = C db0 ( 1 + V db V 0 )

2
f t = g m ( 2 ( C gs + C gd ) ) assuming C gd C gs f t = ( 3V ov ) ( 4L )
Feedback: A = A ( 1 + A ) ; x = ( 1 ( 1 + A ) )x ; dA A = ( 1 ( 1 + A ) )dA A ; Hf = H ( 1 + A ) ; Lf = L ( 1 + A )
i

Loop Gain L s r s t ; A f = A ( L ( 1 + L ) ) + d ( 1 + L ) ; Z port = Z 0 ( ( 1 + L S ) ( 1 + L O ) )

P
PM = L(j 1) + 180 ; GM = L(j 180) dB
Pole Splitting p1 1 ( g m R 2 C f R 1 ) ; p2 ( g m C f ) ( C 1 C 2 + C f ( C 1 + C 2 ) )
2
2
s + ( o Q )s + o = 0 ; Q 0.5 real poles ; Q > 1 2 freq resp peaking
2
2

Power Amps: Class A: = ( 1 4 ) ( V o ( IR L ) ) ( V o V CC ) Class B: = ( 4 ) ( V o V CC ) ; P DN_max = V CC ( R L )

2
Class AB: i n i p = I Q
2-stage cmos opamp: p1 ( 1 ( R 1 G m2 R 2 C c ) ); p2 ( G m2 C 2 ) ; z ( 1 ( C c ( ( 1 G m2 ) R ) ) )

SR = I C c = t V ov1 ; will not SR limit if t V o < SR

Pole Pair:

MOS Transistor; CMOS basic parameters. Channel length = 0.18m

Vt
(V)

C ox

( A V ) ( m/V )
2

( fF m )

t ox
( nm )

L ov
( m )

C db0
---------W
fF-
------ m

C ox
2

NMOS

0.4

240

0.05

8.5

0.04

0.3

PMOS

-0.4

60

-0.05

8.5

0.02

0.3

page 10 of 10