NOISE IN DEVICES AND CIRCUITS

Effects of body biasing on the low frequency noise of

MOSFETs from a 130 nm CMOS technology
M. Marin, M.J. Deen, M. de Murcia, P. Llinares and J.C. Vildeuil
Abstract: The impact of body biasing on the low frequency noise (LFN) performances of MOS
transistors from a 130 nm CMOS technology was investigated. The body-to-source voltage VBS
was varied from 0.5 V to +0.5 V for reverse and forward mode substrate biasing. Detailed
electrical characterisation was performed and the benets of the body bias analysed in terms of
current and maximum transconductance variations. Noise measurements were rst performed at
low drain bias VDS=725 mV and VBS=0 V in order to discuss the noise origin in the devices.
Results are in agreement with the carrier number uctuation theory DN for NMOS and with the
correlated carrier numbermobility DNDm model for PMOS. Bulk bias dependence of the LFN
was investigated at VDS=VDD=71.2 V. Signicant noise reduction of about 50% in both N and
PMOSFETS was observed in the weak inversion regime when applying a forward body bias. In
strong inversion, the noise level was found to be approximately independent of the substrate bias
VBS. An explanation of the main noise results based on McWhorters number uctuation theory is
proposed.

Introduction

The demand for low-voltage, low-power electronics has

grown rapidly due to the development of portable
electronics such as cell phones with single battery operation
and laptops. If the dynamic power consumption of CMOS
circuits can be directly reduced by scaling the supply voltage
VDD (PdynpV2DD), then the threshold voltage must be
scaled accordingly (VTBVDD/3) so as not to degrade circuit
speed or operating logic noise margins. On the other hand,
VT scaling is limited by the off-state current and static
power consumption constraints. To circumvent this issue,
new schemes such as the dynamic threshold voltage
MOSFET [1, 2] (DTMOS) or the gated lateral bipolar
junction transistors (G-LBJTs) [3] using the bulk terminal as
an active electrode, have been introduced for low-voltage
applications. A constant substrate biasing technique can
also be used with a standard CMOS architecture to improve
MOSFET performance. Indeed, forward body biasing
reduces the threshold voltage VT and thus increases the
device speed, whereas reverse body biasing can be used to
control the off-state leakage current for low power
applications where static power dissipation is a major
concern [4].
The body bias is also used in analogue integrated circuits
such as current mirrors or VCOs to ne-tune transistor
characteristics. For example, forward and reverse substrate
biasing has recently been used to control oscillation

frequency, power dissipation and phase noise in a CMOS

oscillator [57]. An important feature of the oscillator was
that it had two control voltages for the oscillation
frequency, the supply voltage which was used as a coarse
control and the substrate voltage as a ne control for the
oscillation frequency.
Concerning the low frequency noise performance, the
impact of biasing the substrate has not been widely studied
[8, 9]. In this contribution, we rst present the current
voltage and transconductance characteristics at various VBS
to illustrate the benets of body biasing. Two important
consequences of body biasing are the ability to change the
threshold voltage and transconductance [4, 10]. Both
parameters have a profound impact on the dc, noise and
ac performance of the MOSFET and MOS-based circuits.
In this paper, we extend the work of [11].
2

2.1

Experiments

Devices studied

The devices used in this study were isolated N and

PMOSFETs fabricated using a standard 130 nm CMOS
process. The MOS transistors used dual polysilicon gates.
The gate oxide thickness tox 1.7 nm and shallow trench
isolation was used. These devices were designed for
operation at a nominal supply voltage VDD 71.2 V. A
constant gate width W 10 mm, and various mask gate
lengths Lm 10, 0.8 and 0.2 mm were available. The devices
were provided by STMicroelectronics-Crolles, France.

r IEE, 2004

2.2

IEE Proceedings online no. 20040509

doi:10.1049/ip-cds:20040509
Paper rst received 20th June and in revised form 24th September 2003
M. Marin, P. Llinares and J.C. Vildeuil are with STMicroelectronics, 38926
Crolles cedex, France. M. Marin is also with CEM2, Universite Montpellier II
M.J. Deen and M. de Murcia are with CEM2, Universit!e Montpellier II, 34095
Monptellier cedex 5, France. M.J. Deen is also with the Electrical and
Computer Engineering Dept., McMaster University, Hamilton, Ontario,
Canada

The DC characteristics were measured using the HP4142A

semiconductor parameter analyser. Noise measurements
were performed on-wafer in a shielded probe station. The
DUT was biased using batteries and the drain current noise
amplied with an ultralow noise current amplier (transresistance amplier) EG&G 5182 or a low-noise voltage
amplier EG&G 5003, depending on the operating regime
of the transistor. Both congurations are schematically

IEE Proc.-Circuits Devices Syst., Vol. 151, No. 2, April 2004

Experimental set-up

95

104
105

VBS = + 0.5 V

106
107
IDS, A

shown in Figs. 1 and 2 respectively. Drain current noise

power spectral density (PSD) was measured using an
HP3562A dynamic signal analyser in the frequency range
1 Hz100 kHz. The experimental setup is controlled by a
HP workstation. For the range of biasing currents studied,
both setups gave almost identical results.

VBS = 0.5 V

108
109

VD

1010

LN current
amplifier

NMOS
at VDS = 25 mV

1011

DUT

1012
0

0.2

0.4

0.6
0.8
VGS, V
a

VG
HP3562A

1.0

1.2

1.4

105
VBS = 0.5 V

106
107

Fig. 1 Noise measurement setup using a low-noise current

amplifier (EG&G 5182)
VD

IDS, A

biasing system

VBS = +0.5 V

108
109
1010

PMOS
at VDS = 25 mV

1011

Rp
HP3562A

1012
0

0.2

AV

0.4

0.6
0.8
VGS, V
b

1.0

1.2

1.4

Fig. 3 Drain current IDS against gate voltage VGS characteristics

as a function of substrate bias VBS from +0.5 V to 0.5 V in steps of
0.25 V

VG

DUT

LN voltage
amplifier

(W/L 10/10)
a NMOS
b PMOS

biasing system

Fig. 2 Noise measurement setup using a low-noise voltage

amplifier (EG&G 5003)

3.1

DC characterisation

IV characteristics

Typical measured IDS(VGS) and gm(VGS) characteristics are

shown in Figs. 3 and 4, respectively. The body-to-source
voltage VBS was varied from +0.5 V to 0.5 V in steps of
0.25 V. These characteristics are plotted for a W/L 10 mm/
10 mm transistor in the linear regime of operation at
VDS 725 mV. Figure 3 illustrates the subthreshold
characteristics and threshold voltage variations due to the
body bias effect [4, 9]. Reverse substrate biasing increases
the threshold voltage and produces a signicant reduction
in the off-state current at VGS 0 V. Inversely, a forward
body bias results in a decrease in VT and an increase in the
on-state current.
Variation of the transconductance gm as a function of
VBS is shown in Fig. 4. One can observe that the
transconductance peak value is dependent on VBS.
Figure 4 also shows that most of the transconductance
improvement occurs at VGSB70.2 to 0.3 V, which is close
to the threshold voltage value. This improvement in gm has
signicant implications for low-voltage, low-power analogue circuits where VBS biasing close to VT is actively
researched.
96

To illustrate one of these implications, we look at the

results in Fig 4. For example, at VGSB70.28 V,
gm(NMOS) changes from B0.8 mS (VBS 0.5 V) to
B10.4 mS (VBS +0.5 V) while gm(PMOS) changes from
B0.4 mS (VBS +0.5 V) to B2.7 mS (VBS 0.5 V). That
is, for a change in VBS of 1 V, gm (NMOS) changes by 12
times and gm(PMOS) changes by 7 times for these two sets
of transistors. These large changes in gm at low VGS have
signicant implications for operating parameters such as
switching speed, unity current gain frequency and noise in
low-voltage, low-power integrated circuits.
Figure 5 shows the variations of the maximum
transconductance change Dgm.max as a function of the
substrate bias VBS and gate length Lm at VDS 725 mV.
Dgm.max is dened as
Dgm;max VBS

gm;max VBS  gm;max VBS 0V

gm;max VBS 0V

For the two longest devices (Lm 10 and 0.8 mm), the
maximum transconductance is enhanced when applying a
forward substrate bias VBS, while it is degraded in the case
of a reverse body bias. This behaviour can be explained by
considering that the effective mobility of the carriers is
degraded by enhancement of the effective transverse electric
IEE Proc.-Circuits Devices Syst., Vol. 151, No. 2, April 2004

14

15
gm,max /gm,max (VBS = 0), %

VBS = +0.5 V

12
10
gm, S

8
VBS = 0.5 V

6
4

NMOS

2
0

0.2

0.4

0.6
0.8
VGS, V

1.0

1.2

NMOS

5
0
5
VBS = 0.5 V (reverse)
10

at VDS = 25 mV
0

10

VBS = + 0.5 V (forward)

15
101

1.4

100

101

102

Lmask, m

3.5
VBS = 0.5 V

3.0

20
gm,max /gm,max (VBS = 0), %

PMOS

gm, S

2.5
2.0
VBS = + 0.5 V
1.5
1.0
PMOS
at VDS = 25mV

0.5

10

10
VBS = 0.5 V (forward)
VBS = 0.5 V (reverse)

20
0
0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

101

VGS, V

100

Fig. 4 Transconductance gm against gate voltage VGS characteristics as a function of the substrate bias VBS from +0.5 V to 0.5 V
in steps of 0.25 V
(W/L 10/10)
a NMOS
b PMOS

eld. Depending on the body bias polarity, the magnitude

of the transverse eld is increased or decreased, thus
changing the mobility and hence the transconductance. The
maximum transconductance of the shortest transistor
(Lm 0.2 mm) shows a weaker VBS dependence. This
behaviour has previously been explained with the help of
numerical simulations [12, 13]. In fact, for short channel
devices, one has to consider the dependence of the quasiFermi level gradient on the substrate bias. This phenomenon compensates the mobility variations and takes over at
a critical gate length that depends on the substrate doping
level.

3.2

101

102

Lmask, m
b

Fig. 5 Variations of the maximum transconductance gm,max with

substrate bias VBS and gate length Lm at VDS 725 mV
a NMOS
b PMOS

Table 1: Conduction parameters NMOS/PMOS (CMOS

130 nm technology)
W/L (mm)

10/10

10/0.8

10/0.2

VT (V)

0.26/0.27

0.34/0.29

0.45/0.33

mo (cm2/Vs)

298/70

y (V1)

0.47/0.74

DL (mm)

0.06/0.036

Racc (O.mm)
S (mV/dec) at
VDS 725 mV

110/420
75/71

74/71

78/74

Conduction parameters

The main conduction parameters were extracted in the

linear region from a set of IDSVGS transfer characteristics
and gm(VGS) transconductance curves at VDS 725 mV
and VBS 0 V, using the method in [14]. These parameters
include the channel length reduction DL, the parasitic
resistances Racc in series with the intrinsic channel of the
transistor, the threshold voltage VT, the low eld mobility
mo, the mobility degradation factor y and the subthreshold
swing S. The values for N and PMOS devices are reported
in Table 1. The threshold voltage VT was found to increase
with reduction of the gate length Leff. This well-known VT
roll-up is attributed to pocket implants which induced a
non-uniform lateral doped channel. The large value of the
IEE Proc.-Circuits Devices Syst., Vol. 151, No. 2, April 2004

mobility degradation factor is consistent with the very thin

oxide tox 1.7 nm used for these transistors. The subthreshold swing S values were extracted at VDS 71.2 V from
the IDSVGS characteristics. The data are shown in Fig. 6
as a function of VBS and gate length Lm.
The subthreshold swing S is observed to increase from
reverse to forward body biasing. The swing factor
expression is given by


kT
CD Cit
ln 10 1
S
2
q
Cox
where CD is the depletion charge capacitance (that depends
on the depletion width xd) and Cit the interface charge
97

1013

100

1015

NMOS

95

Si (f ), A2/Hz

S, mV/dec

85

75

1025

0
VBS, V
a

0.2
0.4
forward

0.6

S, mV/dec

102

103

104

105

Fig. 7 Drain current noise spectral density Si(f) as a function of

the frequency at various drain current IDS for an NMOS device

PMOS

85

4.1 Noise results in linear regime at

VBS 0V

80
75
70

0.4
0.2
forward

0
VBS, V
b

0.2
0.4
reverse

0.6

Fig. 6 Variations of subthreshold slope S as a function of VBS at

VDS 71.2 V for various gate lengths
Lm 10 (), 0.8 (m) and 0.2 (~) mm
a NMOS
b PMOS

capacitance. As body bias is varied from reverse to forward

mode, the depletion width xd is reduced, resulting in an
increase in CD and hence an increase of S.
Noise characterisation

Low-frequency noise measurements were performed in the

1 Hz to 100 kHz frequency range. Figure 7 illustrates typical
spectra obtained at various drain currents IDS from weak to
strong inversion modes of operation, for an NMOSFET
with 0.8 mm gate length.
The low-frequency spectra are predominantly 1/f like for
almost all devices. It is noticed that at low IDS values and
higher frequencies, the noise spectra variation with
frequency deviates from 1/f due to the cut-off frequency
of the device-preamplier equivalent circuit. Moreover, it
should be mentioned that when drain current noise spectral
density SiD includes additional pronounced Lorentzian
spectra in the subthreshold regime or for small gate
area devices, the 1/f noise component was extracted
assuming that SiD f is a superposition of 1/f noise and
g-r or RTS noise (Lorentzian behaviour). The results
presented and discussed later are only for the 1/f noise
measured or extracted. All data are plotted at a frequency
f 1 Hz.
98

101

W/L 10/0.8 biased at VDS 1.2 V and VBS 0 V

90

65
0.6

1027
100

f, Hz

95

1021
1023

0.4
0.2
reverse

IDS

1019

80

70
0.6

1/f

1017

90

Noise measurements were rst performed at low drain bias

VDS 725 mV and at VBS 0 V in order to investigate the
physical origin of the uctuations. Figure 8 shows the
variations of the normalised drain current noise Si/I2DS as a
function of IDS from weak to strong inversion and in the
linear region for the different gate lengths. These plots are
usually made when studying the noise origin in MOSFETs
[13].
For the NMOS devices, the normalised noise level is
found to level off in weak inversion and decrease as I2
DS in
strong inversion. Moreover, good correlation is obtained
when comparing Si/I2DS variations with the ratio (gm/IDS)2.
This is in agreement with the carrier number uctuation
theory [13] DN since:
 2
Si
gm

S
3
Vfb
2
IDS
IDS
where SVfb is the at-band voltage spectral density given by
SVfb

q2 kT lNt EF
2
WLfCox

with l the attenuation coefcient of the electron/hole

wavefunction in the oxide (lE0.1 nm). The oxide trap
density Nt(EF) value has been extracted as
6  1017 eV1 cm3 from experiments.
Considering the PMOS transistor results, the relative
noise Si/I2DS saturates in weak inversion and then decreases
2
as I1
DS in strong inversion. Si/IDS is not correlated with the
2
(gm/IDS) variations, and moreover, the input-referred noise
voltage gives rise to a parabolic dependence with gate
voltage VGS. In this case, it is shown [15] that the
normalised noise Si/I2DS variations with IDS agree with the
correlated carrier numbermobility uctuation DNDm
model given by:

  
Si
IDS 2 gm 2
1  as mef Cox
SVfb
5
2
gm
IDS
IDS
where as is the Coulomb scattering coefcient. Its value is
found to be 2  105 Vs/C. It is noticed that the oxide trap
density NT(EF) value is similar to the previous one obtained
for the NMOSFETs. The average plateau value of Si/I2DS in
weak inversion at xed IDS current are reported in Fig. 9 as
a function of the effective gate length Leff. Correct scaling of
IEE Proc.-Circuits Devices Syst., Vol. 151, No. 2, April 2004

106

10

NMOS

109
1010
1011

NMOS

1012
109

108

107

106
IDS, A

105

104

10

Leff1

108

1Si /IDS22, 1/Hz

IDS2
(g m /IDS)2, a.u

SiD /IDS2, 1/Hz

107

10

10

103

10

10

10

10

a
107
10

PMOS
10

108

107

106
IDS, A

105

104

103

Leff1

109

1Si /IDS22, Hz1

108

(g m /IDS)2, a.u

SiD /IDS2, 1/Hz

~ IDS1

1010
109

10

Leff, m
a

10

10

10

10

2
Fig. 8 Variations of normalised drain current noise Si /IDS
against
drain current IDS at VDS 725 mV

Lm 10 (), 0.8 (m) and 0.2 (~) mm gate length devices

a NMOS
b PMOS

the normalised noise magnitude is obtained when compared

with the theoretical variation, that is, Si/I2DSpL1
eff
(see (4)).

4.2 Noise results in nonlinear regime as a

function of VBS
In order to study the effect of substrate biasing in the usual
operating regime of the transistor, noise measurements were
performed from weak to strong inversion in a deep
saturation regime at VDS 71.2 V. The body bias VBS
was varied from VBS 0.5 V to VBS +0.5 V. The upper
VBS limit value in the forward mode of operation was
chosen because at this substrate bias, the sourcesubstrate
ISB diode current as well as the drain current IDS at zero
VGS is still low, that is ISBo0.2 nA and IDSo10 nA.
However, further increases in VBS forward bias result in
signicant increases in IDS, making the static power
dissipation unacceptably high. Considering the weak
inversion region, the noise level for both N and PMOSFETs followed a quadratic variation with the drain current
IDS. Figure 10 shows the average plateau value of the
normalised noise level /Si/I2DSS at constant current
IDSE1 mA as a function of the substrate bias VBS and gate
length Leff.
A signicant noise level reduction of about 50% for all
devices is observed in this operating region when applying a
forward body bias whereas the noise is weakly impacted
with a reverse substrate bias. The noise expression [15] in
IEE Proc.-Circuits Devices Syst., Vol. 151, No. 2, April 2004

10

10

10

Leff, m
b
2
Fig. 9 Normalised drain current noise Si /IDS
in the subthreshold
regime against effective gate length Leff at IDSE1 mA and
VDS 725 mV

Lm 10 (), 0.8 (m) and 0.2 (~) mm

a NMOS
b PMOS

weak inversion is given by

Si
q4 lNt EF

2
IDS kTWLf Cox CD Cit 2

q2 lkTNt EF ln102
1
/ 2
2
2
S
WLfCox S

Following (6), the normalised drain current noise Si/I2DS

should be correlated with the variations of the swing factor
S with VBS. We have plotted in Fig. 11 the variations of the
normaliszed noise level Si/I2DS and the variations of 1/S2
with VBS for the longest (Lm 10 mm) and the shortest
(Lm 0.2 mm) devices. As shown, Si/I2DS and 1/S2 follow
similar trends with the substrate bias VBS and qualitative
agreement is observed. Nevertheless, it is noticed that the
noise level in the forward mode decreases faster than 1/S2
for the shortest gate length device, pointing out that
depletion charge capacitance variations with VBS cannot
fully account for the noise reduction experimentally
observed in this operating region.
Considering now the strong inversion regime, the LFN
results are plotted as a function of the drain current IDS and
body bias VBS for Lm 10, 0.8 and Lm 0.2 mm in Fig. 12
for NMOS and PMOS transistors, respectively. The noise
level is found to be clearly independent of the body bias at
xed IDS current. Moreover for the longest gate length
NMOSFET, SiDpIDS as it is predicted in deep saturation
99

10

10

1/S2, a.u

1Si /IDS22, Hz

1Si /IDS22, 1/Hz

Lm = 0.2 m

VBS = 0 V
VBS = + 0.5 V (forward)

NMOS

10

VBS = 0.5 V (reverse)

10

10

Lm = 10 m

10

(1)
10

NMOS
10

10

0.8

10

10

10

10

0.6 0.4
reverse

0.2

0.2

0.4
0.6
forward

VBS, V
a

10

0.8

Leff, m
a
7

10

Lm = 0.2 m

10

10

VBS = 0 V
VBS = + 0.5 V (reverse)

1/S2, a.u

1Si /IDS22, Hz

1Si /IDS22, 1/Hz

VBS = 0.5 V (forward)

10

Lm = 10 m
9

10

10

10
(1)

PMOS

10

10

10

0.8

0.6 0.4
forward

0.2

0
VBS, V

0.2

0.4
0.6
reverse

0.8

b
1

10

10

10

Leff, m
b

Fig. 10 Average plateau values of the normalised drain current

2
noise Si /IDS
in the subthreshold regime at VDS 71.2 V as a
function of the substrate bias VBS and gate length Leff
a NMOS
b PMOS

by DN model. For the longest PMOS device we nd

SiDpI3/2
DS at VDS4VGSVT.
Indeed, to understand physically the dependence observed of the LFN with VBS, we have to consider the
McWhorter approach where the noise source is suppose to
be due to the carrier number uctuation in our N and
PMOS devices. Considering the charge conservation
principle [16], a variation of the oxide charge dQox induces
a variation of the inversion charge dQinv given by:
Cinv
dQinv
dQox
7
Cox CD Cit  Cinv
where Cox, CD, Cit, Cinv are the oxide, depletion charge,
interface traps and inversion charge capacitance per unit
area respectively. In the weak inversion regime, assuming
that Cox+CD+Cit4Cinv, the uctuation in the amount of
trapped oxide charges dQox induced inversion carrier
uctuation dQinv, which shows a strong dependence on
VBS, as expected from (7).
In the strong inversion regime, the previous capacitance
ratio becomes almost unity (CinvcCox+CD+Cit). This
means that the uctuation in the oxide trapped charge is
fully correlated with uctuations in the inversion charge,
that is, dQinvEdQox. As the charge exchange with the
depletion layer becomes negligible in this region, the noise
level should not be affected by the substrate biasing VBS.
Some scattering with VBS is observed for the shortest
NMOS device Lm 0.2 mm. Extra noise measurements
100

PMOS

10

Fig. 11 Variations of
for Lm 10 and 0.2 mm

2
Si /IDS

and 1/S 2 with the substrate bias VBS

a NMOS
b PMOS

have been performed at VBS 0.25 V and +0.25 V in

order to discriminate between dispersion and some short
channel effects. As they show a similar level, the observed
variations are attributed to dispersion of the data and are
not interpreted as a body bias effect.
Other possibilities for explaining the improved lowfrequency noise characteristics in MOS devices with
forward body bias are now discussed. Forward body bias
increases the effective gate or lateral electric eld which in
turn lowers the semiconductor oxide barrier. This lowered
barrier result in a decreased attenuation coefcient l of the
carrier wave function in the oxide, thus decreasing SVfb (see
(4)) and Si/I2DS (see (3) and (5)). Another factor to be
considered is the number of carriers in the channel and how
this is affected by body bias. Since a forward body-source
bias decreases the threshold voltage in NMOS transistors,
then for the same gate voltage, the number of electrons in
the channel increases, resulting in reduced Coulombic
scattering due to the diminished scattering coefcient. With
diminished Coulombic scattering, the low-frequency noise
also decreases. Finally, in these thin oxide or short channel
devices, quantisation of the inversion layer and a peak
carrier density some distance (Bnm) from the inversion
layer most be considered. Both of these are dependent on
the effective gate bias that must include the body bias.
More details on these effects can be found in [17]
and [18].
5

Conclusions

The impact of forward and reverse substrate biasing on

low-frequency noise performances of N and PMOS
IEE Proc.-Circuits Devices Syst., Vol. 151, No. 2, April 2004

on p-type surface channel devices illustrate that the

correlated DNDm model is more suitable in all operating
regime to predict the 1/f noise behaviour. Possibilities for
explaining the low-frequency noise behaviour with body
bias were also discussed.

1012
1013
1014

Lm = 0.2 m

NMOS

Si , A2/Hz

1015
1016
1017

Lm = 0.8 m

1019

IDS

1020

Lm = 10 m

1021
1022
107

106

105

104
IDS, A
a

103

102

1013
1014

Lm = 0.2 m

PMOS

1015

1016
1017

Lm = 0.8 m

1018

IDS3/2

1019
1020

Lm = 10 m

1021
1022
107

106

105

104

The authors thank STMicroelectronics-Crolles, France, for

providing the samples. M. Marin thanks STMicroelectronics for funding and Dr V. Le-Goascoz for interest and
support. M.J. Deen thanks CNRS, France; Micronet,
Canada; and NSERC, Canada for support.
7

1012

Si , A2/Hz

Acknowledgments

1018

103

102

IDS, A
b

Fig. 12 Current noise spectral density Si versus drain current IDS

in strong inversion at VDS 71.2 V
VBS 0.5 V (m), 0 V (), + 0.5 V (,) for Lm 10, 0.8 and 0.2 mm
a NMOS
b PMOS

transistors in a 130 nm CMOS technology has been

investigated from weak to strong inversion modes of
operation. A detailed electrical characterisation was rst
performed and the main conduction parameters determined. Maximum transconductance gm,max were found to
be a complicated function of the substrate bias, and its
variation was interpreted considering the effective transverse
electric eld dependence of carrier mobility for long channel
devices. Noise measurements were performed at low drain
bias VDS 725 mV and VBS 0 V in order to investigate
the physical origin of the uctuations.
Noise level variations agree with the carrier number
uctuation theory DN for NMOS devices and with the DN
Dm model for PMOS devices. The oxide trap density Nt(EF)
was found to be 6  1017 eV1 cm3. Body bias effect has
been investigated at VDS VDD 71.2 V. A signicant
noise reduction of about 50% was observed in the
subthreshold regime when applying a forward body bias,
in agreement with depletion capacitance variations and
Reimbold theory based on the McWhorter model. In strong
inversion, the noise level was found to be independent of the
substrate bias VBS. In addition the measurements performed

IEE Proc.-Circuits Devices Syst., Vol. 151, No. 2, April 2004

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