Hey All,

These are few very simple and general ARM processor assignment questions.
Each question number means your roll number, solve questions as per your roll number.
Ex: Roll number 1: will soive question no. 1
Roll number 30: will soive question no. 30 & so on..

ARM Processor Assignment Questions

1. What are the types of CORTEX-M series ?
2. How do you select a specific CORTEX-M processor ?
3. What is pipelining, what are the types?
4. Explain the architecture of the CORTEX series ARM that you have used .
5. What is the use of the AMBA interface and where is it present in the architecture ?
6. For ARMv7-A memory management, which attribute control field is used in a
page table entry to control use of a page table with a given Address Space
IDentifier (ASID)?
A) AP (Access Permission)
B) nG (Not Global)
C) SH (Shared)
D) XN (Execute Never)
7. What is the significance of ! in a load/store instruction?
A) Dont update base register in post-indexed load/store
B) Dont update base register in pre-indexed load/store
C) Update base register in post-indexed load/store
D) Update base register in pre-indexed load/store
8. A cache that supports dirty bits to manage the most recently written value to
a given memory location in the memory hierarchy is referred to as a:
A) write-back cache.
B) write-through cache.
C) set-associative cache.
D) fully-associative cache.
9. The ARM processor registers R13, R14, and R15 are architecturally used for
special purposes. Which is the correct respective sequence of special purpose
registers?
A) PC, LR, SP

B) LR, PC, SP
C) SP, LR, PC
D) LR, SP, PC

10. When building code for a processor without floating point hardware, how
would the compiler deal with floating point calculations in the source code?
A) The compiler will produce code that results in calculations with less
accuracy
B) The compiler will produce an error and not compile
C) The compiler will use libraries to perform the floating point operations
with integer instructions
D) The compiler will warn the programmer that the code needs to be
rewritten using fixed-point arithmetic

11. When should i use '!' in ARM programming and where is it Not Allowed to be used in ARM
programming ?
12. Discuss 'Single Data Transfer' and 'Multiple Data Transfer' in ARM
13. How will you manually Enable / Disable an interrupt in ARM Processor ?
14. Discuss MRS and MSR instructions ?
15. Can you tell a 32-bit branch instruction and the way you used it ?
16. Write a program to mask bytes in ARM assembly ?
17. ARM7 family of processors does not use any branch prediction scheme. Neither
ARM9 nor ARM9E family implements branch prediction - True / False
18. The ARM11 micro-architecture uses two techniques to predict branches - True / False
19. What is Translation Lookaside Buffer (TLB) ?
20. What are the types of addressing modes in ARM ?
21. Can you brief up the evolution of ARM architecture ?
22. Why ARM7TDMI alone highlights the features that it supports in its naming and why not
other ARM architectures ?
23. When will you choose to use ARM and when will you choose to use Thumb instructions ?
24. Can you explain the operation of ARM7 pipeline for simple instructions ?
25. Can you tell about function performed by this instruction - ADD r3, r5, r12 ?
26. Tell about the Exception Handling in ARM processor. What does the ARM Core do
automatically for every exception ?
27. Can you tell about DSP in ARM7TDMI or DSP in STRONGARM or DSP in ARM9E ?
28. What is the use of 'SWI' in ARM assembly ?
29. How to Represent a Digital Signal in ARM ?
30. Give Example of STMFD w.r.t Stack Operation push/pop ?
31. Tell about Extended Multiply Instructions in ARM
32. Tell about the NORMAL Multiply Instructions in ARM
33. Tell about ADR's relation with LDR and the Advantage of using LDR together with '=' ?
34. When does the Processor Stall in ARM and what is the pipeline hazard in ARM?
35. What is called 'pipeline bubble' in ARM ?
36. What is Saturating Arithmetic ? Explain
37. What does the 'B' mean in LDRB or What is the difference between LDR and LDRB in ARM

?
38. What is the use of Write-Back ?
39. How will you flush the instuction Cache in ARM processor ?
45. List the issues when porting C code to the ARM processor ?
46. Write a program to mask bytes in ARM assembly ?
47. ARM7 family of processors does not use any branch prediction scheme. Neither
ARM9 nor ARM9E family implements branch prediction - True / False
48. The ARM11 micro-architecture uses two techniques to predict branches - True / False
49. What is Translation Lookaside Buffer (TLB) ?
50. What are the types of addressing modes in ARM ?
51. Can you brief up the evolution of ARM architecture ?
52. Why ARM7TDMI alone highlights the features that it supports in its naming and why not
other ARM architectures ?
53. When will you choose to use ARM and when will you choose to use Thumb instructions ?
54. explain the operation of ARM7 pipeline for simple instructions ?
55. explain function performed by this instruction - ADD r3, r5, r12 ?
56. Explain the architecture of the CORTEX series ARM that you have used .
57. What is the use of the AMBA interface and where is it present in the architecture ?
58. When should i use '!' in ARM programming and where is it Not Allowed to be used in ARM
programming ?
59.Tell about 'Single Data Transfer' and 'Multiple Data Transfer' in ARM
60. How will you manually Enable / Disable an interrupt in ARM Processor ?
61. What are the advantages of writing in Assembly in ARM processor?
62. Explain this -> "AREA |.text|, CODE, READONLY"
63. What is the use of the 'EXPORT' directive ?
64. What is the use of various directives ?
65. How to build using command line tools w.r.t ARM ?
66. Write a simple square.s program in ARM assembly called from a C file ?
67. What will you change that program when calling ARM code from C compiled as Thumb ?
68. How will you allow Thumb C code to call the ARM assembly Code ?
69. What is the use of 'RN' directive in ARM assembly ?
70. What imports the libraries like printf automatically in the assembly side of ARM ?
71. What is the DCB directive and its relation with strings ?
72. What is ARMulator ? Where and How have you used it ?
73. How will you handle the Register Shortage problem in ARM ?
74. Relation between CPSR flags, S Suffix Instructions and Comparison Instructions ?
75. What is Conditional Execution in ARM ?
76. What is single issue multiple data (SIMD) processing ?
77. What is a Coprorcessor / CP15 in ARM ?
78. Which of the following processors would be best suited to a system requiring
hard real-time responses, such as a hard drive controller?
A) ARM1136
B) Cortex-A5

C) Cortex-R4
D) Cortex-A9
79. Assume a control register has a value of 0xFECBCA56.
Which of the following actions is needed to set bit 3 of the control register
without changing other bits?
A) A Read-Modify-Write sequence of the control register
B) No operation is required since bit 3 is already 1
C) A bitwise AND of the control register value with 0x08
D) A Write-Modify-Read sequence of the control register
80. In a Cortex-A processor, which exception vector is located at the highest
memory address of the exception vector table?
A) Undefined Instruction
B) Data Abort
C) IRQ
D) FIQ
81. According to the ARM Architecture Procedure Call Standard (AAPCS), what is
the maximum number of arguments passed to a function to be considered most
efficient?
A) 4 Arguments
B) 6 Arguments
C) 8 Arguments
D) 16 Arguments
82. An ARM processor using a Generic Interrupt Controller (GIC) is servicing an
active interrupt I1 with a priority value 0x10, when a new interrupt I2, with a
priority value 0x0F, is received by the GIC. What action does the GIC take?
Assume that the number of priority levels implemented is 256, and the priority
mask for that processor interface is 0xFF.
A) I2 is forwarded to the processor
B) I2 is rejected and signalled to the sending peripheral
C) I2 is forwarded to another processor that is currently idle
D) I2 is held pending until I1 is completely serviced
83. Thumb-2 technology is implemented in which of the following?
A) All ARM processors
B) All ARMv7 processors
C) ARMv7-A processors only
D) ARMv7-A and ARMv7-R but not ARMv7-M
84. Which assembly instruction would you use to load 4 words starting from the
memory location 0x80000000 into the registers r0-r3?

(Assume r9 contains the base address 0x80000000)

A) LDMDB r9, {r0-r3}
B) LDMIA r9, {r0-r3}
C) LDMIB r9, {r0-r3}
D) LDMDA r9, {r0-r3}
85. The ARM processor registers R13, R14, and R15 are architecturally used for
special purposes. Which is the correct respective sequence of special purpose
registers?
A) PC, LR, SP
B) LR, PC, SP
C) SP, LR, PC
D) LR, SP, PC
86. When building code for both ARM and Thumb states, which tool decides for
each function call whether to use a BL or BLX instruction?
A) The linker
B) The archiver
C) The compiler
D) The assembler
87. When building code for a processor without floating point hardware, how
would the compiler deal with floating point calculations in the source code?
A) The compiler will produce code that results in calculations with less
accuracy
B) The compiler will produce an error and not compile
C) The compiler will use libraries to perform the floating point operations
with integer instructions
D) The compiler will warn the programmer that the code needs to be
rewritten using fixed-point arithmetic
88. Which one of the following statements is TRUE for hardware breakpoints?
A) Hardware breakpoints utilize the BPKT instruction on ARM processors
B) Hardware breakpoints are not suitable for debugging exception
handlers
C) Hardware breakpoints can be used to debug code running from readonly memory
D) Cache maintenance operations may be required when placing a
hardware breakpoint
89. Address Contents
0x24 0x06
0x25 0xFC
0x26 0x03
0x27 0xFF
If r0 has the value 0x24, what is the content of r12 after executing the
following instruction?
LDRB r12, [r0], #2
A) 0xFC
B) 0x03
C) 0x06

D) 0xFF
90. Which of the following provides fastest access for the processor?
A) Tightly Coupled Memory (TCM)
B) Hard disk
C) Onboard flash memory
D) Register File