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IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 15, NO. 1, JANUARY 2000

Three-Phase Short Circuit Testing of High-Voltage

Circuit Breakers Using Synthetic Circuits
Denis Dufournet, Member, IEEE, and Georges Montillet, Member, IEEE

AbstractHigh-voltage circuit-breakers have reached such high

short-circuit breaking capabilities that they must be tested in synthetic circuits with separate current and voltage sources. As the
main performance to be verified by type tests is the interruption
of three-phase faults, it is desirable whenever possible to perform
three-phase tests. Three-phase synthetic testing is rather new and
not covered by ANSI/IEEE and IEC standards. The purpose of this
paper is to present a procedure for three-phase synthetic testing
which can properly test the circuit-breaker at a reasonable cost,
i.e., a number of tests using a limited number of circuit-breaker
specimen for the entire series of type tests.
Index TermsCircuit-breaker, synthetic, testing.
Fig. 1.

Synthetic test circuit.

I. INTRODUCTION

NTERNATIONAL standards such as IEC and ANSI/IEEE

require that the performance of high-voltage circuit-breakers
must be demonstrated by type tests for all currents ranging from
its rated continuous current to 100% of its breaking capability
under short-circuit conditions (Isc) [1], [2]. At the present time
the performance of high-voltage circuit-breakers are so high that
verification of their short-circuit interrupting capability under
the full rated voltage is generally not possible with direct tests
circuits where one source delivers the required current under
the specified voltage. Even the most powerful test laboratories,
with three-phase short circuit power of about 6000 MVA, do not
have the capacity to test properly a three-phase 145 kV circuitbreaker with a short-circuit current exceeding 25 kA. It is then
necessary to use synthetic circuits where current and voltage
are delivered by separate sources. These synthetic test circuits,
used for terminal fault interruption, are described in ANSI/IEEE
guide C37-081 and IEC guide 427 [3], [4].
Under certain conditions standards allow tests to be performed on a single phase, or even on one unit of one pole of
a circuit-breaker.
But as single-phase tests aim to demonstrate the interruption
of all three phases in a single operation, they are more severe
than in the real situation where the highest recovery voltage is
applied only on the first pole to clear.
Moreover, the correct current and voltage stresses should be
applied on all phases in order to reproduce the real conditions
of a three-phase interruption. This is of particular importance
for those circuit-breakers which have their three poles in the
same enclosure and a common mechanism. It is then desirable
to perform three-phase short-circuit tests.
Manuscript received August 11, 1998.
D. Dufournet is with ALSTOM, Villeurbanne, France.
G. Montillet is with ALSTOM, Charleroi, PA USA.
Publisher Item Identifier S 0885-8977(00)00577-X.

Standards require that interruption of 100% of Isc be made by

two test duties. One test duty (T100s or TD4) is performed with
a symmetrical current, while the other test duty (T100a or TD5)
is done with an asymmetrical current which is the sum of an ac
component and a dc component decreasing with a time constant
of 45 ms.
While three-phase testing under symmetrical conditions is
well established (see Section II), testing of asymmetrical current interruption has still to be properly defined. The aim of
this paper is to present a test procedure for three-phase synthetic testing with asymmetrical short-circuit currents. It is the
authors opinion that such tests must give a reasonable confidence to the user on the circuit-breaker performance, but at the
same time they must be done at a reasonable cost, i.e., without
requiring an excessive number of tests, and in such a way that
only one circuit-breaker specimen is necessary. In the future IEC
56 will limit the number of test specimens to one or two (depending on the type of equipment and the type of tests). It is then
essential to define a test procedure for synthetic tests which is
compatible with this requirement.
II. THREE-PHASE SYNTHETIC TESTS WITH SYMMETRICAL
CURRENT
As shown on Fig. 1, a synthetic test circuit has separate
sources of current and voltage.
The arcing time, or period between contact separation and arc
extinction at current zero, is chosen before the test. The arc is
fed by the high current source and at the chosen current zero
instant the recovery voltage is applied by the voltage source.
This principle is commonly applied for single-phase testing,
it is now also applied for three-phase testing using a three-phase
source and generally two voltage sources, one provides the recovery voltage of the first pole to clear and the other gives the
recovery voltage of the second and third pole to clear.

08858977/00$10.00 2000 IEEE

DUFOURNET AND MONTILLET: THREE-PHASE SHORT CIRCUIT TESTING OF HIGH-VOLTAGE CIRCUIT BREAKERS USING SYNTHETIC CIRCUITS

Three-phase synthetic circuits, including the one shown in

Fig. 1, are described in IEC guide 1633 [5].
In the case of symmetrical current interruption (test duty
T100s of IEC or TD4 of ANSI), the definition of the arcing
time is rather easy. As current zeros are occuring every 60 el.
on one phase or another (Fig. 2), it is sufficient to check the
performance of the circuit-breaker with a range of arcing times
for the first pole to clear of 60 el. minus , being a slight
delay of contact separation that can be met in test laboratory.
In the future edition of IEC standard 56 the time interval is
defined as 18 el.
It follows that contact separation shall be such that arcing
times for the first pole to clear are comprised between a short
value tmsym, at least equal to the minimum arcing time, and a
longest value tmsym + 60 el. 18 el. = tmsym + 42 el.
IEC standards require tmsym to be the minimum arcing time
and that this value must be checked, by as many tests as necessary, by varying the instant of contact separation by 18 el.
ANSI/IEEE has a more pragmatic approach which limits the
number of tests and requires the choice of a short arcing time
(tmsym) and then the demonstration of the required interrupting
window of 42 el. In this way the long arcing time is at least
equal to the longest one which would be obtained in a threephase direct test so that the more severe condition is covered
with a reduced number of tests.
As both IEC and ANSI/IEEE standards require three
breaking operations with short, long, and medium arcing times,
they should be done with arcing times which are defined as
follows:
a) First test with arcing time for the first pole to clear =
tmsym.
b) Second test with arcing time for the first pole to clear =
tmsym + 420 el.
c) Third test with arcing time for the first pole to clear =
tmsym + 21 el.

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Fig. 2. Three-phase symmetrical current interruption.

Fig. 3. Asymmetrical currents during 3-phase short-circuit interruption of 40

kA60 Hz by 2-cycle circuit-breaker with kpp = 1.3. Interruption of the first
pole to clear after a major loop. Case a).

III. THREE-PHASE SYNTHETIC TESTS WITH ASYMMETRICAL

CURRENT
The definition of a test procedure for asymmetrical current is
more complicated than in the previous case as, on one hand,
interruption can occur after a minor loop or a major loop of
current and, on the other hand, the type of neutral grounding
must be considered.
In principle two types of neutral grounding must be taken into
account:
Solidly Grounded Neutral: General case considered in
the revised ANSI standard C37-04 (1999) reflecting the
present situation of North American networks. In this
case the first pole to clear factor (kpp) is equal to 1.3.
Isolated or Impedance-Earthed NeutralPedersen Coil:
Particular case of some networks, mostly European. In this
case the first pole to clear factor (kpp) is equal to 1.5.
The main purpose of tests duties with asymmetrical currents
at the rated breaking short-circuit current value is to demonstrate
that the circuit-breaker can interrupt in the two most severe conditions:

Fig. 4. Asymmetrical currents during 3-phase short-circuit interruption of 40

kA60 Hz by 3-cycle circuit-breaker with kpp = 1.3. Interruption of the first
pole to clear after a major loop. Case a).

i) Interruption by the first pole to clear after a major loop

with the required percentage of the dc component. In this
case the circuit-breaker must withstand the highest transient recovery peak (slightly reduced by current asymmetry, see IEEE Guide C37-08la-1997 [6]).

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IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 15, NO. 1, JANUARY 2000

ii) Interruption by one of the last poles to clear after a major

extended loop with the required percentage of the dc component. This test is intended to prove that the circuitbreaker can interrupt when one pole has the highest arc
energy content during the last current loop. As this condition occurs for one of the last poles to clear, the transient
recovery voltage is lower than in test condition i).
In all that follows interruption is required after a major loop
(or major extended loop) of current but for those circuit-breakers
which cannot do so due to their interrupting technique, it is allowed to have interruption after the subsequent minor loop.
In accordance with IEC and ANSI/IEEE standards, a major
or a minor loop of current will be considered to be symmetrical
when the percentage dc component is lower than 20%. For these
situations the minimum arcing time is assumed to be the same as
the one obtained during tests duties T100s (IEC) or TD4 (ANSI)
with symmetrical currents, i.e., equal to tmsym as defined in
Section II.
In addition it is the authors experience with many circuit-breakers (SF6 puffer or self blast type) that the minimum
arcing time obtained after a minor loop is generally very close
to tmsym.
The study of a test procedure for asymmetrical currents is detailed hereafter for the general case of networks with grounded
neutral (first pole to clear factor equal to 1.3) and with the stan= 17
dard value of the network time constant (45 ms or
at 60 Hz). It is made by simulating three-phase asymmetrical
short-circuit current interruption using the SABER software.
The most general possible cases are taken into account, deviations in particular cases are possible but should not be considered when defining a basic standard specification. A standard
should not be a catalog of all possible cases, it should only cover
about 9095% of cases.
The computations are done for a power frequency of 60 Hz,
but as results are given in electrical degrees this study is also
applicable to other frequencies (50 Hz in particular).
A. Three-Phase Interruption of Asymmetrical Currents in
Grounded Neutral Networks
Condition i): Interruption by the first pole to clear after a
major loop with the required percentage of the dc component.
Two cases are possible:
Case a: The minimum arcing time of the first pole to clear
after a major loop is lower than the minimum arcing time tmsym
(of T100s or TD4) plus 72 el. (2 cycle circuit-breaker) or 64
el. (3 cycle circuit-breaker).
This case is illustrated by Figs. 3 and 4.
One pole fails to interrupt after a symmetrical loop (dc component <20%), and the next pole then clears as a first pole to
clear after a major loop with the following longest arcing times
(tmxasym):
tmxasym
tmxasym

tmsym + 60 el. (for 2 cycle circuit-breakers)

tmsym + 54 el. (for 3 cycle circuit-breakers)

This is considered to be the more general case.

Figs. 5 and 6 show, respectively, the transient recovery
voltage on each pole for 2- and 3-cycle circuit-breakers.

Fig. 5. Transient recovery voltages during 3-phase short-circuit interruption

of 40 kA60 Hz by 2-cycle circuit-breaker with kpp = 1.3. Interruption of the
first pole to clear after a major loop.

Fig. 6. Transient recovery voltages during 3-phase short-circuit interruption

of 40 kA60 Hz by 3-cycle, circuit-breaker with kpp = 1.3. Interruption of the
first pole to clear after a major loop.

For a 2-cycle circuit-breaker, the TRV peak on the first pole

to clear is reduced by a factor 0.87 (186.7/213.2), due to current
asymmetry. It is consistent with the value given in the IEEE
Guide [6]. The dc component for the first pole to clear is about
67%.
For a 3-cycle circuit-breaker the TRV peak on the first pole
to clear is reduced by a factor 0.94.
Case b: The minimum arcing time of the first pole to
clear after a major loop is higher than the minimum arcing time
tmsym (of T100s or TD4) plus 72 el. (2 cycle circuit-breaker)
or 64 el. (3 cycle circuit-breaker).
This case is illustrated by Figs. 7 and 8.
One pole fails to interrupt after a symmetrical loop (minor
loop but with dc component <20%), the next one does not interrupt after a major loop (with dc component less than rated) and
the first phase to clear does so after a major loop with rated dc
component and the following longest arcing:
tmxasym

tmsym + 142 el.

tmxasym

(for 2 cycle circuit breakers)

tmsym + 129 el.
(for 3 cycle circuit-breakers)

DUFOURNET AND MONTILLET: THREE-PHASE SHORT CIRCUIT TESTING OF HIGH-VOLTAGE CIRCUIT BREAKERS USING SYNTHETIC CIRCUITS

Fig. 7. Asymmetrical currents during 3-phase short-circuit interruption of 40

kA60 Hz by 2-cycle circuit-breaker with kpp = 1.3. Interruption of the first
pole to clear after a major loop. Case b).

145

Fig. 9. Asymmetrical currents during 3-phase short-circuit interruption 40

kA60 Hz by 2-cycle circuit-breaker with kpp = 1.3. Interruption after a major
extended loop by the second pole to clear.

Fig. 8. Asymmetrical currents during 3-phase short-circuit interruption 40

kA60 Hz by 3-cycle circuit-breaker with kpp = 1.3. Interruption of the first
pole to clear after a major loop. Case b).

This case is less likely than case a).

Condition ii): Interruption by one of the last pole to clear
after a major extended loop with the required percentage of the
dc component.
This case is illustrated by Figs. 9 and 10.
One pole fails to interrupt after a symmetrical loop (dc component <20%), the next phase clears as a first phase to clear after
a major loop with reduced dc component and another phase then
clears as the second phase to clear (kpp = 1.3) after a major extended loop and the following longest arcing times:
tmxasym
tmxasym

tmsym + 155 el.

(for 2 cycle circuit-breakers)
tmsym + 143 el.
(for 3 cycle circuit-breakers)

Fig. 10. Asymmetrical currents during 3-phase short-circuit interruption of 40

kA60 Hz by 3-cycle circuit-breaker with kpp = 1.3. Interruption after a major
extended loop by the second pole to clear.

The results obtained in Section III-A are also valid for the
first pole to clear.
Condition ii): Interruption by one of the last pole to clear
after a major extended loop with the required percentage of the
dc component.
This case is illustrated by Figs. 11 and 12.
One pole fails to interrupt after a symmetrical loop (dc component <20%), the next phase clears as a first phase to clear after
a major loop with reduced dc component and one of the last two
phases then clears after a major extended loop and the following
longest arcing times:

B. Three-Phase Interruption of Asymmetrical Currents in

Isolated or Impedance-Earthed Neutral Networks

tmxasym

Condition i): Interruption by the first pole to clear after a

major loop with the required percentage of the dc component.

tmxasym

tmsym + 163 el.

(for 2 cycle circuit-breakers)
tmsym + 153 el.
(for 3 cycle circuit-breakers)

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IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 15, NO. 1, JANUARY 2000

with tmsym = minimum (IEC) or shortest (ANSI) arcing

time of test duty T100s (IEC) or TD4 (ANSI)
if the circuit-breaker fails to clear perform b) and c)
if the circuit breaker interrupts perform c) and d).
b) One test with interruption of the first pole to clear after a
major loop with the required dc component and:
arcing time = tmsym + 135 el.
the circuit-breaker must interrupt after the major loop or
the subsequent minor loop.
c) One test with interruption of the second pole to clear after
a major extended loop and the required dc component
and:

Fig. 11. Asymmetrical currents during 3-phase short-circuit interruption of 40

kA60 Hz by 2-cycle circuit-breaker with kpp = 1.5. Interruption after a major
extended loop by the second pole to clear.

arcing time

tmsym + 150 el.

if kpp = 1.3

arcing time

tmsym + 160 el.

if kpp = 1.5

or

the circuit-breaker must interrupt after the major loop or

the subsequent minor loop.
d) A third interruption shall be made when a) and c) are done
to verify that c) is the condition with the longest arcing
time after a major extended loop:
Contact separation is advanced by 30 el., the circuitbreaker must interrupt the first phase after a symmetrical
(or minor) loop and not after the subsequent major loop.
V. CONCLUSION

Fig. 12. Asymmetrical currents during 3-phase short-circuit interruption of 40

kA60 Hz by 3-cycle circuit-breaker with kpp = 1.5. Interruption after a major
extended loop by the second pole to clear.

IV. APPLICATION TO STANDARDS

The results presented in Section III can be used, and simplified for the purpose of standardization, to define a test procedure
applicable to three-phase synthetic testing of high-voltage circuit-breakers (test duty T100a of IEC and TD5 of ANSI/IEEE).
The tests must demonstrate the circuit-breaker capability to
interrupt in conditions i) and ii) defined in Section III with the
longest arcing time. It is also necessary to perform three tests as
already specified in ANSI C37-09 and IEC 56.
The following procedure is then proposed:
a) One test with interruption of the first pole to clear after a
major loop with the required dc component and:
arcing time = tmsym + 60 el.

Due to power laboratories limitations it is generally not possible to completely test a three-phase circuit-breaker by threephase direct tests. Either single-phase tests, unit tests or threephase synthetic tests must be performed.
At the moment, the procedure for three-phase synthetic tests
is not well defined, especially in the case of asymmetrical currents (test duty T100a of IEC 56 or TD5 of ANSI/IEEE).
The study presented in this paper introduces a procedure for
three-phase synthetic asymmetrical tests which is able to assess
the circuit-breaker capability to interrupt its rated breaking current with the required dc component.
This test procedure aims at limiting the number of tests to the
same number required for direct testing. It should be then possible to limit the number of specimen necessary for type testing
to a reasonable value and also to limit the cost of type testing
which in recent years has greatly increased due to the introduction of new requirements.
REFERENCES
[1] , IEC Standard 56 or 60056 (1987). Under revision.
[2] , ANSI/IEEE Standard C37-09 (1979). Under revision.
[3] Guide for Synthetic Fault Testing of AC High-Voltage Circuit-Breakers
Rated on a Symmetrical Current Basis, ANSI/IEEE C37-081. Under revision.
[4] , IEC Standard 427 (1989-10).
[5] , IEC Technical Report 1633 (1995).
[6] Supplement to IEEE Guide for Synthetic Fault Testing of AC
High-Voltage Circuit-Breakers Rated on a Symmetrical Current Basis,
IEEE Standard C37-08la-1997.

DUFOURNET AND MONTILLET: THREE-PHASE SHORT CIRCUIT TESTING OF HIGH-VOLTAGE CIRCUIT BREAKERS USING SYNTHETIC CIRCUITS

Denis Dufournet was born in Annecy, France on

January 25, 1952. He graduated from ENSEM Nancy
in electrical engineering. He joined ALSTOM (then
Delle Alsthom), Villeurbanne France, in 1977 as a
Research Engineer. Since 1987, he has been Head
of Research on interrupting techniques applicable to
high-voltage and medium voltage circuit-breakers.
He is a Member of the IEEE High-Voltage Subcommittee, of several IEEE working groups, of
IEC WG21 (revision IEC 56), of IEC WG23
(harmonization of IEC and ANSI power tests), of
CIGRE WG 13-01 (application of arc physics), of CIGRE-CIRED WG CC03
(TRV in Medium Voltage). Since 1993, he has been a senior member of the
French Socit des Electriciens et Electroniciens.

147

Georges Montillet was born in Nice, France on December 8, 1944. He graduated from the Polytechnic
Institute of Grenoble (ENSI) in 1968 in power electrical engineering and in 1974 obtained the M.B.A.
degree in finance from NYU-New York. He joined
Cogenel, now ALSTOM, New York, in 1971 after
working on several projects in France, Algeria, and
New York.
He is now Project Manager of Dead Tank
Development in ALSTOM. He has been a member
of IEEE since 1970, and a member of the High
Voltage Switchgear Committee, and various subcommittees, one of which one
is Synthetic Testing of High Voltage Circuit Breakers.