Robust Power Gating Implementation using ICC

Ariel Wolf

Intel Corporation
Mobile Wireless Group, Israel
ariel.wolf@intel.com

ABSTRACT
In the latest mobile communication devices, long battery life becomes a key feature for the end
consumer. Leakage power optimization plays a dominant role in achieving this goal.
Using latest DSM (Deep Sub Micron) process technologies, Traditional Multi-Vt techniques are
not sufficient and power gating needs to be implemented.
IC Compiler DP (Design Planning) introduces advanced features to support power gating
implementation and its derivatives, e.g.: Power domains, Coarse-Grain MT-CMOS switches,
Isolation cells placement, and AON (Always-On) synthesis.
This paper describes BKMs (Best Known Methods) for designing a Multi-Domain FP
(Floorplan), including Voltage area creation and shaping, power switches insertion and
stitching, and PNS/PNA (Power Network synthesis & analysis). In addition, paper discusses in
details the UPF (Unified Power Format) flow advantages and P&R (Place and Route) effects.

Table of Contents
1 Introduction .............................................................................................................................. 3
2 Multi-Vt flows .......................................................................................................................... 4
2.1 Traditional Multi-Vt techniques .......................................................................................... 4
2.2 Multi-VT flow in 45nm ....................................................................................................... 4
3 Power Gating basics ................................................................................................................. 5
3.1 Introduction .......................................................................................................................... 5
3.2 Power Switches placement styles ........................................................................................ 6
3.3 Low-Power cells .................................................................................................................. 7
4 UPF flow .................................................................................................................................. 8
4.1 Synopsys UPF flow .............................................................................................................. 8
4.2 UPF examples ...................................................................................................................... 9
5 Low-Power flow steps ............................................................................................................ 11
5.1 Multi-VDD floor planning ................................................................................................. 11
5.2 MT-CMOS switches insertion, placement, connection ..................................................... 11
5.3 Multi-Domain Power Grid ................................................................................................. 14
5.4 Domain aware Place & Route ............................................................................................ 14
5.5 Always-on synthesis........................................................................................................... 15
6 Low-Power flow analysis ....................................................................................................... 16
6.1 Power network analysis ..................................................................................................... 16
6.2 Low-Power cells connections ............................................................................................ 17
6.3 MT-CMOS switch count.................................................................................................... 17
7 Conclusions ............................................................................................................................ 18
8 Acknowledgements ................................................................................................................ 18
9 References .............................................................................................................................. 19
10
Appendix ............................................................................................................................ 19
10.1 Abbreviation Table ............................................................................................................ 19

Table of Figures
Figure 1 Multi-Vt optimization flow ........................................................................................... 4
Figure 2 Power Gating ................................................................................................................. 6
Figure 3 - Switch cell placement..................................................................................................... 7
Figure 4 Low Power cells usage .................................................................................................. 8
Figure 5 - UPF flow support across Synopsys tools ....................................................................... 9
Figure 6 Schematics of Double-Input power switch .................................................................. 12
Figure 7 - Distributed placement of MT-CMOS switches ............................................................ 13
Figure 8 - Voltage Area view of Multi-Domain block ................................................................. 13
Figure 9 implementation techniques for always-on cells ........................................................... 16
Figure 10 - Static IR drop ............................................................................................................. 16
Figure 11 - ELS power connection ............................................................................................... 17
Figure 12 - I/R drop through power switch ................................................................................... 18

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Robust Power Gating Implementation

Introduction

As device geometries shrink, the fraction of leakage power out of the total power becomes more
and more significant. In addition, growing demand for highly integrated SoC with many logic
functions contribute to increased power consumption.
Low power designs are becoming more prevalent in semiconductor industry with the exponential
demand for mobile devices with longer battery life. Several methods are being adopted right
from architectural level all the way till the transistor level, in order to reduce power consumption
in functional and standby modes of the design. Reducing the stand-by leakage power is one of
the most challenging requirements of SoC designs targeted for mobile electronic devices.
This paper describes BKMs (Best Known Methods) for implementing robust Ultra low-power
designs using Multi-Domain approach.

Chapter 2 describes traditional Multi-Vt optimization method for leakage reduction and its
limitation and complexity at advanced process nodes.
Chapter 3 describes the basics of power gating
Chapter 4 give an overview of UPF flow and how its being supported in Synopsys tools
Chapter 5 details the various steps in Power-gating implementation flow, including Voltagearea creation, Power-Grid synthesis, Power switches insertion and domain aware place &
route. This chapter also discusses always-on cells usage inside switchable domains.
Chapter 6 describes the required flows for analyzing power gating design, in order to make
sure it meets the specifications with good Quality of Results.

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2
2.1

Multi-Vt flows
Traditional Multi-Vt techniques

Initially presented at 0.18u process nodes, Multi-Vt optimization technique has become the
standard solution for reducing leakage current. The main idea is library cells with same
functionally but with various Vt classes: High, Standard & Low. Low-Vt cells are faster but
more leaky, while high-Vt cells are slower but less leaky.
High-Vt cells are used for non-critical paths, while Standard-Vt cells for critical paths.
Various Vt cells share same footprint and allow easy swapping during the implementation cycle.
Implementing non-Standard Vt cells requires 2 additional implant layers which increases the
overall product cost.
Most EDA tools support Multi-Vt swapping and usually the designer goal is to reach high
percentage of High VT cells among all Standard cells being used.

Figure 1 Multi-Vt optimization flow

2.2

Multi-VT flow in 45nm

In 45nm under Worst case conditions for timing (SS, 0.99V, -40C) H-Vt cells has higher leakage
compared to S-Vt cells. In this PVT corner, the gate leakage current becomes the dominant part
of the cell leakage (instead of the sub-threshold current). Since H-Vt devices have slightly larger
gate leakage than S-Vt counterpart, their total leakage is higher.
In order to perform Multi-Vt optimization, additional corner libraries (Typical) are required and
also Multi-Corner optimization capabilities are required.
ICC presents MCMM technique which supports this optimization, but it also implies higher TAT
(TurnAround Time). Leakage optimization is done under typical mode.
In addition, While 10X leakage reduction achieved in 90nm, only 3.5X difference is seen in
45nm.

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3
3.1

Power Gating basics

Introduction

Power Gating is performed by shutting down the power for a portion of the design, using a
dedicated power Switch (Also known as Power Management Cell). The basic idea of power
gating is to separate the VDD or GND power supply from the standard cells of a specific design
hierarchy. The power switches are implemented using appropriately sized transistors of PMOS
(Header) or NMOS (Footer) type. These two different methods only differ in the fact that the
switches switch different power rails, VDD and VSS respectively. Customers turned to use
header switches since header switches have less leakage and they are also more intuitive for
implementation.
Switch cell has 2 modes of operation: ON or OFF. When switches are in OFF state, they
disconnect the devices inside the block from their power source. This reduces the leakage
current flow in the devices of the block.
There are 2 approaches for power gating- fine grain and coarse grain. In fine grain
implementation, each standard cell has inbuilt power switch. On the other hand, coarse-grain
switches controls entire block of standard cells, using a large size transistor. Each of these
methodologies has their various tradeoffs. Fine grain is easier to implement in terms of timing
analysis, but with significant area overhead resulting in higher fabrication cost. On the other hand,
the coarse grain switches require more consideration in terms of timing and wake-up time, but shows
greater leakage saving.
The Coarse-Grain power gating methodology becomes the common implementation technique
nowadays and can reduce the leakage current by 30X.

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VDD

VDD

Header

Power Domain
VDD_SW

Power Domain
Footer

VSS

VSS

Figure 2 Power Gating

3.2

Power Switches placement styles

Coarse grain implementation provides multiple placement topologies for the power switches. For
example, switches can be placed around the power domain (in a column or ring way) or in an
array fashion inside the domain area. Array style is a more common technique as it yields
smaller IR-drop and less area. It is also more efficient with respect to Power-Gates control
sequence. On the other hand, ring approach can eliminate the user from synthesizing complicated
Power-Grid and it also gives better placement results, as it removes fragmentations from
placement areas.
Array style also suits best Flip-Chip designs, where Power is delivered from the Bond pads
placed also inside the core, which reduce IR-drop significantly, when compared to ring
placement style.

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Figure 3 Power Switch cells placement

3.3

Low-Power cells

To facilitate data transfer between multiple Power domains operating at different voltage levels, it is
recommended to use level-shifters. Usually both low-to-high and high-to-low level shifters are
provided by library vendors.
Level shifters are used for two main reasons. First of all, when a signal propagates from a lowvoltage block to a high-voltage block, a lower voltage at the PMOS gate might result in the gate not
being entirely switched off, which can cause abnormal leakage current.
Secondly, because signals must transition across voltage domains, levels shifters should be used to
ensure that both net transition and net delays are accurately calculated.
For power domains which share the same operating voltage but some of them may be shut-off, an
isolation cell is required on power domain interface. The reason for this is that cells connected to
power-off blocks, their inputs become floating which may cause high leakage power. Therefore,
isolation cells are necessary to isolate floating inputs. The isolation is performed by setting a default
logic value on the output depends on the state of a dedicated control pin. Usually 2 types of isolation
cells are provided by the library vendor: clamp0 and clamp1, which differs by the default value, set
in isolation state. Desired cell type is chosen according to the functionality on the receiver side.
Blocks operate at different voltage levels, and some of them can also be turned off, requires both
isolation and level-shifting functions at the power domain interface. To simplify implementation,
library vendors usually supply a single cell called the enable-level shifter, which is basically a
level-shifter that includes an enable signal.
The recommendation is to place Enable Level Shifters on all outputs of such blocks.
Both Isolation cells and Enable Level Shifters are placed on the Always-on area.
Figure 4 illustrates Low-Power cells usage between various types of power domains.

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Figure 4 Low Power cells usage

4
4.1

UPF flow
Synopsys UPF flow

The Unified Power Format (IEEE P1801 UPF) is a standard set of Tcl-like commands used to
specify the low-power design intent for electronic systems. It allows the designer to specify the
power requirements of a design, but without specifying explicitly how those requirements are
implemented. The language specifies how to create a power supply network to each design
element, the behavior of supply nets with respect to each other, and how the logic functionality is
extended to support dynamic power switching to design elements. It does not contain any
placement or routing information.
The UPF specification is separate from the RTL description of the design, which enables easy
adoption when using legacy RTL files.
Design Compiler reads the UPF side-file and uses it to automatically insert isolation, levelshifters and Always-On cells into the gate-level design, to match the specification defined in the
UPF file.
UPF file content might be updated during the flow with implementation information, for
example, explicit power connections of Low-Power cells are added during synthesis.
IC Compiler reads in the gate-level netlist and UPF file exported by Design-Compiler, and based
on its content, performs physical implementation (placement and routing), producing a modified
gate-level netlist, and an updated UPF file, which contains the modifications to low-power circuit
structures resulting from physical implementation, such as power switches.
In further stages of the flow such as verification/power-analysis, tools reads an updated UPF file
which match the correspondence netlist, as illustrated in the Figure below.

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Figure 5 - UPF flow support across Synopsys tools

4.2

UPF examples

The following example contain complete UPF file for design with 2 power domains, PD_1 and
PD_2. PD_1 operates at lower voltage level then PD_2 and both domains may be switched off
completely.
# Power Domains
create_power_domain PD_top -include_scope
create_power_domain PD_1 -elements blockA
create_power_domain PD_2 -elements blockB
# Power Ports Definitions
create_supply_port VDD -direction in
create_supply_port VSS -direction in
create_supply_port VDDL -direction in
# Supply nets definitions
create_supply_net VDD -domain PD_top
create_supply_net VDD -domain PD_1 reuse
create_supply_net VDDL domain PD_top
create_supply_net VDDL -domain PD_2 -reuse
create_supply_net VSS -domain PD_top
create_supply_net VSS -domain PD_1 -reuse
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create_supply_net VSS -domain PD_2 -reuse

create_supply_net VDD_SW1 -domain PD_top
create_supply_net VDD_SW2 -domain PD_top
create_supply_net VDD_SW1 -domain PD_1 -reuse
create_supply_net VDD_SW2 -domain PD_2 reuse
# Set primary P/G for Power Domains
set_domain_supply_net PD_top -primary_power_net VDD -primary_ground_net VSS
set_domain_supply_net PD_1 -primary_power_net VDD_SW1 -primary_ground_net VSS
set_domain_supply_net PD_2 -primary_power_net VDD_SW2 -primary_ground_net VSS
# connect Supply nets to Ports
connect_supply_net VDD -ports VDD
connect_supply_net VDDL -ports VDDL
connect_supply_net VSS -ports VSS
# Define Power Switches
create_power_switch SW1 -domain PD_1 \
-output_supply_port {SWOUT VDD_SW1} \
-input_supply_port {SWIN VDD} \
-control_port {CNTL pd1_power_down} \
-on_state {state1 SWIN {pd1_power_down}}
map_power_switch SW1 -domain PD_1 \
-lib_cell {coarse_grain_lib/HDRDID2BWPHVT}
Create_power_switch SW2 \
.
# Define Power States
add_port_state VDD -state {HV 0.990000}
add_port_state VDDL -state {LV 0.810000}
add_port_state VSS -state {OFF 0.00}
add_port_state SW1/SWOUT -state {HV 0.990000} -state {OFF off}
add_port_state SW2/SWOUT -state {LV 0.810000} -state {OFF off}
create_pst top_pst -supplies [list VDD VDDL VDD_SW1 VDD_SW2 VSS]
add_pst_state all_on -pst top_pst -state {HV LV HV LV OFF}
add_pst_state pd1_on_pd2_off -pst top_pst -state {HV LV HV OFF OFF}
add_pst_state pd1_off_pd2_on -pst top_pst -state {HV LV OFF LV OFF}
add_pst_state top_only_on_idlee -pst top_pst -state {HV LV OFF OFF OFF}
# Isolation / Level-Shifter rules
set_isolation iso_pd1 -domain PD_1 \
-isolation_power_net VDD -isolation_ground_net VSS \
-clamp_value 1 -applies_to outputs
set_isolation_control iso_pd1 -domain PD_1 \
-isolation_signal pd1_iso -isolation_sense low -location parent
set_isolation iso_pd1_clamp0 -domain PD_1 \
-isolation_power_net VDD -isolation_ground_net VSS \
-elements { INSTANCE1/pin INSTANCE2/pin }
set_isolation_control iso_pd1_clamp0 -domain PD_1 \
-isolation_signal pd1_iso -isolation_sense low -location parent
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set_isolation iso_pd2 -domain PD_2 -isolation_power_net VDD \

-isolation_ground_net VSS -clamp_value 1 -applies_to outputs
set_isolation_control iso_pd2 -domain PD_2 \
-isolation_signal pd2_iso -isolation_sense low -location parent
set_level_shifter ls_pd2 -domain PD_2 \
-applies_to outputs -rule low_to_high -location parent

5
5.1

Low-Power flow steps

Multi-VDD floor planning

The floorplan is the first design stage where the voltage area can be defined. A voltage area is a
1:1 mapping to a power domain defined in the UPF.they should have the same name and same
set of hierarchical cells. The associated logic information of the voltage area is automatically
derived from its matching power domain.
If user cannot identify the best location for a voltage area manually, he can run a quick coarse
placement and trace the Voltage-Area related logic to determine a suitable location.
After the user-defined voltage areas are created for all power domains, the tool automatically
derives a default voltage area (DEFAULT_VA) for placement of cells not specifically assigned
to any voltage areas and these cells are treated as always-on and connected to True-VDD supply.
In the automatic FP flow, fast coarse placement is executed with the aid of create_fp_placment
command, in order to determine initial placement for power-domain cells. Voltage Areas can
then be shaped automatically using shape_fp_blocks command.
After Voltage area have been shaped and finalized, consecutive create_fp_placment commands
can be execute in order to achieve a Voltage-Area aware legal placement of both STDCELLs and
memory macros.
5.2

MT-CMOS switches insertion, placement, connection

Power switch cells require special placement near the power straps. The
add_header_footer_cell_array command is used to insert and place the MT-CMOS switches.
First a 2-dimensional grid is created and then the switch cells are automatically on specified grid
points, inside or around the Voltage area. Cells are logically instantiated under the power domain
logic hierarchy.
Switches are inserted in an array structure by specifying the vertical and horizontal separation
between each row and column. Number of power switches inserted depends on this separation
and plays important role in IR drop seen by design.
After placing the switch cells, the sleep net (which connects all sleep pins of switch cells) is
connected by using the connect_power_switch command.
2 type of switches usually supplied by library vendors: Single input and Double input.
The double-input switch architecture minimizes the power up glitch by enabling the user first
turn on a small daughter switch, then turn on the mother switch to minimize the performance
degradation. By turning on two switches at different times the user can effectively reduce the
current spikes during ramp-up. The following figures demonstrate schematic and abstract layout
of Double-Input power switch.
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Figure 6 Schematics of Double-Input power switch

Proper care should be taken during power switch insertion to ensure that power switches are
aligned with the Always-on power straps. This will ensure that the TVDD (true VDD) signal pin
of the switch is hooked appropriately to the power strap.
The control pins of the power switch should also be connected fittingly. Power switch enable
connection determines the turn-on control sequence of the shut-off block. This turn-on sequence
is highly important in determining peak rush current, peak IR-drop, and turn-on time. The longer
the turn-on time, the less peak rush current and voltage drop. Stitching the power switch enable
pins can happen in the daisy chain fashion, column based or HFN (High Fanout Net).
HFN enable connection is not recommended due to high in-rush currents during power-up.
If the switches are stacked vertically, the most efficient control pin connection would be vertical
daisy chain. On the other hand, if the switches are placed side to side, then the signals must be
routed horizontally in a daisy chain. In daisy chain connections, which can be used with either
single or double-input headers, the enable signal propagates through the entire delay chain to
switch on the power switches one at a time. For the double-input header, the signal propagates
back through the chain once it has reached the end. The daisy chain connection can be snaked in
different patterns throughout the block.
In the column based approach, columns can be turned on one by one, with a delay between each
column. Another option is turn on groups of columns at the same time to shorten wake-up time.
Alternatively, some columns can be turned on from the bottom instead of the top to balance the
turn-on current distribution.
The following figure illustrates a column based placement of power switches.

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Figure 7 - Distributed placement of MT-CMOS switches

After power switches have been optimally placed and their control lines were stitched properly in
order to meet design requirement for power-up, it is recommended to review both placement and
connectivity of MT-CMOS power switches in the layout window, with the aid of special view in
IC-Compiler as illustrated in the following figure.

Figure 8 - Voltage Area view of Multi-Domain block

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5.3

Multi-Domain Power Grid

Once Voltage areas have been created and shaped, switch has been inserted and design is legally
placed, Multi-Domain Power-Grid can be created.
Ground mesh should be continuous across all Voltage Areas since Ground net is common for all
power domains. True-VDD power straps should also be continuous since they need to be
connected to all power switches. On the other hand, Switched power grid needs to be created for
each switched net inside VA boundary only.
Synthesis of power-grid can be done effectively using PNS engine inside IC-compiler. Tool is
capable of generating a power-grid for each domain by automatically synthesizing the rings
around core and voltage areas boundary using pre defined constraints. The corresponding
switched nets are synthesized for each voltage area, and always-on power grid is synthesized for
non-switching area in design. Synthesis engine creates multiple power-grid internal databases to
select an optimal power grid structure which meets the target IR drop.
The tool uses power switch placement data and strap alignment constraints file to align the metal
straps on top of power switches. IR aware power grid synthesis is done by using syntax
(VDD+VDD_SW1, VDD+VDD_SW2) for the power net. This syntax allows the tool to consider
IR drop across power switch when synthesizing the top level net. Tool creates virtual metal1 rail
connection to the cells for accurate IR drop computation during synthesis. Tool automatically
distributes the total specified block power to each voltage areas based on instance count of each
voltage area. Based on this power number and the target IR drop specified tool creates the
internal database of PG straps in a grid structure. Tool optimizes the width of PG straps to meet
the IR drop target.
Once IR goals are met, synthesized power grid is committed to the block and suggested straps
turn into real wires. Tool creates a TCL script containing all information which can be loaded in
future runs to instantly replicate the created power grid.
5.4

Domain aware Place & Route

Cell placement steps performed by place_opt mega command are voltage-area-aware. This
means that each design instance is assigned to a single voltage area, the voltage area is
exclusively allocated to a certain logic hierarchy partition, and any new instance created for a
certain logic hierarchy is legally placed within the voltage area boundary and subjected to the
same operating conditions.
Placement recognizes the cells working at the power domain interface and places those cells near
the related voltage area boundary. Moreover, IC Compiler routing estimation is capable of
detouring around voltage areas.
Low-Power cells, such as level-shifters and isolation cells are placed automatically by the tool on
the power domain boundaries. However, user needs to make sure to follow all placement rules
for Level-Shifter cell to avoid DRC issues due to floating wells.
Clock-Tree Synthesis, performed by clock_opt mega command is multi-voltage aware. The clock
tree synthesis engine in IC Compiler recognizes the logic hierarchy associated with the voltage
area and creates the clock tree bottom-up by clustering sink points from the same voltage area.
After the clock subtrees are built for each voltage area, clock tree synthesis joins the subtrees at
the root of the clock net.

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Routing step is also Voltage-Area aware. The global router honors voltage areas constraints by
routing all nets that belong to the power-domain within the voltage area boundary, which is
treated as a hard constraint. The detailed router, if there is no routing resource available, can
route outside the voltage area boundaries at local spots only. The nets traversing power domains
do not follow the same rule. They can be routed through the related voltage area.
5.5

Always-on synthesis

When dealing with shut-down domains, there can be some situations in which certain cells in the
shut-down domain need to stay active, such as power switches control lines, low-power cells
(isolation or level-shifters) and pure logic paths from inputs to outputs.
There are 2 implementation techniques to enable active logic to reside within shut-down power
domain.
One method for implementing always-on logic is with the aid of dedicated always-on cells,
which may exist in STDCELL libraries. Compared to an ordinary cell, a functionally equivalent
always-on cell has an extra power supply that serves as a backup power during the shut-off mode.
These cells are usually implemented as double heighted cells and can be placed anywhere inside
the domain. In order to enable this technique, use needs to run the following commands:
# DUAL POWER RAIL AO STRATEGY
set_always_on_strategy -cell_type dual_power -object_list {PD_1 PD_2}
# SET CORRECT AO ATTRIBUTES ON DESIRED PINS
set_attribute [get_lib_pins <PINS REQUIRE AO SYNTHESIS>] always_on true
# GLOBAL VARIABLE TO ENABLE AO SYNTHESIS
set enable_ao_synthesis true

Another method for implementing always-on paths with normal cells (with a single power
supply) is to create a dedicated placement area which has constant power supply. This type of
special placement area is allocated exclusively for always-on cells and also known as exclusive
move bound. User need to take care of explicit power connections to this region, by generating
Always-ON power rails inside that region and connect them the True VDD power straps.
A move bound can be defined as exclusive bound and assigned with the always-on cells, using
the following commands:
## SINGLE POWER RAIL AO STRATEGY
set_always_on_strategy -object {MODULE_A} -cell_type single_power
## CREATE MOVE BOUND FOR AO CELLS
create_bound name AO_BOUND exclusive -coordinates {120 140 160 180}
set_power_guide name AO_BOUND -type always_on
# GLOBAL VARIABLE TO ENABLE AO SYNTHESIS
set enable_ao_synthesis true

The following figure demonstrates the 2 possible implementation techniques for always-on logic.

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Figure 9 implementation techniques for always-on cells

6
6.1

Low-Power flow analysis

Power network analysis

Before continue to P&R, it is very important to perform IR-Drop/EM analysis, to validate:

Sufficient number of switches.
Optimal switch placement.
Static IR-drop target is met
In-rush current and power-up time are within system specification range.
During Power-Grid analysis it is very important to take into account IR drop across the Switch
cells due to internal resistance. Power-Gate resistance data is supplied by the library vendor, and
its usually a constant value (~100Ohm). IC-Compiler support this features by honoring this R
value during analysis. Insufficient number or sub-optimal distribution of power switches will
increase the resistance (and Voltage Drop) across the switch and will be easily identified during
Static IR drop analysis

Figure 10 - Static IR drop

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6.2

Low-Power cells connections

Enable Level Shifter are usually placed on the Always-ON domain.

VDDL Power port should be connected to the switched power net of the source input signal.
Power-related cells such as level shifters, isolation cells, always-on cells, and power switches
typically have multiple power and ground pins and are taller than standard cells.
As a designer, you need to make sure that all the power pins are connected
and correctly routed to the power nets.
For example, consider the following figure of Enable Level Shifter on output signal of PD1
domain. The secondary power pin, VDDL, should be connected to the power supply net,
VDD_SW1. For power supply routing, VDDL needs to be routed to the VDD_SW1 strap.
However, this cannot be achieved with the normal signal or power routing method. A special
type of routing, called net mode routing (specified with the command preroute_standard_cell
mode net), is required to connect the secondary pin to the nearby power strap.

Figure 11 - ELS power connection

6.3

MT-CMOS switch count

In order to ensure correct operation under functional mode, we need to make sure no I/R drop is
within cell characterization range (usually 10% of Nominal voltage). Since Power switches are in
linear state when they are turned ON, they act like a resistor which drops the Voltage based on its
resistance, as described in figure 12.

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Figure 12 - I/R drop through power switch

Minimal number of power switches can be determined from the following data:
DC I/V curve (Transistors are in linear state)
IR drop limit for the switches
Domain power consumption
One can use the following formula to derive the minimum number of switches required for a
design when the above data is given as input.
Min Switch #

SW res .(Ohm ) Domain Current Consumptio n ( mA )

Switch Vdrop (mV )

Additional optimization can be made for leakage/Performance tradeoff. While large number of
switches increases total leakage & area, insufficient number of switches increase IR drop and
degrades performance.

Conclusions

Power-Gating is required for achieving a competitive mobile communication product.

Designers can take advantage of UPF driven flows to automate many steps in implementing and
validating Power-gating design.
New features in IC-Compiler Design-Planning flow enable robust implementation of large
number of power domains.
Placement, CTS & routing commands are voltage aware by default.

Acknowledgements

The author would like to acknowledge Moti Zeltzer, AC of Synopsys, for reviewing this paper
and providing helpful feedback. Thanks are also due to TSMC world-wide support teams for
their invaluable support in developing this flow.

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References

[1]
[2]
[3]
[4]

TSMC Standard Cell Library Application Note

Synopsys Low-Power Flow User-Guide, B-2008.09
TSMC Reference-Flow 9.0
Keating M., Flynn D., Aitken R., Gibbons A., Shi K., Low Power Methodology Manual for
System-on-Chip Design, Springer 2007, ISBN 978-0-387-71818-7

10 Appendix
10.1 Abbreviation Table
Abbreviation
AO
CTS
EDA
FF
ISO
L/S/H Vt
LV
LS / ELS
LP
MCMM
PNS PNA
PVT
PD
SS
TAT
QOR
UPF
VA

SNUG Israel 2009

Meaning
Always On
Clock Tree Synthesis
Electronic Design Automation
Fast Fast
Isolation Cell
Low, Standard, High Voltage Threshold
Low Voltage
Level Shifter / Enable Level Shifter
Low Power
Multi Corner Multi Mode
Power Network Synthesis / Analysis
Process Voltage Temperature
Power Domain
Slow Slow
Turn Around Time
Quality Of Results
Unified Power Format
Voltage Area

19

Robust Power Gating Implementation