ANNA UNIVERSITY PRACTICAL EXAMINATION - APR/MAY -2011

DEPARTMENT OF ECE
EC1404 VLSI DESIGN LAB
Date of Examination: 09.04.11

List of Experiments
1.

Design a 4-to-1 Multiplexer in verilog and simulate with graphical test bench
using Modelsim simulator for the following models:
i)
Switch level model
ii)
Data flow model.

2. Design a 4-to-1 Multiplexer in verilog and simulate with text test bench
using Modelsim simulator for the following models:
i)
Gate level model
ii)
Behavioral model.
3. Design a 1-bit full adder and half adder and simulate with graphical test bench
using Xilinx project navigator for the following models.
i)
Gate level model
ii)
Data flow model
4. Design and simulate a D latch and D Flip Flop in behavioral model and verify the
functionality using Modelsim simulator with inputs given through a text test bench.
5. Design a 4 bit equality detector and perform graphical test bench simulation using
Xilinx ISE simulator for the following models:
i)
Behavioral model
ii)
Gate level model
6. Design and synthesize a 4 to 2 priority encoder in behavioral model using Xilinx
ISE simulator and generate various synthesis reports.
7. Design a 2 to 4 decoder using Schematic option in Xilinx project navigator and
generate verilog code for the schematic and simulate with graphical test bench.
8. Design and simulate a 4-bit ripple carry adder in gate level model with graphical
test bench using Modelsim simulator.
9. Design an half adder in behavioral model and perform back annotation using
Xilinx ISE simulator.
10. Design, Simulate and synthesize a synchronous counter using Xilinx project
navigator and generate the place and route report
11. Design, simulate and implement a signed 8-bit multiplier using Spartan3 FPGA

kit.
12. Design, simulate and implement an 8 bit parallel adder using Spartan 3 FPGA kit.
13. Design, simulate and implement an 8 bit serial adder using Spartan 3 FPGA kit.
14. Design and simulate the traffic light controller using Xilinx ISE simulator.
15. Study of design and implementation of the traffic light controller using Spartan 3
FPGA kit.
16. Study of design and implementation of real time clock using Spartan 3 FPGA kit.

INTERNAL EXAMINER

EXTERNAL EXAMINER

1. Design a 4-to-1 Multiplexer in verilog and simulate with graphical test bench using
Modelsim simulator for the following models:
a. Switch level model
b. Data flow model.
Aim,
Algorithm,
Procedure
(10)

Logic dia,Eqn,
Truth table
(15)

Program
(35)

Simulation
(25)

Result
(5)

Viva
(10)

Total
(100)

2. Design a 4-to-1 Multiplexer in verilog and simulate with text test bench using
Modelsim simulator for the following models:
a. Gate level model
b. Behavioral model.
Aim,
Algorithm,
Procedure
(10)

Logic dia,Eqn,
Truth table
(15)

Program
(35)

Simulation
(25)

Result
(5)

Viva
(10)

3. Design a 1-bit full adder and half adder and simulate with graphical test bench
using Xilinx project navigator for the following models.
i)
Gate level model
ii)
Data flow model
Aim,
Logic dia,Eqn,
Algorithm,
Program Simulation
Result
Viva
Truth table
Procedure
(35)
(25)
(5)
(10)
(15)
(10)

Total
(100)

Total
(100)

4. Design and simulate a D latch and D Flip Flop in behavioral model and verify the

functionality using Modelsim simulator with inputs given through a text test bench.
Aim,
Algorithm,
Procedure
(10)

Logic dia,Eqn,
Truth table
(15)

Program
(35)

Simulation
(25)

Result
(5)

Viva
(10)

Total
(100)

5. Design a 4 bit equality detector and perform graphical test bench simulation using
Xilinx ISE simulator for the following models:
a. Behavioral model
b. Gate level model
Aim,
Algorithm,
Procedure
(10)

Logic dia,Eqn,
Truth table
(15)

Program
(35)

Simulation
(25)

Result
(5)

Viva
(10)

Total
(100)

6. Design and synthesize a 4 to 2 priority encoder in behavioral model using Xilinx

ISE simulator and generate various synthesis reports.
Aim,
Algorithm,
Procedure
(10)

Logic dia,Eqn,
Truth table
(15)

Program
(35)

Simulation
& Synthesis
(25)

Result
(5)

Viva
(10)

Total
(100)

7. Design a 2 to 4 decoder using Schematic option in Xilinx project navigator and

generate verilog code for the schematic and simulate with graphical test bench.
Aim,
Algorithm,
Procedure
(10)

Logic dia,Eqn,
Truth table
(15)

Program
(35)

Simulation
& Synthesis
(25)

Result
(5)

Viva
(10)

Total
(100)

8. Design and simulate a 4-bit ripple carry adder in gate level model with graphical
test bench using Modelsim simulator.
Aim,
Algorithm,
Procedure
(10)

Logic dia,Eqn,
Truth table
(15)

Program
(35)

Simulation
(25)

Result
(5)

Viva
(10)

Total
(100)

9. Design an half adder in behavioral model and perform back annotation using
Xilinx ISE simulator.
Aim,
Algorithm,
Procedure
(10)

Logic dia,Eqn,
Truth table
(10)

Program
(35)

Simulation
& Synthesis
(30)

Result
(5)

Viva
(10)

Total
(100)

10. Design, Simulate and synthesize a synchronous counter using Xilinx project
navigator and generate the place and route report.
Aim,
Algorithm,
Procedure
(10)

Block diagram
(05)

Program
(35)

Simulation
& Synthesis
(35)

Result
(5)

Viva
(10)

Total
(100)

11. Design, simulate and implement an 8 bit parallel adder using Spartan 3 FPGA kit.
Aim,
Algorithm,
Procedure
(10)

Program
(35)

Simulation &
Synthesis
(15)

Implement
-ation
(20)

Manual
Calculation
(5)

Result
(5)

Viva
(10)

Total
(100)

12. Design, simulate and implement an 8 bit serial adder using Spartan 3 FPGA kit.
Aim,
Algorithm,
Procedure
(10)

Program
(35)

Simulation &
Synthesis
(15)

Implement
-ation
(20)

Manual
Calculation
(5)

Result
(5)

Viva
(10)

Total
(100)