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Data Sheet
FEATURES
GENERAL DESCRIPTION
APPLICATIONS
Wireless infrastructure (W-CDMA, TD-SCDMA,
WiMAX, GSM, PCS, DCS, DECT)
Point to point/point to multipoint microwave links
Satellites/VSATs
Test equipment/instrumentation
Clock generation
REFIN A
REFIN B
CLK
DATA
LE
AVDD
AVDD
CE
10-BIT R
COUNTER
2
DOUBLER
DVDD
VP
RSET
VVCO
VRF
MULTIPLEXER
2
DIVIDER
MUXOUT
CREG 1
LOCK
DETECT
DATA REGISTER
FUNCTION
LATCH
CREG 2
CHARGE
PUMP
CPOUT
PHASE
COMPARATOR
VTUNE
VREF
INTEGER
REG
FRACTION
REG
VCO
CORE
MODULUS
REG
VBIAS
VREGVCO
OUTPUT
STAGE
THIRD-ORDER
FRACTIONAL INTERPOLATOR
RFOUTB
PDBRF
1/2/4/8/
16/32/64
OUTPUT
STAGE
CPGND
AGNDRF
SDGND
RFOUTA
ADF5355
MULTIPLEXER
AGND
RFOUTA+
AGNDVCO
12714-001
N COUNTER
Figure 1.
Rev. A
Document Feedback
ADF5355
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Register 3 ..................................................................................... 25
Applications ....................................................................................... 1
Register 4 ..................................................................................... 26
Register 5 ..................................................................................... 27
Register 6 ..................................................................................... 28
Register 7 ..................................................................................... 30
Specifications..................................................................................... 4
Register 8 ..................................................................................... 31
Register 9 ..................................................................................... 31
Register 10 ................................................................................... 32
Register 11 ................................................................................... 32
Register 12 ................................................................................... 33
RF N Divider ............................................................................... 16
Lock Time.................................................................................... 35
VCO.............................................................................................. 18
Register 0 ..................................................................................... 22
Register 1 ..................................................................................... 23
Register 2 ..................................................................................... 24
Rev. A | Page 2 of 38
Data Sheet
ADF5355
REVISION HISTORY
2/15Rev. 0 to Rev. A
Changed Register 5, Bit DB5 Value from 0 to 1 ........ Throughout
Changed Register 5 Default Value from 0x00800005 to
0x00800025 .................................................................... Throughout
Changed Register 8 Default Value from 0x102D4028 to
0x102D0428 ................................................................... Throughout
Changes to Table 1 ............................................................................ 4
Changed Timing Diagram Section to Write Timing Diagram
Section ................................................................................................ 7
Changes to Table 4 ..........................................................................10
Changes to Figure 4 to Figure 6 ....................................................11
Added Figure 7 to Figure 9; Renumbered Sequentially .............11
Changes to Figure 10 to Figure 18 ................................................12
Changes to Figure 20 ......................................................................13
Changes to Figure 23 and Figure 27 .............................................14
Changes to Figure 28 to Figure 30 and Figure 31 Caption ........15
Changes to Reference Input Section and INT, FRAC, MOD,
and R Counter Relationship Section ............................................16
Changes to Phase Frequency Detector (PFD) and Charge Pump
Section ..............................................................................................17
Changes to VCO Section and Output Stage Section ..................18
Rev. A | Page 3 of 38
ADF5355
Data Sheet
SPECIFICATIONS
AVDD = DVDD = VRF = 3.3 V 5%, 4.75 V VP = VVCO 5.25 V, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, RSET = 5.1 k, dBm referred
to 50 , TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
REFINA/REFINB CHARACTERISTICS
Input Frequency
Symbol
Min
Typ
Max
Unit
Single-Ended Mode
Differential Mode
Input Sensitivity
Single-Ended Mode
10
10
250
600
MHz
MHz
0.4
AVDD
V p-p
Differential Mode
0.4
1.8
V p-p
60
250
125
pF
pF
A
A
MHz
Input Capacitance
Single-Ended Mode
Differential Mode
Input Current
Phase Detector Frequency
CHARGE PUMP (CP)
Charge Pump Current, Sink/Source
High Value
Low Value
RSET Range
Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
Input High Voltage
Input Low Voltage
Input Current
Input Capacitance
LOGIC OUTPUTS
Output High Voltage
Test Conditions/Comments
6.9
1.4
ICP
VINH
VINL
IINH/IINL
CIN
1.5
VOH
DVDD
0.4
1.5
mA
mA
k
%
%
%
0.6
1
3.0
1.8
3.15
4.75
Fixed
0.5 V VCP 1 VP 0.5 V
0.5 V VCP1 VP 0.5 V
VCP1 = 2.5 V
V
V
A
pF
V
IOH
VOL
IVCO
RSET = 5.1 k
4.8
0.3
5.1
3
3
1.5
AVDD
DVDD, VRF
VP, VVCO
IP
AVDD
5.0
8
62
6 to
36
70
Rev. A | Page 4 of 38
500
0.4
V
A
V
3.45
5.25
9
69
85
mA
mA
mA
Data Sheet
Parameter
RFOUTA/RFOUTB Supply Current
ADF5355
Symbol
IRFOUTx
Min
Harmonic Content
Second
Third
Fundamental VCO Feedthrough
RF Output Power 4
Typ
Max
Unit
16
30
42
55
500
1000
20
35
50
70
mA
mA
mA
mA
A
A
6800
13600
6800
15
15
0.5
MHz
MHz
MHz
MHz/V
MHz/V
MHz
30
MHz
27
22
20
12
8
55
dBc
dBc
dBc
dBc
dBm
dBc
+8
3
dBm
dBm
1
1
1
1
6
4
60
30
15
17
dBm
dBm
dB
dB
dB
dB
dBm
dBm
dBm
dBm
116
136
138
155
113
133
135
153
110
130
132
150
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
3400
6800
53.125
KV
NOISE CHARACTERISTICS
Fundamental VCO Phase Noise Performance
Rev. A | Page 5 of 38
Test Conditions/Comments
RFOUTA output stage is
programmable; enabling RFOUTB
draws negligible extra current
4 dBm setting
1 dBm setting
2 dBm setting
5 dBm setting
Hardware power-down selected
Software power-down selected
Fundamental VCO range
2 VCO output (RFOUTB)
ADF5355
Parameter
VCO 2 Phase Noise Performance
Data Sheet
Symbol
Min
Typ
Max
Unit
110
130
132
149
107
127
129
147
103
124
126
144
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
221
223
116
150
80
dBc/Hz
dBc/Hz
dBc/Hz
fs
dBc
Test Conditions/Comments
VCO noise in open-loop conditions
100 kHz offset from 6.8 GHz carrier
800 kHz offset from 6.8 GHz carrier
1 MHz offset from 6.8 GHz carrier
10 MHz offset from 6.8 GHz carrier
100 kHz offset from 10 GHz carrier
800 kHz offset from 10 GHz carrier
1 MHz offset from 10 GHz carrier
10 MHz offset from 10 GHz carrier
100 kHz offset from 13.6 GHz carrier
800 kHz offset from 13.6 GHz carrier
1 MHz offset from 13.6 GHz carrier
10 MHz offset from 13.6 GHz carrier
Rev. A | Page 6 of 38
Data Sheet
ADF5355
TIMING CHARACTERISTICS
AVDD = DVDD =VRF = 3.3 V 5%, 4.75 V VP = VVCO 5.25 V, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, RSET = 5.1 k, dBm referred
to 50 , TA = TMIN to TMAX, unless otherwise noted.
Table 2. Write Timing
Parameter
t1
t2
t3
t4
t5
t6
t7
Limit
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
t5
CLK
t2
DATA
DB31 (MSB)
t3
DB30
DB3
(CONTROL BIT C4)
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t7
t1
t6
Rev. A | Page 7 of 38
12714-002
LE
ADF5355
Data Sheet
Rating
0.3 V to +3.6 V
0.3 V to +0.3 V
0.3 V to +5.8 V
0.3 V to AVDD + 2.5 V
0.3 V to VP + 0.3 V
0.3 V to DVDD + 0.3 V
0.3 V to AVDD + 0.3 V
0.3 V to AVDD + 0.3 V
2.1 V
40C to +85C
65C to +125C
150C
27.3C/W
TRANSISTOR COUNT
The transistor count for the ADF5355 is 103,665 (CMOS) and
3214 (bipolar).
ESD CAUTION
260C
40 sec
1000 V
2500 V
Rev. A | Page 8 of 38
Data Sheet
ADF5355
32
31
30
29
28
27
26
25
CREG 2
SDGND
MUXOUT
REFINA
REFINB
DVDD
PDBRF
CREG 1
1
2
3
4
5
6
7
8
ADF5355
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
VBIAS
VREF
RSET
AGNDVCO
VTUNE
VREGVCO
AGNDVCO
VVCO
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
12714-003
AGND
VRF
RFOUTA+
RFOUTA
AGNDRF
RFOUTB
AGNDRF
AV DD
9
10
11
12
13
14
15
16
CLK
DATA
LE
CE
AVDD
VP
CPOUT
CPGND
Mnemonic
CLK
DATA
LE
CE
5, 16
AVDD
VP
CPOUT
8
9
10
CPGND
AGND
VRF
11
RFOUTA+
12
RFOUTA
13, 15
14
17
AGNDRF
RFOUTB
VVCO
18, 21
19
AGNDVCO
VREGVCO
20
VTUNE
22
RSET
Description
Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
Serial Data Input. The serial data is loaded most significant bit (MSB) first with the four least significant bits
(LSBs) as the control bits. This input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register
that is selected by the four LSBs.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.
A logic high (at levels equal to DVDD) on this pin powers up the device, depending on the status of the powerdown bits.
Analog Power Supply. This pin ranges from 3.15 V to 3.45 V. Connect decoupling capacitors to the analog
ground plane as close to this pin as possible. AVDD must have the same value as DVDD.
Charge Pump Power Supply. VP must have the same value as VVCO. Connect decoupling capacitors to the
ground plane as close to this pin as possible.
Charge Pump Output. When enabled, this output provides ICP to the external loop filter. The output of the
loop filter is connected to VTUNE to drive the internal VCO.
Charge Pump Ground. This output is the ground return pin for CPOUT.
Analog Ground. Ground return pin for AVDD.
Power Supply for the RF Output. Connect decoupling capacitors to the analog ground plane as close to this
pin as possible. VRF must have the same value as AVDD.
VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is
available. This pin can be left floating if RFOUTA is disabled in Register 6 or by the PDBRF pin.
Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided
down version is available. This pin can be left floating if RFOUTA is disabled in Register 6 or by the PDBRF pin.
RF Output Stage Ground. Ground return pins for the RF output stage.
Auxiliary VCO Output. The 2 VCO output is available at this pin.
Power Supply for the VCO. The voltage on this pin ranges from 4.75 V to 5.25 V. Place decoupling capacitors to
the analog ground plane as close to this pin as possible. For best performance, this supply must be clean and
have low noise.
VCO Ground. Ground return path for the VCO.
VCO Compensation Node. Place decoupling capacitors to the ground plane as close to this pin as possible.
Connect this pin directly to VVCO.
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT
output voltage.
Bias Current Resistor. Connecting a resistor between this pin and ground sets the charge pump output current.
Rev. A | Page 9 of 38
ADF5355
Pin No.
23
Mnemonic
VREF
24
25, 32
VBIAS
CREG1, CREG2
26
PDBRF
27
DVDD
28
29
30
REFINB
REFINA
MUXOUT
31
SDGND
EP
Data Sheet
Description
Internal Compensation Node. DC biased at half the tuning range. Connect decoupling capacitors to the
ground plane as close to this pin as possible.
Reference Voltage. Connect a 100 nF decoupling capacitor to the ground plane as close to this pin as possible.
Outputs from the LDO Regulator. Pin 25 and Pin 32 are the supply voltages to the digital circuits. Nominal
voltage of 1.8 V. Decoupling capacitors of 100 nF connected to AGND are required for these pins.
RFOUTA Power-Down. A logic low on this pin powers down the RFOUTA outputs only. This power-down function
is also software controllable. Do not leave this pin floating.
Digital Power Supply. This pin must be at the same voltage as AVDD. Place decoupling capacitors to the ground
plane as close to this pin as possible.
Complementary Reference Input. If unused, ac couple this pin to AGND.
Reference Input.
Multiplexer Output. The multiplexer output allows the digital lock detect, the analog lock detect, scaled RF, or
the scaled reference frequency to be externally accessible.
Digital - Modulator Ground. Pin 31 is the ground return path for the - modulator.
Exposed Pad. The exposed pad must be connected to AGND.
Rev. A | Page 10 of 38
Data Sheet
ADF5355
50
50
70
70
90
110
130
150
90
110
130
1k
10k
100k
1M
10M
100M
170
12714-004
170
1k
50
50
70
70
90
110
130
150
10M
100M
90
110
130
100k
1M
10M
100M
170
1k
10k
100k
1M
10M
100M
12714-208
10k
12714-005
1k
70
70
50
90
110
130
90
110
130
150
150
1k
10k
100k
1M
10M
100M
12714-006
1M
150
170
100k
170
10k
12714-207
150
170
1k
10k
100k
1M
10M
Rev. A | Page 11 of 38
100M
12714-209
ADF5355
Data Sheet
50
90
110
130
150
10k
100k
1M
10M
100M
90
170
50
10k
100k
1M
10M
100M
1
2
70
110
130
150
90
110
130
1k
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
70
90
1k
50
1
2
4
8
16
32
64
70
170
12714-011
150
12714-008
170
1k
110
130
150
90
110
130
150
10k
100k
1M
10M
100M
170
12714-009
1k
1k
10k
100k
1M
10M
100M
12714-012
130
1
2
4
8
16
32
64
70
110
12714-010
1k
170
90
150
12714-007
170
1
2
70
70
50
1
2
4
8
16
32
64
Rev. A | Page 12 of 38
Data Sheet
ADF5355
70
90
110
130
170
1k
10k
100k
1M
10M
100M
12714-013
150
10
9
8
7
6
5
4
3
2
1
0
1
2
3
4
5
6
7
8
9
10
40C
+25C
+85C
FREQUENCY (GHz)
50
5
70
10
15
90
POWER (dBc)
12714-016
50
110
130
20
25
30
35
40
150
1k
10k
100k
1M
10M
100M
50
12714-014
170
12714-017
45
10
50
8
6
4
POWER (dBm)
90
110
130
2
0
2
4
6
150
170
1k
10k
100k
1M
10M
100M
10
FREQUENCY (GHz)
12714-018
8
12714-015
70
Rev. A | Page 13 of 38
ADF5355
8
0.45
0.40
0.35
2
0
2
0.25
0.20
0.15
0.10
0.05
10
6.7
7.7
8.7
9.7
10.7
11.7
12.7
13.7
FREQUENCY (GHz)
0
0.8
1.8
2.8
3.8
4.8
5.8
6.8
Figure 22. Output Power vs. Frequency, RFOUTB (10 pF Bypass Capacitor
De-Embedded)
Figure 25. RMS Jitter vs. Output Frequency, fPFD = 61.44 MHz, Loop Filter = 20 kHz
50
40C
+25C
+85C
1
2
PFD = 15.36MHz
PFD = 30.72MHz
PFD = 61.44MHz
60
0.30
12714-019
0.50
40C
+25C
+85C
12714-021
10
Data Sheet
4
5
6
7
8
9
10
11
12
70
80
90
100
13
3.9
4.4
4.9
5.4
5.9
6.4
6.9
FREQUENCY (GHz)
110
12714-126
15
3.4
12714-022
14
80
POWER (dBm)
10
20
30
40
50
90
100
110
120
130
140
150
10
15
FREQUENCY (GHz)
20
170
12714-020
60
1k
10k
100k
1M
10M
Figure 24. Wideband Spectrum, RFOUTB, VCO = 6.8 GHz, RFOUTB Enabled,
RFOUTA+/RFOUTA Disabled (Board Measurement)
100M
12714-023
160
Rev. A | Page 14 of 38
ADF5355
70
70
80
80
90
100
110
120
130
140
150
160
110
120
130
140
150
10k
100k
1M
10M
100M
170
1k
80
4.60
90
4.55
100
4.50
FREQUENCY (GHz)
4.65
110
120
130
140
4.35
4.30
4.20
10M
100M
4.15
1
12714-025
1M
100M
160
100k
10M
4.40
4.25
10k
1M
4.45
150
1k
100k
70
170
10k
12714-127
1k
100
160
12714-024
170
90
2
TIME (ms)
12714-128
Data Sheet
Figure 31. Lock Time for 250 MHz Jump from 4150 MHz to 4400 MHz,
Loop Bandwidth = 20 kHz
Rev. A | Page 15 of 38
ADF5355
Data Sheet
CIRCUIT DESCRIPTION
REFERENCE INPUT
REFERENCE
INPUT MODE
85k
SW2
BUFFER
SW1
SW3
MULTIPLEXER
TO
R COUNTER
AVDD
ECL TO CMOS
BUFFER
N INT
REFINA
REFINB
2.5k
2.5k
12714-026
SW4
BIAS
GENERATOR
RF N DIVIDER
The RF N divider allows a division ratio in the PLL feedback
path. Determine the division ratio by the INT, FRAC1, FRAC2,
and MOD2 values that this divider comprises.
RF N COUNTER
FRAC1 +
N = INT +
MOD2
MOD1
TO PFD
N COUNTER
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
INT
REG
FRAC1
REG
FRAC2
VALUE
MOD2
VALUE
12714-027
FROM
VCO OUTPUT/
OUTPUT DIVIDERS
FRAC2
FRAC2
MOD2
MOD1
FRAC1
(3)
where:
INT is the 16-bit integer value (23 to 32,767 for 4/5 prescaler,
75 to 65,535 for 8/9 prescaler).
FRAC1 is the numerator of the primary modulus (0 to 16,777,215).
FRAC2 is the numerator of the 14-bit auxiliary modulus
(0 to 16,383).
MOD2 is the programmable, 14-bit auxiliary fractional
modulus (2 to 16,383).
MOD1 is a 24-bit primary modulus with a fixed value of 224 =
16,777,216.
This calculation results in a very fine frequency resolution with
no residual frequency error. To apply this formula, take the
following steps:
1. Calculate N by dividing VCOOUT/fPFD.
2. The integer value of this number forms INT.
3. Subtract this value from the full N value.
4. Multiply the remainder by 224.
5. The integer value of this number forms FRAC1.
6. Calculate MOD2 based on the channel spacing (fCHSP) by
MOD2 = fPFD/GCD(fPFD, fCHSP)
(4)
where:
fCHSP is the desired channel spacing frequency.
GCD(fPFD, fCHSP) is the greatest common divisor of the PFD
frequency and the channel spacing frequency.
7. Calculate FRAC2 by the following equation:
FRAC2 = [(N INT) 224 FRAC1)] MOD2
(5)
Rev. A | Page 16 of 38
Data Sheet
ADF5355
(6)
where:
fPFD is the frequency of the phase frequency detector.
fCHSP is the desired channel spacing.
GCD is a greatest common divisor function.
THREE-STATE OUTPUT
DVDD
DGND
R DIVIDER OUTPUT
INT N Mode
N DIVIDER OUTPUT
Q1
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 34 is a simplified schematic of
the phase frequency detector. The PFD includes a fixed delay
element (INT = 1.6 ns, FRAC = 2.6 ns) that sets the width of the
anti-backlash pulse. This pulse ensures that there is no dead
zone in the PFD transfer function and provides a consistent
reference spur level. Set the phase detector polarity to positive
on this device because of the positive tuning of the VCO.
D1
DGND
12714-029
RESERVED
UP
U1
CLR1
DELAY
U3
CHARGE
PUMP
CP
CLR2
DOWN
D2
Q2
U2
IN
12714-028
HIGH
MUXOUT
+IN
CONTROL
R Counter
HIGH
MUX
C4
0
0
0
0
0
0
0
0
1
1
1
1
1
Rev. A | Page 17 of 38
C3
0
0
0
0
1
1
1
1
0
0
0
0
1
Control Bits
C2
0
0
1
1
0
0
1
1
0
0
1
1
0
C1
0
1
0
1
0
1
0
1
0
1
0
1
0
Register
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Register 8
Register 9
Register 10
Register 11
Register 12
ADF5355
Data Sheet
50
45
PROGRAM MODES
VCO
The VCO core in the ADF5355 consists of four separate VCOs,
each of which uses 256 overlapping bands, which allows the
device to cover a wide frequency range without large VCO
sensitivity (KV) and without resultant poor phase noise and
spurious performance.
The correct VCO and band are chosen automatically by the
VCO and band select logic whenever Register 0 is updated and
automatic calibration is enabled. The VCO VTUNE is disconnected
from the output of the loop filter and is connected to an internal
reference voltage.
The R counter output is used as the clock for the band select
logic. After band selection, normal PLL action resumes. The
nominal value of KV is 15 MHz/V when the N divider is driven
from the VCO output, or the KV value is divided by D. D is
the output divider value if the N divider is driven from the
RF output divider (chosen by programming Bits[D23:D21] in
Register 6).
35
LINEAR
TREND LINE
30
AVERAGE
VCO SENSITIVITY
25
20
15
10
5
0
3.3
3.8
4.3
4.8
5.3
5.8
FREQUENCY (GHz)
6.3
6.8
12714-133
40
OUTPUT STAGE
The RFOUTA+ and RFOUTA pins of the ADF5355 connect to
the collectors of an NPN differential pair driven by buffered
outputs of the VCO, as shown in Figure 37. In this scheme,
the ADF5355 contains internal 50 resistors connected to
the VRF pin. To optimize the power dissipation vs. the output
power requirements, the tail current of the differential pair is
programmable using Bits[D2:D1] in Register 6. Four current
levels can be set. These levels give approximate output power
levels of 4 dBm, 1 dBm, +2 dBm, and +5 dBm, respectively.
Levels of 4 dBm, 1 dBm, +2 dBm can be achieved using a
50 resistor to VRF and ac coupling into a 50 load. A +5 dBm
level requires an external shunt inductor to VRF. Note that an
inductor has a narrower operating frequency than a 50
resistor. For accurate power levels, refer to the Typical
Performance Characteristics section. Add an external shunt
inductor to provide higher power levels; however, this is less
wideband than the internal bias only. Terminate the unused
complementary output with a circuit similar to the used output.
VRF
VRF
50
50
RFOUTA
RFOUTA+
BUFFER/
DIVIDE BY
1/2/4/8/
16/32/64
12714-032
VCO
2 VCO
MUX
RFOUTB
Rev. A | Page 18 of 38
12714-033
Data Sheet
ADF5355
RFOUTB directly connects to the VCO, and it can be muted but
only by using the RFOUTB bit (Bit DB10) in Register 6.
RFOUTA Off
78 mA
RFOUTA = 4 dBm
78 mA
RFOUTA = 1 dBm
78 mA
RFOUTA = +2 dBm
78 mA
RFOUTA = +5 dBm
78 mA
79.8 mA
87.8 mA
97.1 mA
104.9 mA
109.8 mA
113.6 mA
115.9 mA
101.3 mA
110.1 mA
119.3 mA
127.1 mA
131.8 mA
135.5 mA
137.8 mA
111.9 mA
120.6 mA
130.1 mA
137.8 mA
142.7 mA
146.5 mA
148.9 mA
122.7 mA
131.9 mA
141.6 mA
149.2 mA
154.1 mA
157.8 mA
160.1 mA
132.8 mA
141.9 mA
152.1 mA
159.7 mA
164.6 mA
168.4 mA
170.8 mA
Rev. A | Page 19 of 38
ADF5355
Data Sheet
REGISTER MAPS
AUTOCAL
PRESCALER
REGISTER 0
RESERVED
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
0
PR1
AC1
N15
N16
N14
N13
N12
N11
N10
N9
N8
N7
DB8
DB7
DB6
DB5
DB4
N5
N4
N3
N2
N1
N6
DB3
DB2
C4(0) C3(0)
DB1
DB0
C2(0) C1(0)
REGISTER 1
RESERVED
CONTROL
BITS
DBR 1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
F24
F23
F22
F21
F20
F19
F18
F17
F16
F15
F14
F13
F12
F11
F10
F9
F8
F7
F6
DB7 DB6
DB5 DB4
DB3
F4
F2
F5
F3
F1
DB2
DB1
DB0
REGISTER 2
DBR 1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
F14
F13
F12
F11
F10
F9
F8
F7
F6
F5
CONTROL
BITS
F4
F3
F2
M14
F1
M13
M12
M11
M10
M9
M8
M7
M6
DB8
DB7
DB6
DB5
DB4
M5
M4
M3
M2
M1
DB3
DB2
DB1
DB0
CONTROL
BITS
PA1
P24
P23
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
DB7 DB6
P6
P5
P4
DB5 DB4
DB3
P3
P2
P1
COUNTER
RESET
PR1
PD
POLARIT Y
SD1
MUX LOGIC
REF MODE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
CP THREESTATE
DBR 1
PD
PHASE
ADJUST
PHASE
RESYNC
SD LOAD
RESET
RESERVED
REGISTER 3
DB2
DB1
DB0
CONTROL
BITS
DBR 1
DOUBLE BUFF
MUXOUT
RDIV2
RESERVED
REFERENCE
DOUBLER DBR 1
REGISTER 4
DBR 1
10-BIT R COUNTER
CURRENT
SETTING
DBR 1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
M3
M2
M1
RD2
RD1
R10
R9
R8
R7
R6
R5
R4
R3
R2
D1
R1
CP4
CP3
CP2
CP1
U6
DB7 DB6
U5
U4
U3
DB5 DB4
DB3
U2
U1
DB2
DB1
DB0
REGISTER 5
CONTROL
BITS
DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
RFOUTA+/
RFOUTA
RESERVED
RF
OUTPUT
POWER
DB3
DB2
DB1
DB0
1DBR
2DBB
RFOUTB
MTLD
RF
DIVIDER SELECT 2
RESERVED
FEEDBACK
SELECT
NEGATIVE
BLEED
RESERVED
RESERVED
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
BL10
BL9
D13
D12
D11
D10
BL8
BL7
BL6
BL5
BL4
BL3
BL2
BL1
D8
D7
D3
D2
D1
CONTROL
BITS
DB3
DB2
DB1
DB0
DB31
GATED
BLEED
RESERVED
REGISTER 6
Data Sheet
ADF5355
LD MODE
LD
CYCLE
COUNT
RESERVED
FRAC-N LD
PRECISION
RESERVED
LOL MODE
LE SYNC
REGISTER 7
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
0
LE
LD4
LD5
LOL LD3
CONTROL
BITS
DB3
DB2
DB1
DB0
REGISTER 8
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
DB7 DB6
DB5 DB4
1
DB3
DB2
DB1
DB0
REGISTER 9
TIMEOUT
SYNTHESIZER
LOCK TIMEOUT
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
VC8
VC7
VC6
VC5
VC4
VC3
VC2
VC1
TL10
TL9
TL8
TL7
TL6
TL5
TL4
TL3
TL2
TL1
AL5
AL4
AL3
AL2
AL1
SL5
CONTROL
BITS
DB7 DB6
DB5 DB4
SL4
SL2
SL3
DB3
DB2
DB1
DB0
ADC
CLOCK DIVIDER
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
AD8
AD7
AD6
AD5
AD4
DB7 DB6
AD3 AD2
AD1
ADC ENABLE
ADC
CONVERSION
REGISTER 10
DB5 DB4
CONTROL
BITS
DB3
DB2
DB1
DB0
REGISTER 11
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
DB7 DB6
DB5 DB4
0
DB3
DB2
DB1
DB0
REGISTER 12
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
Rev. A | Page 21 of 38
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
12714-035
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
P16
CONTROL
BITS
RESERVED
RESYNC CLOCK
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
0
AC1
PR1
CONTROL
BITS
N16
N15
N14
N13
N12
N11
N10
N9
N8
N7
N6
DB8
DB7
DB6
DB5
DB4
N5
N4
N3
N2
N1
PR1
PRESCALER
N16
N15
...
N5
N4
N3
N2
N1
4/5
...
NOT ALLOWED
8/9
...
NOT ALLOWED
...
NOT ALLOWED
...
...
...
NOT ALLOWED
DB3
DB2
DB1
DB0
...
23
AC1
VCO
AUTOCAL
...
24
...
...
DISABLED
...
65533
ENABLED
...
65534
...
65535
12714-036
RESERVED
PRESCALER
Data Sheet
AUTOCAL
ADF5355
REGISTER 0
Prescaler Value
Control Bits
The dual modulus prescaler (P/P + 1), along with the INT,
FRACx, and MODx counters, determines the overall division
ratio from the VCO output to the PFD input. The PR1 bit
(Bit DB20) in Register 0 sets the prescaler value.
Reserved
Operating at CML levels, the prescaler takes the clock from the
VCO output and divides it down for the counters. It is based on
a synchronous 4/5 core. When the prescaler is set to 4/5, the
maximum RF frequency allowed is 7 GHz. The prescaler limits
the INT value; therefore, if P is 4/5, NMIN is 23, and if P is 8/9,
NMIN is 75.
Rev. A | Page 22 of 38
Data Sheet
ADF5355
CONTROL
BITS
DBR 1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
F24
F23
F22
F21
F20
F19
F18
F17
F16
F15
F14
F13
F12
F11
F10
F9
F8
F7
F6
F24
F23
..........
F2
F1
..........
..........
..........
..........
..........
..........
..........
..........
16777212
..........
16777213
..........
16777214
.........
16777215
F5
DB7 DB6
F4
F3
DB5 DB4
DB3
F2
F1
DB2
DB1
DB0
12714-037
RESERVED
REGISTER 1
Control Bits
Reserved
Bits[DB31:DB28] are reserved and must be set to 0.
Rev. A | Page 23 of 38
ADF5355
Data Sheet
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
F14
F13
F12
F11
F10
F9
F8
F7
F6
F5
F4
CONTROL
BITS
F3
F2
M14
F1
M13
M12
M11
M10
M9
M8
M7
DB8
DB7
DB6
DB5
DB4
M6
M5
M4
M3
M2
M1
DB3
DB2
DB1
DB0
F14
F13
..........
F2
F1
FRAC2 WORD
M14
M13
..........
M2
M1
..........
..........
NOT ALLOWED
..........
..........
NOT ALLOWED
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
16381
..........
16380
..........
16382
..........
16381
..........
16382
..........
16382
.........
16383
.........
16383
12714-038
DBR 1
REGISTER 2
Control Bits
Rev. A | Page 24 of 38
ADF5355
PHASE
ADJUST
PHASE
RESYNC
SD LOAD
RESET
RESERVED
Data Sheet
CONTROL
BITS
DBR 1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
SD1
PR1
PA1
PA1
PR1
SD1
P24
P23
P22
P21
P20
P19
PHASE
ADJUST
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P24
P23
..........
P2
P1
DISABLED
..........
ENABLED
..........
..........
..........
..........
..........
..........
..........
16777212
..........
16777213
..........
16777214
.........
16777215
PHASE
RESYNC
DISABLED
ENABLED
SD LOAD
RESET
ON REGISTER0 UPDATE
DISABLED
P7
P6
P5
P4
P3
DB5 DB4
DB3
P2
P1
DB2
DB1
DB0
12714-039
DB7 DB6
REGISTER 3
Control Bits
With Bits[C4:C1] set to 0011, Register 3 is programmed. Figure 44
shows the input data format for programming this register.
Reserved
Phase Adjust
SD Load Reset
When writing to Register 0, the - modulator resets. For
applications in which the phase is continually adjusted, this may
not be desirable; therefore, in these cases, the - reset can be
disabled by writing a 1 to the SD1 bit (Bit DB30).
Phase Resync
To use the phase resynchronization feature, the PR1 bit (Bit DB29)
must be set to 1. If unused, the bit can be programmed to 0. The
phase resync timer must also be used in Register 12 to ensure
that the resynchronization feature is applied after PLL has settled to
the final frequency. If the PLL has not settled to the final frequency,
phase resync may not function correctly. Resynchronization is
useful in phased array and beam forming applications. It ensures
repeatability of output phase when programming the same
frequency. In phase critical applications that use frequencies
requiring the output divider (<3400 MHz), it is necessary to
feed the N divider with the divided VCO frequency as distinct
Rev. A | Page 25 of 38
COUNTER
RESET
CP THREESTATE
DBR 1
PD
CURRENT
SETTING
PD
POLARITY
DBR 1
10-BIT R COUNTER
REF MODE
DOUBLE BUFF
DBR 1
RDIV2
MUXOUT
RESERVED
MUX LOGIC
Data Sheet
REFERENCE
DOUBLER DBR 1
ADF5355
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
0
M3
M2
M1
RD1
R10
RD2
REFERENCE
DOUBLER
DISABLED
ENABLED
R9
R8
R7
R6
R5
R4
R3
R1
1
..........
..........
..........
..........
..........
1020
R DIVIDER (R)
..........
1021
..........
1022
..........
1023
M3
M2
M1
OUTPUT
THREE-STATE OUTPUT
DVDD
DGND
R DIVIDER OUTPUT
N DIVIDER OUTPUT
RESERVED
U6
U5
U4
U3
U2
U1
DB3
DB2
DISABLED
ENABLED
DIFF
ENABLED
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CP2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CP1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ICP (mA)
5.1k
0.31
0.63
0.94
1.25
1.56
1.88
2.19
2.50
2.81
3.13
3.44
3.75
4.06
4.38
4.69
5.00
U2
DB0
C1(0)
COUNTER
RESET
U1
0
CP3
DB1
REFIN
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CP1
SINGLE
ENABLED
R2
CP2
U6
..........
CP3
CP4
..........
CP4
DISABLED
DISABLED
D1
DOUBLE BUFFERED
REGISTER 6, BITS[DB23:DB21]
REFERENCE DIVIDE BY 2
R9
R1
D1
RD1
R2
R10
1DBR
RD2
CP
THREE-STATE
U5
LDP
1.8V
DISABLED
3.3V
ENABLED
U4
PD POLARITY
U3
POWER DOWN
NEGATIVE
DISABLED
POSITIVE
ENABLED
12714-040
CONTROL
BITS
REGISTER 4
Control Bits
With Bits[C4:C1] set to 0100, Register 4 is programmed. Figure 45
shows the input data format for programming this register.
Reserved
Bits[DB31:DB30] are reserved and must be set to 0.
MUXOUT
RDIV2
Setting the RDIV2 bit (Bit DB25) to 1 inserts a divide by 2,
toggle flip-flop between the R counter and PFD, which extends
the maximum reference frequency input rate. This function
provides a 50% duty cycle signal at the PFD input.
10-Bit R Counter
Reference Doubler
Setting the RD2 bit (Bit DB26) to 0 feeds the reference frequency
signal directly to the 10-bit R counter, disabling the doubler.
Setting this bit to 1 multiplies the reference frequency by a factor
of 2 before feeding it into the 10-bit R counter. When the doubler
is disabled, the REFIN falling edge is the active edge at the PFD
input to the fractional synthesizer. When the doubler is enabled,
both the rising and falling edges of the reference frequency become
active edges at the PFD input.
Double Buffer
The D1 bit (Bit DB14) enables or disables double buffering of
the RF divider select bits (Bits[DB23:DB21]) in Register 6. The
Program Modes section explains how double buffering works.
Rev. A | Page 26 of 38
Data Sheet
ADF5355
Reference Mode
Level Select
Setting the U2 bit (Bit DB5) to 1 puts the charge pump into
three-state mode. Set DB5 to 0 for normal operation.
The U4 bit (Bit DB7) sets the phase detector polarity. When a
passive loop filter or a noninverting active loop filter is used, set
DB7 to 1 (positive). If an active filter with an inverting
characteristic is used, set this bit to 0 (negative).
Counter Reset
The U1 bit (Bit DB4) resets the R counter, N counter, and VCO
band select of the ADF5355. When DB4 is set to 1, the RF
synthesizer N counter, R counter, and VCO band select are reset.
For normal operation, set DB4 to 0.
Power-Down
The U3 bit (Bit DB6) sets the programmable power-down mode.
Setting DB6 to 1 performs a power-down. Setting DB6 to 0 returns
the synthesizer to normal operation. In software power-down
mode, the ADF5355 retains all information in its registers. The
register contents are only lost if the supply voltages are removed.
REGISTER 5
The bits in Register 5 are reserved and must be programmed as
described in Figure 46, using a hexadecimal word of 0x00800025.
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
0
Rev. A | Page 27 of 38
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
12714-041
CONTROL
BITS
RESERVED
RESERVED
RFOUTA+/
RFOUTA
MTLD
RF
OUTPUT
POWER
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
0
BL10
BL9
D13
D12
D11
D10
BL8
BL7
BL6
BL5
BL4
BL3
BL2
BL1
D8
D7
D3
D2
FEEDBACK
D13 SELECT
0
1
DIVIDED
FUNDAMENTAL
DISABLED
ENABLED
DISABLED
ENABLED
D12
D11
D10
RF DIVIDER SELECT
D8
MUTE TILL
LOCK DETECT
MUTE DISABLED
16
MUTE ENABLED
32
64
BL8
1BITS[DB23:DB21]
D7
RFOUTB
ON
OFF
BL7
..........
BL2
BL1
..........
(3.75A)
..........
(7.5A)
..........
..........
..........
..........
252
(945A)
..........
253
(948.75A)
..........
254
(952.5A)
..........
255
(956.25A)
DB3
DB2
DB1
DB0
D1
D2
D1
OUTPUT POWER
4dBm
1dBm
+2dBm
+5dBm
D3
RF OUTA+/RFOUTA
DISABLED
ENABLED
BLEED CURRENT
ARE BUFFERED BY A WRITE TO REGISTER 0 WHEN THE DOUBLE BUFFER BIT, BIT DB14 OF REGISTER 4, IS ENABLED.
12714-042
RF DIVIDER
SELECT 1
RFOUTB
RESERVED
RESERVED
FEEDBACK
SELECT
Data Sheet
NEGATIVE
BLEED
GATED
BLEED
RESERVED
ADF5355
REGISTER 6
Reserved
Control Bits
Reserved
Bit DB31 is reserved and must be set to 0.
Gated Bleed
Bleed currents can be used for improving phase noise and spurs;
however, due to a potential impact on lock time, the gated bleed
bit, BL10 (Bit DB30), if set to 1, ensures bleed currents are not
switched on until the digital lock detect asserts logic high. Note
that this function requires digital lock detect to be enabled.
Negative Bleed
Use of constant negative bleed is recommended for most
fractional-N applications because it improves the linearity of
the charge pump, leading to lower noise and spurious signals than
leaving it off. To enable negative bleed, write 1 to BL9 (Bit DB29),
and to disable negative bleed, write 0 to BL9 (Bit DB29).
Feedback Select
D13 (Bit DB24) selects the feedback from the output of the
VCO to the N counter. When D13 is set to 1, the signal is taken
directly from the VCO. When this bit is set to 0, the signal is
taken from the output of the output dividers. The dividers
enable coverage of the wide frequency band (3.4 GHz to 6.8 GHz).
When the divider is enabled and the feedback signal is taken
from the output, the RF output signals of two separately
configured PLLs are in phase. Divided feedback is useful in
some applications where the positive interference of signals is
required to increase the power.
Divider Select
D12 to D10 (Bits[DB23:DB21]) select the value of the RF output
divider (see Figure 47).
Rev. A | Page 28 of 38
Data Sheet
ADF5355
RF Output B Enable
Tests have shown that the optimal bleed set is the following:
Reserved
Reserved
Bit DB12 is reserved and must be set to 0.
RF Output A Enable
D3 (Bit DB6) enables or disables the primary RF output
(RFOUTA+/RFOUTA). If DB6 is set to 0, the primary RF output
is disabled. If DB6 is set to 1, the primary RF output is enabled.
Output Power
D2 and D1 (Bits[DB5:DB4]) set the value of the primary RF
output power level (see Figure 47).
Rev. A | Page 29 of 38
LD
CYCLE
COUNT
RESERVED
LD MODE
LOL MODE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
0
LE
LD5
LD4
LOL LD3
LE SYNCHRONIZATION
DB3
DB2
DB1
DB0
LD1
LE
CONTROL
BITS
FRACTIONAL-N
INTEGER-N (2.9ns)
LD3
LD2
FRACTIONAL-N LD PRECISION
5.0ns
6.0ns
8.0ns
12.0ns
DISABLED
DISABLED
LE SYNCED TO REFIN
ENABLED
LD5
LD4
1024
2048
4096
8192
12714-043
RESERVED
FRAC-N LD
PRECISION
Data Sheet
LE SYNC
ADF5355
REGISTER 7
Control Bits
Set the LOL mode bit (Bit DB7) to 1 when the application is a
fixed frequency application in which the reference (REFIN) is
likely to be removed, such as a clocking application. The standard
lock detect circuit assumes that REFIN is always present; however,
this may not be the case with clocking applications. To enable this
functionality, set DB7 to 1.
Reserved
Bits[DB31:DB29] are reserved and must be set to 0. Bit DB28 is
reserved and must be set to 1. Bits[DB27:DB26] are reserved
and must be set to 0.
LE Sync
When set to 1, Bit DB25 ensures that the load enable (LE) edge
is synchronized internally with the rising edge of reference
input frequency. This synchronization prevents the rare event of
reference and RF dividers loading at the same time as a falling edge
of the reference frequency, which can lead to longer lock times.
Reserved
Bits[DB24:DB10] are reserved and must be set to 0.
Rev. A | Page 30 of 38
Data Sheet
ADF5355
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
DB7 DB6
DB5 DB4
1
DB3
DB2
DB1
DB0
12714-044
CONTROL
BITS
RESERVED
SYNTHESIZER
LOCK TIMEOUT
TIMEOUT
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
VC8
VC7
VC6
VC5
VC4
VC3
VC2
VC1
TL10
TL9
TL8
TL7
TL6
TL5
TL4
TL3
TL2
TL1
AL5
AL4
AL3
AL2
..........
TL2
TL1
VC7
..........
VC2
VC1
..........
..........
..........
..........
..........
..........
252
..........
253
..........
254
..........
255
VC8
TIMEOUT
..........
..........
..........
..........
..........
..........
1020
..........
1021
..........
1022
..........
1023
SL4
SL3
DB3
..........
SL2
SL1
..........
..........
..........
..........
..........
..........
28
..........
29
..........
30
..........
31
ALC WAIT
AL4
..........
AL2
AL1
..........
..........
..........
..........
..........
..........
28
..........
29
..........
30
..........
31
DB2
DB1
DB0
SL2
SL4
AL5
SL5
SL5
TL9
TL10
AL1
CONTROL
BITS
SLC WAIT
12714-045
REGISTER 8
Timeout
REGISTER 9
AL5 to AL1 (Bits[DB13:DB9]) set the timer value used for the
automatic level calibration of the VCO. This function combines
the PFD frequency, the timeout variable, and ALC wait variable.
Choose the ALC such that the following equation is always
greater than 50 s.
Control Bits
With Bits[C4:C1] set to 1001, Register 9 is programmed. Figure 50
shows the input data format for programming this register.
ADC
CLOCK DIVIDER
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
AD8
AD8
AD7
AD6
AD5
AD4
DB7 DB6
AD3 AD2
AD7
..........
AD2
..........
..........
..........
..........
..........
..........
252
..........
253
..........
254
..........
255
DB5 DB4
CONTROL
BITS
DB3
DB2
DB1
DB0
AD1
AE1
ADC
DISABLED
ENABLED
AE2
ADC CONVERSION
DISABLED
ENABLED
12714-047
RESERVED
ADC ENABLE
Data Sheet
ADC
CONVERSION
ADF5355
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
DB7 DB6
0
DB5 DB4
0
DB3
DB2
DB1
DB0
12714-048
CONTROL
BITS
RESERVED
REGISTER 10
Control Bits
Reserved
ADC Enable
AE1 (Bit DB4), when set to 1, powers up the ADC for the
temperature dependent VTUNE calibration. It is recommended to
always use this function.
REGISTER 11
The bits in this register are reserved and must be programmed
as described in Figure 52, using a hexadecimal word of
0x0061300B.
Rev. A | Page 32 of 38
Data Sheet
ADF5355
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
P15
P14
P13
P12
P11
P10
P8
P9
P7
P6
P5
P4
P3
P2
P1
P16
P15
...
P5
P4
P3
P2
P1
...
NOT ALLOWED
...
1/NORMAL OPERATION
...
...
...
...
22
...
23
...
24
...
...
...
65533
...
65534
...
65535
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
12714-049
P16
CONTROL
BITS
RESERVED
REGISTER 12
Control Bits
Reserved
Bits[DB15:DB4] are reserved. Bit DB10 and Bit DB4 must be set
to 1, and all other bits in this range must be set to 0.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Register 12
Register 11
Register 10
Register 9
Register 8
Register 7
Register 6
Register 5
Register 4
Register 3
Register 2
Register 1
Register 0
Rev. A | Page 33 of 38
ADF5355
Data Sheet
RFOUT = INT +
FRAC2
MOD2 ( f )/ RF Divider
PFD
MOD1
FRAC1 +
(7)
where:
RFOUT is the RF output frequency.
INT is the integer division factor.
FRAC1 is the fractionality.
FRAC2 is the auxiliary fractionality.
MOD1 is the fixed 24-bit modulus.
MOD2 is the auxiliary modulus.
RF Divider is the output divider that divides down the VCO
frequency.
fPFD = REFIN ((1 + D)/(R (1 + T)))
From Equation 8,
fPFD = (122.88 MHz (1 + 0)/2) = 61.44 MHz
RFOUT
N
DIVIDER
12714-148
PFD
(8)
where:
REFIN is the reference frequency input.
D is the REFIN doubler bit.
R is the REF reference division factor.
T is the reference divide by 2 bit (0 or 1).
fPFD
where:
INT = 68
FRAC1 = 13,019,817
MOD2 = 1536
FRAC2 = 1024
RF Divider = 2
OPTIMIZING JITTER
For lowest jitter applications, use the highest possible PFD
frequency to minimize the contribution of in-band noise from
the PLL. Set the PLL filter bandwidth such that the in-band noise
of the PLL intersects with the open-loop noise of the VCO,
minimizing the contribution of both to the overall noise.
Use the ADIsimPLL design tool for this task.
Rev. A | Page 34 of 38
(9)
Data Sheet
ADF5355
SPUR MECHANISMS
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop can cause a problem. Feedthrough of low
levels of on-chip reference switching noise, through the
prescaler back to the VCO, can result in reference spur levels
as high as 80 dBc.
ALC Wait = 30
Synthesizer Lock Timeout = 12
Finally, ALC Wait > (50 s fPFD)/Timeout, is rearranged for
Timeout = Ceiling((fPFD 50 s)/ALC Wait)
Timeout = Ceiling((61.44 MHz 50 s)/30) = 103
LOCK TIME
The PLL lock time divides into a number of settings. All of
these settings are modeled in the ADIsimPLL design tool.
Much faster lock times than those detailed in this data sheet
are possible; contact Analog Devices for more information.
By combining
The total lock time for changing frequencies is the sum of the
four separate times (synthesizer lock, VCO band selection, ALC
timeout, and PLL settling time) and is all modeled in the
ADIsimPLL design tool.
Rev. A | Page 35 of 38
ADF5355
Data Sheet
APPLICATIONS INFORMATION
POWER SUPPLIES
For the 3.3 V supply pins, use one or two ADM7150 regulators.
Figure 55 shows the recommended connections.
VOUT = 3.3V
VIN
ON
100nF
VOUT
COUT
1F
ADM7150
EN
100nF
LOCK
DETECT
OFF
REF
BYP
CBYP
1F
17
VREG
REF_SENSE
1nF
CREG
10F
GND
1nF
FREF IN
27
16
26
10
25
32
10pF
29 REF A
IN
1nF
RFOUTB 14
100
FREF IN
30
VOUT
28 REF INB
1nF
7.5nH
7.5nH
1 CLK
1nF
VIN = 6.0V
VOUT = 5.0V
VIN
CIN
1F
EN
REF
BYP
CBYP
1F
CREG
10F
COUT
1F
ADM7150
ON
OFF
VOUT
VREG
REF_SENSE
GND
2 DATA
RFOUTA+ 11
3 LE
ADF5355
RFOUTA 12
1nF
VTUNE 20
430
CPOUT 7
22 RSET
4.7k
1F
33nF
6800pF
68
31
21
15
19
10pF
Rev. A | Page 36 of 38
23
24
0.1F 10pF
0.1F 10pF
0.1F
12714-050
CIN
1F
Data Sheet
ADF5355
OUTPUT MATCHING
The low frequency output can simply be ac-coupled to the next
circuit, if desired; however, if higher output power is required,
use a pull-up inductor to increase the output power level.
VRF
7.5nH
12714-051
50
100pF
RFOUTA+
Rev. A | Page 37 of 38
ADF5355
Data Sheet
OUTLINE DIMENSIONS
0.30
0.25
0.18
32
25
24
0.50
BSC
*3.75
3.60 SQ
3.55
EXPOSED
PAD
17
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
8
16
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
PIN 1
INDICATOR
BOTTOM VIEW
0.25 MIN
08-16-2010-B
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
ORDERING GUIDE
Model 1
ADF5355BCPZ
ADF5355BCPZ-RL7
EV-ADF5355SD1Z
1
Temperature Range
40C to +85C
40C to +85C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board
Rev. A | Page 38 of 38
Package Option
CP-32-12
CP-32-12