MING

Branc
h:
COM
PUTE
R
SCIE
NCE
AND
ENGI
NEER
ING
Year
Sessio:
I n No

SESSION PLAN
Sub Name : COMPUTER ORGANIZATION
Branch: ELECTRICAL AND ELECTRONICS ENGINEERING
Year : IV
Semester: I
Class: B.Tech

unit
no

Topic

Sub Topic

Lecture
No

Time required
to deliver
lecture (S) in
min

UNIT-I::BASIC STRUCTURE OF COMPUTERS

1
Semes
ter: I 2

1 Introduction

Introduction to Computer

L1

50

Computer Types

micro,mini,mainframe and super

computers

L2

30

Functional unit

Input,output,memory,ALU and
control unit

L3

20

Basic Operational concepts

Basic Operational concepts

L4

50

Bus structures

single and multi bus structures

L5

50

Software

system software and application

L6

50
30
50

4
Class:
B.Tech
5

7
8

1 Performance
1 Data Representation

Performance
Fixed Point Representation.

L7
L9

Floating Point Representation.

L10

50

10

Floating Point arithmetic operations L11

50

UNIT-II::REGISTER TRANSFER LANGUAGE AND MICROOPERATIONS

10

2 Register transfer language

Register transfer language

L1

50

11

2 Register transfer

Computer registers

L2

30

Computer registers, Computer

instructions

L3

20

12

2 Bus and Memory transfer

Three state bus buffer,memory

transfer

L4

50

13

2 Arithmetic Micro operations

Binary adder,addersubtractor,incrementer

L5

50

14

2 Logic Micro Operations

Hardware
Implementation,applications

L6

50

15

2 Shift Micro Operations

hardware
Implementation,left,right,circular

L7

50

16

2 Arithmetic Logic Shift Unit

ALU Operation

L8

50

17

2 Instruction Codes

Stored program
organization,Indirect address

L9

50

18

2 Computer Instructions

L10

50

19

2 Instruction Cycle

Fetch and decode,type of

instruction

L11

20

20

2 Computer Registers

common bus system

L12

30

L1

50

L2

50

L3

50

Instruction set

UNIT-III:INSTRUCTIONS AND ADDRESSING MODES

21

AND to AC,ADD to

22

Memory reference instructions AC,LDA,STA,BUN,BSA,ISZ

Input output configuration
3 Input output instructions

23

3 Data transfer and Manipulation Manipulation

Data Transfer Instructions,data

24
25

3 Program control Instructions

3 Stack Organization

Status bit conditions,sub routine

26

27

3 Addressing modes

28

3 RISC

Instruction Formats

UNIT-IV
29
4 Control memory

L4
L5

50
50

Three address,2 address,one and

zero address instructions

L6

50

Examples of addressing modes

L7

50

L8

50

Control Memory
Conditional Branching,Mapping of
Instruction

L5

50

L6

50

Register stack,Memory stack

Characteristics of RISC

30

4 Address Sequencing

31

4 Micro Program Example

Computer configuration,Micro
Instruction format

L7

50

32
33
34

4 Design of Control unit

4 Hardwired Control
4 Micro Programmed control

Design of Control unit

Hardwired Control
Micro Programmed control

L8
L9
L10

50
50
50

Basic concepts-semi conductor

memories

L1

50

UNIT-V:: THE MEMORY SYSTEM

35

36

RAM memories

L2

50

37

ROM- Introduction

L3

50

38
39
40
41
42

5
5
5
5
5

ROM memories

L4
L5
L6
L7
L8

50
50
50
50
50

THE MEMORY SYSTEM

Cache memories
Performance considerations
Virtual memories
Secondary storage

UNIT-VI INPUT-OUTPUT ORGANIZATION

43

6 INPUT-OUTPUT ORGANIZATION Peripheral devices

6
Input-output Interfaces
6
Asynchronous data transfer

L1
L2
L3

20
30
20

Modes of transfer

L4

30

45

Priority Interrupt ,DMA

L5

50

46

Input-Output processor

L6

20

Serial communication
Introduction to peripheral
component
PCI
bus
Introduction
to standard serial
protocol-RS 232

L7

30

L8
L9
L10
L11

30
20
50
50

44

47
48
49

6
6
6
6

USB,IEEE 1394

UNIT-VII PIPELINE AND VECTOR PROCESSING

50

7 PIPELINE AND VECTOR PROParallel processing

L1

50

51

pipelining

L2

50

52
53

Arithmetic pipeline

Instruction pipeline

L3
L4

50
50

54

RISC pipeline

L5

20

Vector processing

L6

30

Array processors

L7

50

L1
L2
L3

30
20
50

L4

50

55

UNIT-VIII MULTI PROCESSORS

56
8 MULTI PROCESSORS
Charestrics of multiprocessors
8
Interconnection structures
57
8
Inter processor arbitration
58

Inter processor communication &

synchronization

59
60
61

8
8
8

Cache coherence
Shared memory
Multiprocessors

L5
L6
L7

Prepared by

Approved
by

K.Suman
CSE
Asst.Professor
25/7/2015

Dr.P.Sriniv
asulu
CSE
HOD
25/7/2015

Signature
Name
Department
Designation
Date

50
50
50

SYLLABUS COVERAGE REPORT

Date

unit no

Session
No

Date

Topics

unit no

Time
required
to
Sub-topic Lecture No deliver
lecture
(S)
Minutes

Session No

Topics

Time Taken
to
deliver
lecture(S)

Sub-topic

variance

Time

Topic

Time
required
to
deliver
lecture (S)
Lecture No Minutes

Session

Reason
for
variance

Time
Taken to
deliver
variance
lecture(S)
Time

18/10/13
21/10/13
22/10/13
25/10/13

1
1
1
1

L1
L1
L2
L3

28/10/13

1 L4

Computer Computer Defin

L1
Computer Block DiagramL1
Computer Number syst L2
Hardware Hardware ConL3
Software CSoftware ConcL3
Algorithm Algoirthm defi L4

20
30
50
20
30
50

50
50
50
20
30
50

30
20
0
0
0
0

Suggestions
to rectify

Topic

Computer Systems
Computer Systems
Computer Systems
Hardware Concepts
Software Concepts
Algorithm / Pseudo code

SESSION EXECUTION log

Date

unit no

Session No

Topics

Sub-topic

Lecture No

Time
required to
deliver
lecture (S)
Minutes

Time Taken to
deliver lecture(S)