GD75232 PDF

GD75232
MULTIPLE RS-232 DRIVERS AND RECEIVERS

SLLS206C MAY 1995 REVISED JULY 1998
D
D
D
D
D
D
Single Chip With Easy Interface Between

UART and Serial-Port Connector of IBM
PC/AT and Compatibles
Meets or Exceeds the Requirements of
ANSI Standard TIA/EIA-232-F and ITU
Recommendation V.28
Designed to Support Data Rates up to
120 kbit/s
Pinout Compatible With SN75C185 and
SN75185
ESD Protection to 2 kV on Bus Terminals
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB) Packages, and DIPs (N)
DB, DW, OR N PACKAGE

(TOP VIEW)
VDD
RA1
RA2
RA3
DY1
DY2
RA4
DY3
RA5
VSS
20
19
18
17
16
15
14
13
12
10
11
VCC
RY1
RY2
RY3
DA1
DA2
RY4
DA3
RY5
GND
description
The GD75232 combines three drivers and five receivers from TI trade-standard SN75188 and SN75189
bipolar quadruple drivers and receivers, respectively. The pinout matches the flow-through design of the
SN75C185 to decrease the part count, reduce the board space required, and allow easy interconnection of the
UART and serial-port connector of an IBM PC/AT and compatibles. The bipolar circuits and processing of
the GD75232 provide a rugged, low-cost solution for this function at the expense of quiescent power and
external passive components relative to the SN75C185.
The GD75232 complies with the requirements of the TIA/EIA-232-F and ITU (formerly CCITT) V.28 standards.
These standards are for data interchange between a host computer and a peripheral at signaling rates up to
20 kbit/s. The switching speeds of the GD75232 are fast enough to support rates up to 120 kbit/s with lower
capacitive loads (shorter cables). Interoperability at the higher signaling rates cannot be expected unless the
designer has design control of the cable and the interface circuits at both ends. For interoperability at signaling
rates up to 120 kbit/s, use of ANSI TIA/EIA-423-B (ITU V.10) and TIA/EIA-422-B (ITU V.11) standards is
recommended.
The GD75232 is characterized for operation over the temperature range of 0C to 70C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI is a trademark of Texas Instruments Incorporated.
IBM and PC/AT are trademarks of International Business Machines Corporation.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
GD75232
logic symbol
RA1
RA2
RA3
DY1
DY2
RA4
DY3
RA5
logic diagram (positive logic)
19
18
17
16
15
14
13
12
RA1
RY1
RY2
RA2
19
18
17
16
15
14
13
12
RY1
RY2
RY3
RA3
DA1
DA2
DY1
RY3
DA1
RY4
DA3
DY2
RY5
RA4
This symbol is in accordance with ANSI/IEEE Std 91-1984

and IEC Publication 617-12.
DY3
RA5
DA2
RY4
DA3
RY5
schematic (each driver)

To Other Drivers
VDD
11.6 k
9.4 k
Input DAx
75.8
320
4.2 k
GND
To Other
Drivers
10.4 k
3.3 k
68.5
VSS
To Other Drivers
Resistor values shown are nominal.
DALLAS, TEXAS 75265
DYx Output
GD75232
schematic (each receiver)

To Other Receivers
VCC
9 k
5 k
1.66 k
RYx Output
2 k
3.8 k
Input RAx
10 k
GND
To Other Receivers
Resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Supply voltage, VSS (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Input voltage range, VI: Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V to 7 V
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V to 30 V
Driver output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V to 15 V
Receiver low-level output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 60C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to the network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
DALLAS, TEXAS 75265
GD75232
recommended operating conditions

MIN
NOM
MAX
Supply voltage, VDD
7.5
15
Supply voltage, VSS
7.5
15
Supply voltage, VCC
4.5
5.5
High-level input voltage, VIH (driver only)
1.9
Low-level input voltage, VIL (driver only)
0.8
Driver
High level output current,

High-level
current IOH
Low level output current,
current IOL
Low-level
Receiver
0.5
Driver
Receiver
16
Operating free-air temperature, TA
UNIT
70
V
mA
mA
C
supply currents over recommended operating free-air temperature range

PARAMETER
TEST CONDITIONS
All inputs at 1.9 V,
IDD
Supply current from VDD


ISS
No load
No load
Supply current from VSS

ICC
No load
Supply current from VCC
VCC = 5 V,
No load
MAX
VSS = 9 V
VSS = 12 V
15
VDD = 15 V,
VDD = 9 V,
VSS = 15 V
VSS = 9 V
25
VDD = 12 V,
VDD = 15 V,
VSS = 12 V
VSS = 15 V
5.5
VDD = 9 V,
VDD = 12 V,
VDD = 15 V,
VSS = 9 V
VSS = 12 V
15
VSS = 15 V
VSS = 9 V
25
VDD = 9 V,
VDD = 12 V,
VDD = 15 V,
All inputs at 5,
MIN
VDD = 9 V,
VDD = 12 V,
DALLAS, TEXAS 75265
VSS = 12 V
VSS = 15 V
No load
19
UNIT
mA
4.5
mA
9
19
mA
3.2
3.2
mA
3.2
30
mA
GD75232
DRIVER SECTION
electrical characteristics over recommended operating free-air temperature range, VDD = 9 V,
VSS = 9 V, VCC = 5 V (unless otherwise noted)
PARAMETER
VOH
VOL
High-level output voltage
IIH
IIL
High-level input current
IOS(H)
IOS(L)
rO
TEST CONDITIONS
MIN
VIL = 0.8 V,
VIH = 1.9 V,
RL = 3 k,
See Figure 1
RL = 3 k,
See Figure 1
Low-level input current
VI = 5 V,
VI = 0,
High-level short-circuit output current

(see Note 4)
VIL = 0.8 V,
VO = 0,
See Figure 1
4.5
VIH = 2 V,
VO = 0,
VCC = VDD = VSS = 0,
See Figure 1
4.5
Low-level output voltage (see Note 3)
Low-level short-circuit output current
TYP
MAX
7.5
7.5
UNIT
V
See Figure 2
10
See Figure 2
1.6
mA
12
19.5
mA
12
19.5
mA
VO = 2 V to 2 V
300
NOTES: 3. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic
levels only (e.g., if 10 V is maximum, the typical value is a more negative voltage).
4. Output short-circuit conditions must maintain the total power dissipation below absolute maximum ratings.
5. Test conditions are those specified by TIA/EIA-232-F and as listed above.
Output resistance (see Note 5)
switching characteristics, VCC = 5 V, VDD = 12 V, VSS = 12 V, TA = 25C

PARAMETER
tPLH
Propagation delay time,

low- to high-level output
TEST CONDITIONS
RL = 3 k to 7 k,
k
CL = 15 pF,
pF
MIN
TYP
MAX
UNIT
315
500
ns
75
175
ns
See Figure 3
tPHL
Propagation delay time,

high- to low-level output
tTLH
Transition time,, low- to

high-level output
RL = 3 k to 7 k,
CL = 15 pF,
See Figure 3
60
100
ns
RL = 3 k to 7 k,
CL = 2500 pF,
See Figure 3 and Note 6
1.7
2.5
tTHL
Transition time,, highg to

low-level output
RL = 3 k to 7 k,
CL = 15 pF,
See Figure 3
40
75
ns
RL = 3 k to 7 k,
CL = 2500 pF, See Figure 3 and Note 6
1.5
2.5
s
NOTE 6: Measured between 3-V and 3-V points of the output waveform ( TIA/EIA-232-F conditions), all unused inputs are tied either high
or low.
DALLAS, TEXAS 75265
GD75232
RECEIVER SECTION
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See Figure 5
TA = 25C
TA = 0C to 70 C
MIN
TYP
MAX
1.75
1.9
2.3
VIT
IT+
Positive going input threshold voltage

Positive-going
VIT
Vhys
Negative-going input threshold voltage
0.75
Input hysteresis voltage (VIT + VIT)
0.5
VOH
High level output voltage

High-level
IOH = 0.5
0 5 mA
VIH = 0.75 V
Inputs open
VOL
Low-level input voltage
IIH
High level input current

High-level
IOL = 10 mA,
VI = 25 V,
VI = 3 V
See Figure 5
3.6
See Figure 5
0.43
IIL
Low level output current

Low-level
VI = 3 V,
VI = 25 V,
See Figure 5
3.6
VI = 3 V,
See Figure 5
0.43
1.55
2.6
2.3
0.97
1.25
0.2
0.45
2.6
IOS
Short-circuit output current
See Figure 4
All typical values are at TA = 25C, VCC = 5 V, VDD = 9 V, and VSS = 9 V.
8.3
8.3
UNIT
V
V
mA
mA
3.4
12
mA
TYP
MAX
UNIT
107
250
ns
switching characteristics, VCC = 5 V, VDD = 12 V, VSS = 12 V, TA = 25C

PARAMETER
TEST CONDITIONS
tPLH
tPHL
Propagation delay time, low- to high-level output
tTLH
tTHL
Transition time, low- to high-level output
tPLH
tPHL
tTLH
tTHL
Transition time, low- to high-level output
Propagation delay time, high- to low-level output
MIN
42
150
ns
175
350
ns
16
60
ns
Propagation delay time, low- to high-level output
100
160
ns
Propagation delay time, high- to low-level output
60
100
ns
90
175
ns
15
50
ns
CL = 50 pF,
See Figure 6
RL = 5 k,
Transition time, high- to low-level output
CL = 15 pF,
See Figure 6
Transition time, high- to low-level output
DALLAS, TEXAS 75265
RL = 1.5 k,
GD75232
PARAMETER MEASUREMENT INFORMATION

IOS(L)
VDD
VCC
VDD or GND
IOS(H)
VSS or GND
VI
VO
RL = 3 k
VSS
Figure 1. Driver Test Circuit for VOH, VOL, IOS(H), and IOS(L)
VDD
VCC
IIH
VI
IIL
VI
VSS
Figure 2. Driver Test Circuit for IIH and IIL

3V
1.5 V
Input
VDD
Input V
CC
1.5 V
0V
t PHL
Pulse
Generator
CL
(see Note B)
RL
See Note A
90%
Output
VSS
50%
10%
t PLH
50%
10%
t THL
90%
VOH
VOL
t TLH
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A.
B.
The pulse generator has the following characteristics: tw = 25 s, PRR = 20 kHz, ZO = 50 , tr = tf < 50 ns.
CL includes probe and jig capacitance.
Figure 3. Driver Test Circuit and Voltage Waveforms
DALLAS, TEXAS 75265
GD75232
PARAMETER MEASUREMENT INFORMATION

VDD
VCC
VI
VSS
Figure 4. Receiver Test Circuit for IOS

VDD
VCC
IOH
VIT, VI
VOH
VOL
IOL
VSS
Figure 5. Receiver Test Circuit for VIT, VOH, and VOL

4V
Input
VDD
Input
50%
50%
0V
VCC
t PHL
Pulse
Generator
CL
(see Note B)
RL
See Note A
90%
Output
50%
10%
t PLH
50%
10%
VSS
VOLTAGE WAVEFORMS
NOTES: A.
B.
The pulse generator has the following characteristics: tw = 25 s, PRR = 20 kHz, ZO = 50 , tr = tf < 50 ns.
CL includes probe and jig capacitance.
Figure 6. Receiver Propagation and Transition Times
DALLAS, TEXAS 75265
VOH
VOL
t TLH
t THL
TEST CIRCUIT
90%
GD75232
TYPICAL CHARACTERISTICS
DRIVER SECTION
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
VOLTAGE TRANSFER CHARACTERISTICS
VO
VO Output Voltage V
9
6
3
0
9
12
VDD = 9 V, VSS = 9 V
8
4
0
3-k
Load Line
8
12
VOH(VI = 0.8 V)
RL = 3 k
TA = 25C
16
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

VI Input Voltage V
20
16
12
Figure 7
8
4
0
4
8
VO Output Voltage V
1000
VDD = 9 V
VSS = 9 V
RL = 3 k
TA = 25C
IOS(L) (VI = 1.9 V)

SR Slew Rate V/ s
6
3
VDD = 9 V
VSS = 9 V
VO = 0
16
SLEW RATE
vs
LOAD CAPACITANCE
12
9
12
Figure 8
SHORT-CIRCUIT OUTPUT CURRENT

vs
FREE-AIR TEMPERATURE
IIOS
OS Short-Circuit Output Current mA
VOL(VI = 1.9 V)
12
VDD = 6 V, VSS = 6 V
VDD = 9 V
VSS = 9 V
TA = 25C
16
3
6
20
VDD = 12 V, VSS = 12 V
I O Output Current mA
IO
12
100
10
IOS(H) (VI = 0.8 V)
12
10
20
30
40
50
1
60
70
10
TA Free-Air Temperature C
100
1000
10000
CL Load Capacitance pF
Figure 9
Figure 10
DALLAS, TEXAS 75265
GD75232
TYPICAL CHARACTERISTICS
INPUT THRESHOLD VOLTAGE
vs
SUPPLY VOLTAGE
2.4
2.2
1.8
VIT +
V Input Threshold Voltage V

IT
V Input Threshold Voltage V

IT
INPUT THRESHOLD VOLTAGE

vs
1.8
1.6
1.4
1.2
VIT
1
0.8
0.6
0.4
VIT +
1.6
1.4
1.2
1
VIT
0.8
0.6
0.4
0.2
10
20
30
40
50
60
0
2
70
Figure 11
5
6
7
8
VCC Supply Voltage V
10
Figure 12
NOISE REJECTION
6
MAXIMUM SUPPLY VOLTAGE

vs
VCC = 5 V
TA = 25C
See Note A
16
CC = 500 pF
CC = 12 pF
CC = 100 pF
0
10
40
100
400 1000
4000 10000
tw Pulse Duration ns
NOTE A: This figure shows the maximum amplitude of a

positive-going pulse that, starting from 0 V, does not
cause a change of the output level.
14
VDD Maximum Supply Voltage V
Amplitude V
CC = 300 pF
12
10
8
6
4
2
RL 3 k (from each output to GND)
0
0
Figure 13
10
10
20
30
40
50
60
Figure 14
DALLAS, TEXAS 75265
70
GD75232
APPLICATION INFORMATION
Diodes placed in series with the VDD and VSS leads protect the GD75232 in the fault condition in which the device
outputs are shorted to 15 V and the power supplies are at low and provide low-impedance paths to ground (see
Figure 15).
VDD
15 V
VDD
Output
GD75232
GD75232
VSS
VSS
Figure 15. Power-Supply Protection to Meet Power-Off Fault Conditions of TIA/EIA-232-F

12 V
TL16C450
ACE
11
RI 43
12
DTR 37
13
CTS 40
14
SO 13
15
RTS 36
16
SI 11
17
DSR 41
18
DCD 42
19
20
GND
VSS
RY5
RA5
DA3
DY3
RY4
RA4
DA2
DY2
GD75232
DA1
DY1
RY3
RA3
RY2
RA2
RY1
RA1
VCC
VDD
10
5
9
RI
DTR
CTS
TX
RTS
RX
DSR
DCD
C3
TIA/EIA-232-F
DB9S
Connector
C2
C1
6
1
12 V
5V
Figure 16. Typical Connection
DALLAS, TEXAS 75265
11
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TIs standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (CRITICAL
APPLICATIONS). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMERS RISK.
In order to minimize risks associated with the customers applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TIs publication of information regarding any third
partys products or services does not constitute TIs approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated

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GD75232

MULTIPLE RS-232 DRIVERS AND RECEIVERS

Single Chip With Easy Interface Between

DB, DW, OR N PACKAGE

PRODUCTION DATA information is current as of publication date.

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

logic diagram (positive logic)

This symbol is in accordance with ANSI/IEEE Std 91-1984

schematic (each driver)

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

schematic (each receiver)

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

recommended operating conditions

Supply voltage, VDD

Supply voltage, VSS

Supply voltage, VCC

High-level input voltage, VIH (driver only)

Low-level input voltage, VIL (driver only)

High level output current,

Operating free-air temperature, TA

supply currents over recommended operating free-air temperature range

Supply current from VDD

All inputs at 1.9 V,

Supply current from VSS

Supply current from VCC

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

High-level output voltage

High-level input current

Low-level input current

High-level short-circuit output current

Low-level output voltage (see Note 3)

Low-level short-circuit output current

switching characteristics, VCC = 5 V, VDD = 12 V, VSS = 12 V, TA = 25C

Propagation delay time,

Propagation delay time,

Transition time,, low- to

See Figure 3 and Note 6

Transition time,, highg to

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Positive going input threshold voltage

Negative-going input threshold voltage

Input hysteresis voltage (VIT + VIT)

High level output voltage

Low-level input voltage

High level input current

Low level output current

switching characteristics, VCC = 5 V, VDD = 12 V, VSS = 12 V, TA = 25C

Propagation delay time, low- to high-level output

Transition time, low- to high-level output

Transition time, low- to high-level output

Propagation delay time, high- to low-level output

Propagation delay time, low- to high-level output

Propagation delay time, high- to low-level output

Transition time, high- to low-level output

Transition time, high- to low-level output

POST OFFICE BOX 655303

DALLAS, TEXAS 75265