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Basic principles of accurate dynamic

current mirrors
G.Wegrnann
E.A. Vittoz

Indexing t e r m : Electronic circuits, Circuit theory and design, Transients

Abstract: Basic principles and limitations of accurate dynamic current mirrors based on dynamic
analogue techniques are presented. The accuracy
of dynamic current mirrors is independent of the
mismatch of the transistors building up the
mirror, because the same transistor is sequentially
used at the input and the output of the mirror.
Limitations of such dynamic current mirrors and
the influence of clock phase delays are shown
through simulated, analytical and experimental
results. Improvements are proposed that allow the
performance of dynamic current mirrors to be
increased.

and a high output ripple is produced at the output, which


must be filtered out by using external components.
2

Principle of a dynamic current mirror

form 14th December 1989

Figs. la and b show the basic cell building up a dynamic


current mirror [3-7]*. The principle of memorising and
reproducing a current imposed by an external current
source Ii, is the following:
While the switches Sjl and Sj, are closed (Fig. la), the
current source feeds the input current to the diode connected transistor Tj,. During this phase switch Sj3 is
open. After opening sampling switch Sjl, capacitor C j
maintains (memorises) the gate voltage and thus the
drain current of Tjm remains equal to I,. When Sj, is
open and S j 3 closed (Fig. lb), the memorised drain
current is available at the output. Fig. IC shows the corresponding clock phases. Transistor T j , works thus either
as an independent current source (switch Sjl open) or as
a drain-gate connected transistor (switch Sjl closed).
The elementary cell formed with Tj,, C j and the
switches Sjl, S j , and Sj3 can be repeated as desired to
obtain many current sources of value I, each. Some of
them can be connected in parallel to get non-unity
integer ratios. Ratios smaller than unity can be obtained
using a convergent algorithm [9].
Note that the value of the drain current is independent
of transistor matching and of linearity or hysteresis of
the capacitors Cj,.
The principle IS limited by the following major effects:
When switching off MOS transistors, the mobile
charges in the inversion charge layer are shared between
drain, source and substrate [lo]. A part of the charge
released by the sampling switch Sjl is added to the
charge already stored on the storing capacitor C j and
thus changes the memorised gate voltage and drain
current.
When switching S j , and S j 3 , transients occur. Their
amplitude is proportional to the voltage difference I V ,
- I applied to these switches.
The leakage currents from the junctions of the sampling switch Sjl discharge the storing capacitor C j and
determine the minimum switching frequency of the
mirror for a given accuracy.
An important requirement is that the output current
should not depend on the output voltage. As for a
normal current mirror design, the finite output conductance of the MOS transistor T,, has to be minimised to
obtain an accurate current mirror.

The authors are with the Electronics Laboratory LEG, Swiss Federal
Institute of Technology, Lausanne (EPFL), EL-Ecublens, CH-1015
Lausanne, Switzerland

* Also OGUEY, H., private communication, 1978

Introduction

Dynamic analogue techniques [l] exploit the property


that MOS transistors need no current to be controlled
from the gate to temporarily store some analogue information on capacitors. These techniques are used to
implement offset compensation in amplifiers and to
ensure adequate biasing of CMOS inverters. Another
very useful application is the dynamic comparator [2] in
which the analogue storage capability is exploited by
using the same transistor sequentially as the two devices
of a differential pair. Therefore, the very notion of mismatch disappears and the precision is mainly limited by
charge injection from MOS transistors used as switches.
The current mirror is another ubiquitous elementary
building block, whose precision is limited by device mismatch. Until now an increase in accuracy was obtained
by increasing the transistor areas and by drowning the
threshold voltage mismatch in a high gate voltage overhead. The idea of storing some analogue information on
a capacitor can be applied to a current mirror. The
memorised gate voltage is then an image of the imposed
drain current [3-7]*. This transistor can be sequentially
connected as the input device and the output device of a
mirror. The reproduced current at the output is then
independent of transistor mismatch.
Dynamic element matching proposed in Reference 9
with bipolar technology is based on a chopper technique.
It rejects the mismatch components to higher frequencies

Paper 7156G (E10, E16), first received 29th August 1989 and in revised

IEE PROCEEDINGS, Vol. 137, Pt. G, No. 2, A P R I L 1990

95

I
1
f

d
' j rn= a
'

'djrn"b

53

Fig. 1

Principle of the dynamic current mirror

Practical implementation of dynamic mirrors

To reduce the transients and the output conductance


effect, voltage V , should be as close as possible to voltage
V, A good way to impose this is to implement a cascoded structure by means of a common gate transistor.
To ensure a continuous output current two cells like
the one represented in Fig. 1 are needed leading to the
circuits shown in Fig. 2. Furthermore, the two cells have
to work with complementary clocks [6,7] as represented
in Fig. 2c.
Fig. 2a shows the simplest possible noncritical
dynamic current mirror [3, 6, 71. This structure, also
called a 'stacked mirror', is self biased and occupies the
smallest possible chip area, but has a high saturation
voltage.
To increase the output dynamic V,,, of the mirror, the
sampling switch S j , can be directly connected to the
external current source Ii, as shown in Fig. 2b. The gate
voltage drop of the diode connected transistor To, is
included in the gate voltage of transistor T j , and therefore must not exceed a limit value given by the difference
between the gate voltage of Ti, and its saturation voltage.
Transistor T,, must be in a separate well to avoid Tj,
leaving saturation.
To reduce the amplitude of the transients, transistor
T,,can be biased by an external voltage source hias
(Fig.
2b). This lowers the amplitude of the glitches as there is
no more modulation of the gate due to variations of the
input voltage. This bias voltage source must have the
same structure as the basic mirror cell, either the one of
Fig. 3a or that of Fig. 36, and must be matched to it to
guarantee the lowest possible voltage difference I Go,
- b,, I at the drains of transistors q,,,
. Furthermore an
image current 1;. of the input current I , must be available.

The influence of variations in the memorised gate


voltage on the output current I,,, can be reduced by
memorising only the current difference (Ii. - I,), leading
to a modified basic cell as shown in Fig. 4 [SI. This structure is less sensitive to an error voltage on storing capacitor C j than the others, as for the same gate voltage the
transconductance is reduced by the ratio Ii,,/(Iin - Z,).
The current difference must be larger than zero to ensure
that the drain-gate connected transistor still works correctly. Furthermore, the memorised gate voltage of ?*
must be higher than the saturation voltage of the additional current source I,. On the other hand, the variation in the memorised voltage, and thus the ripple of the
input voltage Kn,is increased.
A small voltage difference I Go, - GlmI (Fig. 2) always
exists because of the mismatch between the common-gate
transistors; the mismatch of switch resistance S j 2 , S j 3 ;
the finite output conductances. If a bias circuit IS used,

f
a

Fig. 3 Circuits required for external biasing of common-gate Iransistor T,<


Circuitfor basic cell of Fig. 2a
b Circuit for basic cell ofFig. 26, uscd for the current mirror
(I

lout

Fig. 2

Variations on the dynamic current mirrors


a Self-biasedmirror ('stacked mirror')
b Externally biased mirror with I , sampled at the drain of diode connected transistor Te
96

IEE PROCEEDINGS, Vol. 137, Pt. G, No. 2, APRIL I990

the voltage difference depends also on the mismatch


and
between the transistors in the bias circuit T,, q,,,
their counterparts in the output cell and on the difference
between I, and 1;. .

4.2 Influence of clock delays

The ideal case avoiding critical configurations would be a


simultaneous and instantaneous switching of the switches
S j , , Sj, and Sj3 as represented in Fig. 2c, but it is impossible to perform. It seems obvious that sampling switch
S j , must only be closed when switch S,, is closed, according to Fig. 2c. Otherwise the charge stored on C j is
altered, the memorised gate voltage of q, is not any
longer an image of the input current l i n and
,
an output
ripple occurs.
Concerning the switching of S,, and Si,, the worst
case is when all switches are open at the same time. This
has been verified analytically and with the circuit simulator program ESACAP [12].
Fig. 5 shows the simulated drain current variations of
transistors To, and TI, for the circuit corresponding to
2 0

Fig. 4

Basic cell for a d y m ' c mirror memorising the current differm e Vi. - 1,)

To achieve the desired accuracy it may be necessary to


reduce the output conductance with the help of a structure several times cascoded. For certain applications one
can manage to work at constant drain voltages to cancel
this effect, which can be done with the help of an amplifier [l I].

1 6

1 2

0 1 ' .
0

Transients ('Glitches')

4.1 Simplified analysis


Dynamic current mirrors are time variant circuits, which
means a different circuit configuration is present at every
switching. For mirrors of non-unity ratios the analysis
can be reduced to the one of a mirror of ratio 1 : 1,
because only two basic cells are interfering at the same
time while switching. The following assumptions are
usually acceptable:
Rsz,s3 * g,, 4 1 and g,, 4 gm , where g, and g, are
the transconductances of the common-source transistor
?;, and the common-gate transistor qC,respectively.
Switch resistances RsZ,s3of S j , and S j , must be small
compared to the transconductances to avoid an excessive
voltage drop on the switches, an effect of the mismatch
between the switch resistances, and to reduce their noise
contribution. Furthermore, the parasitic capacitances C,
are smaller than the functional capacitors Cj . Therefore
the difference between the time constants of the circuit is
so large that their influences can be treated separately.
The variations in the gate-to-source voltage AVgs. are
assumed to be small enough to allow a small signal
analysis. The effect of voltage difference (V,,, - V,,,)
and of charge injection due to the switches S j , , S,, can
be taken into account by modifying the initial conditions.
It can be shown by a theoretical approach that the
transients occurring at the output have the form:
Alout(t)U 9, * (V,,, - V,orn)e(-"L')
(1)
where the main time constant 7 m i is equal to T,, =
C J g I K , with C , being the sum of the parasitic capacitances at the internal nodes of the output cell. For a self
biased structure q,,,may be replaced by the larger of
T , ~ = CPiIJ,, or 7,, = Cj/gm,,where CPi is the sum of
the parasitic capacitances at the internal nodes of the
input cell and R,, is the sampling switch on-resistance.
The amplitude of the transients (Vdlm- born)
is
increased by nonsynchronous switching of Si, and S j , , as
will be shown in the next Section.
IEE PROCEEDINGS, Vol. 137, Pt. G,No. 2, A P R I L I990

04

08

1 2

time,

1 6

I0 8
20

1-15

Fig. 6 Simulated output and input currents of the dynamic current


mirror in Fig. 2a during a switching cycle with excessiue phase delay,
corresponding to critical switching configurations

Fig. 2a, whereas Fig. 6 shows it for the circuit of Fig. 2b.
The parameters of the simulation are the following: input
current I, is equal to 1 PA; storing capacitor C j is 5 pF;
mismatch of the transistors To, and T,, polarised in weak

time,

1-15

Fig. 6 Simulated output and input currents of the dynamic current


mirror in Fig. 2b during a switching cycle with excessiw phase delay,
corresponding to critical switching configurations

inversion is 5 mV and is 7.5 mV for To, and TI, working


in strong inversion. Parasitic capacitances at the internal
nodes Cpoand CPiare 0.5 pF.
The two critical switching situations are the following:
(i) During the time periods t, and ,t all switches
Sj3 and S j , are closed and at times t, and ,t switches
S j 3 or S j , are opened according to Figs. 3a and b. At
times t, and t, sampling switch S I , is closed, thus T,, is
diode connected.
(ii) During time periods t,, and ,,t
all switches Si,
and S j , are open (worst case) and at times ,t and res
switches S j , or Sj, are closed according to Fig. 3a and b.
At times ,t and ,t , sampling switch S,, is closed again.
The current variation observed at the beginning of
time t, is due to the balancing of the two voltages in the
91

source capacitances of q, through the switch resistances


of S j , and S,, . During time period t,,, in a self biased
mirror (Fig. 9, a new current mirror is formed with transistors T c ,while the two internal nodes are shorted. The
drain currents of these transistors are modified in accordance with their mismatch. Thus, the sum of the incoming
currents, at this internal node, is different from the sum of
the outgoing ones, which is equal to 21,. This current
difference loads the parasitic capacitances C , and
decreases or increases the node voltage. During I , , these
internal nodes converge to an equilibrium voltage that
satisfies the current balance. As soon as S,, is closed (at
the beginning of rIcj, the internal node voltages are forced
back to their DC-values and therefore the parasitic
capacitances have to lose their excessive charge, accumulated during r l o . The more charge has been accumulated
during t,,, the more important are the glitches at t , , or
t , , . The current variations observed are proportional to
the time period t , , , to the initial voltage difference I Vdom
- VdlmI and to the mismatch between transistors T,<,
During time period I , , , the source nodes of To, and
T,, are disconnected from the drain nodes of transistors
T , and T,-. The voltage at the source nodes of Tnnand
Ti: increases rapidly asthey are charged by a current of
about I,, whereas the drain voltages of To, and TI,
decrease, because they are discharged by the memorised
drain current of value Ii, . During t,, these internal nodes
are connected together again, converge to an equilibrium
voltage to satisfy the current balance and, as the incoming currents are equal to the outgoing ones, the voltages
remain constant. As soon as S j , is closed (at beginning of
tZr),the internal node voltages are forced back to the
DC-values and therefore the parasitic capacitances have
to lose their excessive charge accumulated during t,, .
The current variations observed are proportional to time
period t,,, to the initial voltage difference (Vdlm- GO,)
and to the input current I, and are thus much larger
than in the first case.
Similar reflections allow us to explain the current
variations shown in Fig. 6 for the mirror of Fig. 2b. Due
to the external, fixed bias voltage Ginsthe difference
between the two critical configurations mentioned above
is increased, and in the worst case configuration variations even larger than the input current can occur.
Due to such important glitches, the transistors building up the dynamic mirror may temporarily leave saturation, nonlinear effects may occur, important
AC-components may be added to the DC current and
the DC-accuracy of the mirror can be completely spoilt.
For well designed clocks, where the time spent in the
all-switches-closed configuration is minimised, the
glitches can be reduced to a small percentage of the input
current and depend on the mismatch between the transistors To,and T,, , and between To, and TI,; the output
voltage through the output conductance of TI, ; the parasitic capacitances C,,; switch resistances and clock overlapping of the switches.
It has to be pointed out that during a cycle the glitches
may all be of the same polarity, and thus do not necessarily cancel each other out. There is a DC-accuracy
tradeoff of the dynamic current mirror against its switching frequency [7], which can be verified experimentally
by changing the switching frequency and clock delays,
and by changing the DC-point of the internal output
node with the help of the output voltage.
Experimental results confirm the influences of clock
delays on the output current. Fig. 7a represents the input
voltage and Fig. 76 the variations in the output current
98

I,,, for an n-type current mirror of ratio 1 : 4 (I,,, =


4 PA), where one clock was delayed. The input voltage
shows stepwise variations because of the mismatch
between the mirror transistors q,,,
and a large glitch due

Fig. 7 Photograph oJinJuence ofexcessive clock phase delay


EITect on the input voltage V ,(mismatchof TJ
h EBect on lhe output currentI,, with I , = 4 @A
x-axis: At = 200 pldiv y-axis. a V, = 5 mV/div, h I,, = 5 nA/dlv
a

to the additional delay. Fig. 76 represents the increased


output current ripple due to the altered memorised
voltage on C j , a large glitch, due to the worst case configuration. Without any additional delay the output
current is constant and shows no such ripple [7].
Depending on the application, the transients (glitches)
may not have a large influence (i.e. when the currents
must be available only during a limited time period; in a
certain time window) or may be very important (for continuous time applications).
5

Charge injection and noise

The error voltage AV&r on C j produces a current error


AI,,,,, given by

_
AIerror
_ - -gmm
Iin

- Iin

* AV,,,,,

(2)

The first strategy that reduces this current error AI,,,,,


is to minimise gm,,,/lin and thus to have a large gate
voltage overhead (5,The major contribution to AV,,
is due to the charge
released by the MOS transistor S j , when switched off. A
reduction in this charge injection AV&j can be obtained
by using a dummy switch and by paying attention to the
different parameters influencing the equipartition of the
channel charge [lo].
It has been shown [lo] that, for minimal sized MOS
switches, the influence of the overlap capacitances may be
of the same importance as that of the channel charge.
Based on this consideration symmetrical dummy
switches lower the effect of asymmetrical overlap capacitances and compensate charge injection. Fig. 8 shows
one possible layout of sampling switch S j , and its symmetrical dummy switches. The charges on the overlap
capacitances designated by the same capital letters cancel
each other out, because they are driven by complementary clocks. The accuracy of the compensation is limited
to the and V, mismatch between the switching transistor S j , and its dummy switches.

v).

ZEE PROCEEDINGS, Vol. 137, P f . G, No. 2, APRIL 1990

Furthermore, the amount of channel charge in the


sampling switch can be minimised by a low gate voltage
overhead, which also favours the equipartition of the
channel charge [lo]. This can be done by using a circuit
metal

cl

II

Input

contact

PHI
PHI

poiy-SI

PHI

Experimental results

Dynamic n-type and p-type current mirrors have been


integrated in a 3p CMOS technology for different current
ratios. The circuits operate either with one clock phase
per basic cell or even with only one external clock per
mirror.
Each time the switch Sjl is closed, the gate voltage of
?, corresponds to the individually required voltage for
the given input current I,. Therefore, having several difvaries step by
ferent transistors ?, the input voltage
step in accordance with the mismatch of the mirror transistors ?, as shown in Fig. 7a.
Fig. 10 represents the measured accuracy of a self
biased p-type current mirror based on the structure represented in Fig. 3a and on the improvements mentioned

en

1000

diffusion

Fig. 8 h y m t ofsymmetrical dummy switches cancelling the efect of


asymmetrical overlap capacitances

that adapts the gate voltage of the sampling switch Sjl to


a value just above the gate voltage of the diode connected transistor ?,,,as represented in Fig. 9. The gate on

-1000

I,", P A

Fig. 10 Measured accuracy for a p t y p e current mirror based on the


structure of Fig. 3a as a function of output voltage and for two different
wafers
Chlp 1, V,, = 3 V
b Chip 1, V,,, = 2 V
(I

e chip 2,

Fig. 9 Principle of the circuit minimising the sampling switch charges


and adapting the gate on voltage of the sampling switch Si,to the input
went

voltage of the clock driving the sampling switch Sjl is


limited to V,, above the stored voltage on C j , which
reduces the amount of charge released by Sjl. For each
mirror transistor T,,, the amount of channel charge of Sjl
is therefore minimised.
The white noise of the switches S j , and S j , is negligible and the noise of qc(or that coming through it) is
divided by the gain of the cascode structure. The only
white noise contribution comes from the transistor ?,
connected to the output.
Switching noise produces a random component of
AV,
of variance kT/C, which can only be reduced by
increasing the value of the storing capacitor C j .
Because the white noise is undersampled, the noise
component in the baseband is larger than for a static
mirror due to the additional foldover terms. The l/f
noise is cancelled at the origin due to the inherent autozero technique, but foldover terms of the l/f noise
increase the white noise component [13].
IEE PROCEEDINGS, Vol. 137, Pt. G , No. 2, APRIL 1990

v,,

2v

above. The phase delay is not optimised and thus a small


variation in the DC-accuracy can be seen. The circuit
works with only one external clock and the achieved
accuracy is better than k500 ppm. During the measurements, the output voltage E,, was equal to 3 V (a) and to
2 V (b and c), while the switching frequency was 500 Hz
to reduce the DC-effect of the glitches mentioned in
Section 4. Graphs a and b show the accuracy for the
same p-type mirror, whereas graph c shows it for a p-type
mirror from another wafer. The output characteristics are
hardly influenced by the mismatch. Experimental results
for n-type mirrors have been presented in [7, 81, where an
accuracy of about 200 ppm was achieved.
7

Conclusions

The basic principles of different accurate dynamic current


mirrors based on dynamic analogue techniques have
been presented and the interfering parameters shown.
The transients that may occur during a cycle have been
analysed and their origin explicated. The influence of
clock delays on the output ripple and on the DCaccuracy has been shown. The proposed dynamic current
mirrors require no trimming and are insensitive to
matching or linearity of capacitors or transistors and
thus to process variations. The accuracy obtained makes
these current mirrors useful for various applications
where accurate currents are needed, such as D/A [SI or
A/D converters [ l l , 14, 151, continuous-time filters,*
neural networks and switched current (SI)filters [16].

* KRUMMENACHER, F., private communication


99

Acknowledgment

This work was supported by the National Program


PN13 of the Swiss Foundation of Scientific Research.
9

References

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ANTOGNETTI, P. (Eds.): VLSI circuits for telecommunications


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1 1 NAIRN, D.G., and SALAMA, C.A.T.: Current mode analog to
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1989
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1989
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pipelined A/D converter architecture using current mirrors, Electron. Lett., 1989,25, (ll), pp. 691692
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A P converter using current dividers, Electron. Lett., 1989, U,(20),
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rents - a new technique for analogue sampleddata signal processing. ISCAS 1989, Portland, pp. 1584-1587

1989

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