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DynamicRandomAccessMemory
DynamicRandomAccessMemory(DRAM)memory
cycles
The timing diagrams for the read, write and refreshonly cycles are shown in the Figure below.
For a read cycle /WE must be inactive before the CAS pulse is applied and remain inactive until
the /CAS pulse is over. After the column address is strobed, /RAS is raised and with /RAS high
and /CAS low the data bit is made available on DOUT.
For a write cycle the DIN signal should be applied by the time /CAS goes low, but after the /WE
pin goes low. The write is performed through the DIN pin while /RAS /CAS and /WE are all low.
The DOUT pin is held at its highimpedance state throughout the write cycle. For the refreshonly
cycle, only the row address is strobed and the /CAS pin is held inactive. The DOUT pin is kept in
its highimpedance state.
Note the address lines are A0 to A7 which provide 28 choices. However the memory is arranged
as a 28 x 28 matrix, giving 216 = 64K choices. The /RAS line is used to select the row and then
the /CAS line is used to select the column of the DRAM.
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http://www.electronics.dit.ie/staff/tscarff/memory/dram_cycles.htm
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