9/18/2013

Fundamental Concepts

F. M. Fernando

URSM-College of Engineering

Back to the bistable element

cross-coupled inverter maintains a zero or one,
but has no provision for forcing a change

enter the set-reset (S-R) latch

a cross-coupled NOR gates

F. M. Fernando

& a cross-coupled NAND gates

(Negative-OR equivalent)

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9/18/2013

Logic Symbol for the S-R and S-R Latch

Active-HIGH Input

S-R Latch

Active-LOW input
F. M. Fernando

URSM-College of Engineering

S-R Latch
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Sample Operation of the S-R Latch

1. ACTIVE-HIGH INPUT S-R LATCH
Recall the Truth Table of activeHIGH input S-R Latch. Use this to
observe the operation of the
device given the following input
signals.

F. M. Fernando

URSM-College of Engineering

9/18/2013

2. ACTIVE-LOW INPUT S-R LATCH

F. M. Fernando

URSM-College of Engineering

Determining the Q Output for a Given

S-R Waveforms
Example 1: If the S-R waveforms in Figure 7-5(a)
are applied to the inputs of the active-LOW S-R
latch, determine the waveform that will be
observed on the Q output. Assume that Q is
initially LOW.
Solution: See Figure 7-5(b)
Example 1-a: Determine the Q output of an activeHIGH input S-R latch if the waveforms in Figure
7-5(a) are inverted and applied to the inputs.
F. M. Fernando

URSM-College of Engineering

9/18/2013

F. M. Fernando

URSM-College of Engineering

F. M. Fernando

URSM-College of Engineering

9/18/2013

An Application: The Latch as a

Contact-Bounce Eliminator
A good example of an application of an S-R latch is
in the elimination of mechanical switch contact
bounce. When the pole of the switch strikes the
contact upon switch closure, it physically vibrates
or bounces several times before finally making a
solid contact. Although these bounces are very
short in duration, they produce voltage spikes that
are often not acceptable in a digital system. This
situation is illustrated in Figure 7-6(a).
F. M. Fernando

URSM-College of Engineering

Figure 7-6
F. M. Fernando

URSM-College of Engineering

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Refer to Fig. 7-6(b): The switch is

normally in position 1, keeping the
R input LOW & the latch RESET.
When the switch is thrown to
position 2, R goes HIGH because
of the pull-up resistor to Vcc , and
S goes LOW on the first contact.
Although S remains LOW for
only a very short time before the switch bounces, this is sufficient
to SET the latch. Any further voltage spikes on the S input due to
switch bounce do not affect the latch, & it remains SET. Notice
that the Q output of the latch provides a clean transition from
LOW to HIGH (or vice versa), thus eliminating voltage spikes
caused by contact bounce.
F. M. Fernando

URSM-College of Engineering

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The 74LS279A Set-Reset Latch

Notice that two of the latches each have

two S inputs.
F. M. Fernando

URSM-College of Engineering

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The Gated S-R Latch

Figure 7-8
F. M. Fernando

A gated latch requires an enable

input, EN (G is also used to designate
an enable input). The logic diagram &
logic symbol is shown in Figure 7-8.
The S and R inputs control the state
to which the latch will go when HIGH
level is applied to the EN input. The
latch will not change until EN is HIGH,
the output is controlled by the state of
the S and R inputs. In this circuit, the
invalid state occurs when both S and
R are simultaneously HIGH and EN is
also HIGH.
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Example 2:

Determine the Q output waveform if the

inputs shown in Fig. 7-9(a) are applied to a gated S-R latch
that is initially RESET.

F. M. Fernando

URSM-College of Engineering

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Example 2-a:

Determine the Q output of an active-HIGH

input S-R latch if the waveforms in Figure 7-5(a) are
interchanged & applied to its inputs.

F. M. Fernando

URSM-College of Engineering

15

The Gated D Latch

Another type of gated latch is called the D latch. It differs from the SR latch because it has only one input in addition to EN. This input is
called the D (data) input. Figure 7-10 contains a logic diagram & logic
symbol of a D latch. When the D input is HIGH and EN is HIGH, the
latch will SET. When the D input is LOW and EN is HIGH, the latch will
RESET. Stated another way, the Q output follows the input D when
EN is HIGH. The device is latched (no change) when EN is LOW for
any state level (X, dont care) of input D.
F. M. Fernando

URSM-College of Engineering

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Example 3:

Determine the Q output waveform if the

inputs shown in Fig. 7-11(a) are applied to a gated D latch,
which is initially RESET.

F. M. Fernando

URSM-College of Engineering

17

The 74LS75 D Latch

F. M. Fernando

URSM-College of Engineering

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Questions
1. List 3 types of latches.
2. Develop the truth table for the
active-HIGH & active-LOW input S-R
latch. Enumerate their difference.
3. What is the Q output of a D latch
when both EN and D are LOW?
F. M. Fernando

URSM-College of Engineering

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