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Power Estimation Tool for Sub-Micron CMOS V L S I C i r c u

Power Estimation Tool for Sub-Micron CMOS VLSI Circuits

for Sub-Micron CMOS V L S I C i r c u i t s F.

F. Rouatbi,

B. Haroun,

A. J. Al-Khalili

Departmentof Electrical Engineering, Concordia University 1455de MaisonneuveBlvd. W., Montreal, QuebecH3G lM8

Abstract

Accurate and fast time-domain current waveform simulation is important for the design of reliable CMOS VLSI circuits. Previous approaches for switch level current simulations used simple current models that did not match accurately the supply current. In this paper, we present a detailed current model that resulted in a maximum of 10% deviation from the current waveforms as obtained by SPICE LEVEL 3, at peak values and 5% on the average current. Our current model accounts for short-channel

effects, input rise times, short-circuit and dynamic current and circuit topology. Moreover, our model produces piece- wise linear current waveforms and hence can be easily incorporated in any switch-level simulator. Using our

models in an event driven simulator we achieved

3-4

orders of magnitude speed-up relative to SPICE LEVEL 3. Our results for- current waveform accuracy outperform previously published methods and in particular for complex CMOS circuits.

1. Introduction Different work has been done to develop fast current simulators andkeepan acceptableaccuracy.A peakcurrent estimator is developed in [l][lll. The simulator deal with the problem at three levels of hierarchy, gate level, macro level and power/ground distribution level. A gate is collapsed into an equivalent inverter and simulated using numerical analysis. A branch an bound algorithm is usedto estimate the peak’current in a macro, which can be 50% higher than SPICEestimates.Another technique to reduce the simulation time is to usean event driven simulator such as that used in [21 143.The current at the gate level is estimatedfrom adatabase,but including all thefactorsthat affects the supply current i.e. input rise/fall time, output capacitance, transistor sizes, input transitions etc., will increase the database size and the computational complexity. Also, the databasemethod does not handle circuits with pass-gates,becausethe stagedecompositionis static and corresponds to gates in the library. While in circuits with pass-gates the stage decomposition is dependenton the inputs [lo]. A current analysis tool that interrogates a switch-level mode simulator and extracts

O-8186-3010-8/92 $03.00 0 1992 IEEE

204

information on resistanceand capacitanceis presentedin

[3], thesecurrent waveforms are generatedby analyzing

a simple RC circuit that fails to give a good

approximation for the current waveforms for complex CMOS gates.Recently,a current model for CMOS gates has been presented in [121. In this work the supply

current is

equivalent inverter. Then the supply current is estimated basedon a pre-characterizedcurrent model. The current

model is basedon 3 time regions. The current estimates are fitted using exponential functions which are inherently difficult to usein event driven simulation. Our work presentsa new approachto overcomethe limitations described above. Our approach is based on event driven simulation using an accurate delay model,

estimated by collapsing a CMOS gate to an

combined with a detailed piece-wise

linear

analytical

current model to closely approximate supply current waveformsduring switching of a complex CMOS gate.

Our model is particularly suitable for event driven

simulation, which is widely used for

analyzing CMOS

circuits. The organization of this paper is as follows,

Section 2 presentsevent driven current simulation. In section 3 we presentcurrent estimation in a CMOS gate using collapsing. Section 4 describes our analytical current anddelay model. Section 5 comparesthe results

of our approach with SPICE level 3 and presents

examples of current simulation.

our work.

2. Event Driven Simulation Event driven simulation is particularly suitable for

fast current estimation in CMOS circuits, becausethe current flows in a CMOS gate only during switching of

the gate.Therefore the current can be viewed asthe sum

of all gate supply current waveforms. In an event driven

simulation the circuit is dynamically divided into stages

[l] [lo]. A timing analysis of the circuit is performed.

The results of the timing simulation are combined with the estimation of supply current waveforms in each stage to estimate the total supply current as shown in Fig. 1. The main issue in the event driven simulation is the accurate delay current alignment in multi-stage

Section 6 summarizes

The main issue in the event driven simulation is the accurate delay current alignment in multi-stage

circuits. As a consequencewe need accurate current

3.1

Current estimation using collapsing to multi-

3.1 Current estimation using collapsing to multi- the peak current and its timing and the averagecurrent.

the peak current

and its timing and the averagecurrent. Furthermore the current waveforms should be quick to compute in an event driven simulation, hencethe need for piece-wise linear analytical models.

models at the stagelevel, specifically

Fig. 1 Event Driven simulation 3. Current Estimation at the StageLevel The supply current flows in a CMOS gate only during the transition of the output node,Fig. 2 showsthe currentsduring the switching of a CMOS gatefrom high to low (low to high is symmetrical). The trigger input is defined as the transistor that triggers the charging or discharging of the output node. The supply current during switching of a CMOS stagehastwo components, the capacitive current lcap and the short-circuit current I sbrr. The short-circuit current is in general less than 20% of the total current and is dependenton the load [7][8]. In the case of a High to low transition C, is chargedand C,, is dischargedso the supply current is the sum of the short-circuit current and the fraction of the capacitivecurrent neededto chargeCp.

Supply current

 

Vdd

&

1”’

Trigget

Trigger

 

+I Cl8

 

Supply current

High to low transition

I

SUPP’YHL(LH))

=I

(similarly

shorf +

for

L to H)

5

(4

( cn +

cp)

Lp

CEQ.l)

Fig. 2 Currents in a CMOS Gate During Switching

gates Our model is basedon basic time-domain current wave- forms shown in Fig. 3 to estimate the capacitive and short-circuit current. These waveforms are then com- bined using EQ. 1 to estimate the supply current. We

havedeterminedthroughcareful analysis and simulation

that 4 basic waveforms cover all the capacitive current possibilities derived with input transitions and node capacitancesvalues. One waveform cover the short cir-

cuit current. The stages of the CMOS system are simplified by collapsing into 3 different gatesto estimate

the parametersincluded

ical model is derived from thecollapsedcircuits. Current estimationin a stage(High to Low transition) is summa- rized in the following steps:

l- The pull-up network is replaced with an equivalent transistor.

in thesewaveforms.The analyt-

2-

The trigger transistor is determined.

3-

The shortest(least number transistors)“on” path P in

the pull-down from the output node to the ground is determined(ex. Fig. 4).

4- All parallel/seriesnetworks of “on” transistorsin par-

allel with any transistor included in P are collapsed into

an equivalent transistor (Fig. 4). The result of this stepis a network of series-connectedMOS transistors(SCM). 5- SCM is collapsedin 2 gates.a) Gate I, to estimatethe capacitivecurrent surgedue to switching, b) Gate2 used to estimate the capacitive current waveform (Fig. 4). Two different gatesare used for the capacitive current estimation, because it’s not possible to accurately estimatethewaveform from a single equivalent circuit.

6- Stageis collapsedinto an equivalent inverter (Gate 3,

Fig. 4) to estimateI~,,, delay and output rise/fall time.

7- Supply current is determinedby combining capacitive andshort-circuit current waveformsusing EQ.l.

3.2 Issueswhen Collapsing a CMOS Gate

To achieve good accuracy in delay and current we

addressedthe following issuesfor the collapsedcircuit:

1- WeensureDelay equivalenceof

the collapsedgateby

determining the equivalent transconductanceasin [6].

2- Body effectsof seriesconnectedtransistorsare taken

into account. 3- Charge equivalence with the original gateby determining all initial voltages. 4- All switched node capacitancesare added when collapsing, their individual contributions are assumednot dependenton their position in the topology. S-In caseof multiple input transitions occur, a time window from the time the first pathto ground is createduntil the time the output nodeis completely switched. If thereare input transitions in that time window, the network is collapsedagain eachtime a new path is setby thesedelayedtransitions.

transitions in that time window, the network is collapsedagain eachtime a new path is setby thesedelayedtransitions.

205

transitions in that time window, the network is collapsedagain eachtime a new path is setby thesedelayedtransitions.
I& fhirnFbe Level :I s 0 I Waveform l-a W I f v e f
I& fhirnFbe Level :I s 0 I Waveform l-a W I f v e f

I&

fhirnFbe

Level

:I

s

0

I Waveform l-a

WIfveform l-b

:I s 0 I Waveform l-a W I f v e f o r m l

~

:I s 0 I Waveform l-a W I f v e f o r m l
 

Collapsed

Gate

1

to estimate

capacitive

current

surg

 

-b. time

Irm 2-b

Capacitive current

Waveform selection table

 

time

Fig. 3 Basic capacitive and short-circuit current waveforms used in our model 4. Analytical Current Model

 

Analytical current expressionsaredeterminedfrom the collapsed gatesof Fig. 4. Also the delay and output rise/fall time are determined. We only presenthere our

 

time

analytical model

for short-channel transistors basedon

Collapsed

Gate

3 to estimate

short-circuit

current

thedevice model in [9]. First we develop acurrent model for an ideal step input where the short-circuit current is zero, then we build on that model to include ramp input

 

effectsand the short-circuit

Step input The capacitive current is modelled based on 3 time

segments(Fig. the behavior of

Segment1 (t,), When the trigger transistor is switched “on” acurrent surgeIhit occurs dueto the switching. The

value of the current surgedependson the trigger position (waveform a or b of Fig. 3). Tl starts in the saturation

and all transistorsfrom T2 to Tn

The voltagesV2to 6-1 (t$ to V,), in Fig. 5 and 6, will fall (rise) until they reach a plateau value. Segment 1 ends when the node voltages V2to V,, are within 1% of their plateau values (Fig. 6). At that moment (ts) the currents through the node capacitancesare almost zero and the nodevoltagesarealmostconstant.

current.

6). These time segmentscorrespond to SCM circuits.

are in the linear region.

Fig. 4 Collapsing

time

Fig. 5 Capacitive current

time segmentscorrespond to SCM circuits. are in the linear region. Fig. 4 Collapsing time Fig. 5

206

time segmentscorrespond to SCM circuits. are in the linear region. Fig. 4 Collapsing time Fig. 5

Segment 2 (to), the capacitive current is almost constant. segment2 ends when Tl gets out of saturation and is omitted for small loads (waveform 2, Fig. 3). Segment 3 (tr), Tl to Tn are in the linear mode andIcap dropsto 0.

We have resolved analytically

wepresent waveform 1 (Fig.

all cases but in this paper 3). The other waveforms are

derived similarly [I4]. Our analytical current model is, more comprehensivethan the model presentedin [5][6] for delay only. In this section we proposeto determinea piece-wiselinear analytical currentmodelapproximation of the capacitivecurrent in SCMs.The capacitivecurrent

(IMP) is equal to the sum of all the currents in the node

capacitances. The initial current surge Iha

switching is determinedfrom collapsed gate I of Fig. 4. The current from the transistors above the trigger is neglected in the estimation of the current surge (lini,). This approximation is valid for fast inputs and gives an acceptableestimatefor practical input rise andfall times. The rest of the capacitive current waveform is

determinedfrom collapsed gate 2 (Fig. 4).

Analytical derivation of time-current points The current-time points of the capacitive current are determined from collapsed gate 2 (Fig.4, Fig.7). To estimate ICoP we resolve the node equations. These equations,when Tl is still in saturation (segmentl&2), lead to an analytical solution. Given the complexity of these equations (Fig. 7). we used a symbolic software package (Maple [25]) to solve for the model parameters as given in Table 1. When Tl gets out of saturation, a

direct solution of the current waveform is not possible. To resolve this problem, we determinethe chargelost by thecircuit during segment1& 2. Sincewe know the total

after

chargebefore the switching, we

during segment 1 & 2 to obtain the charge during segment 3. Then the current during segment 3 is determined from the charge as a linear decay while preserving current continuity. This solution ensures charge preservation and results in accurate average currents.

subtract the chargelost

1 c/p node

node _ _ 1

d

time

Spice

Waveform

l-a

c

cl

Fig. 6 Capacitive current model Input ramp effects

We based our model strategy for a ramp input on the

model derived for a step input (Fig.

current waveform current-time points are affectedby the

input rise time as shown in Fig. 8. The initial current

surgelinir and its timing t- are recalculated to

the input rise time using the short channel model with an approachsimilar to that in [7] for a long-channel inverter

with

(fig. 4) is derived analytically in the sameway and used to estimatethe short-circuit current, output rise/fall time and delay. These complex equations are derived using Maple and arenumerical evaluatedto estimatethe short- circuit current and the delay. Few time steps(3-30) are usually required for practical rise and fall times. This allows accurate short-circuit estimation especially for circuits with large loadslike I/O paddrivers.

8). The capacitive

include

a ramp input. The output voltage of collapsedgate3

Current equations during Segment I&2

:

c

4,

(

1

>

=

e9udl

2

node 2

 

c

&

(I)

=

‘dr

Id1

-IdI

-

Id2

Idl

I&=

Fig. 7 Equivalent gate to estimate the capacitive current

Short-channel model paramters [9];

PLff : effedive

Effective

Ler:

vmr : Carrier drift velocity

mobility;

C,, : Gate capacitance per unit aTea,

channel length.

channel length; Le Electrical

saturation,

= ~v,,,C,,W,

pef,co*w2

7

f

=

effr

1+

Saturation

voltage

(“DO

-

“T

-

3

(t)

1

1+-

V

DD

1

2(t)

[DD -"4~2(N*2(d

E&efn

EC‘,

_

y2

(,)

_

vT

v

d3a, =

(1

-

4

(‘,,

-

4

207

1 1+- V DD 1 “ 2 ( t ) [ “ D D -"4~2(N*2(d E&efn

Tigger

input

Iinif I

n

i

I*

Sameasstepinput

I

-1

(“00

2

litit

IPar.

r

I

init

Table 1: Waveform 1 parameters

Expression

t,

s =

f

(0.99~2~)

I

1 parameters Expression t, ‘ s = f (0.99~2~) I Fig.ti w time Modelling strategy for

Fig.ti

w time

Modelling strategy for an input ramp

5. Model Verification

Our models were tested on different complex CMOS circuits. Good agreementwith SPICE level 3 was achieved and someof the results are shown in Fig. 9, 10,ll. Fig. 9 shows the % difference in averageand peakcurrent with SPICEfor a 5 input NAND gate.For a PAD driver Fig. 10, handling large capacitanceby our model is shown. To demonstratemulti level logic, a 4 bit look-ahead adder with I/O padsis shown in Fig. 11. Our model showed a maximum 5% deviation from SPICE on the average current, and a maximum 10% deviation on the maximum current for several circuits. Table2 showsa comparisonbetweenour approachand

SPICE execution time, the speed-up is increasewith larger circuits.

expected to

6.

Conclusion In this paper we presented a novel

approach to

model the supply current waveforms in CMOS VLSI circuits. Basedon piece-wise linear current waveforms our model takesinto accountdifferent factorsthat affect the current waveforms. Our analytical model can be appended to any switch-level simulator to obtain accurate supply current waveforms. A new collapsing strategy is presentedto model the supply current more accurately. Our approach showed a good agreement with SPICE for different circuits and achieveda speed- up of 3 to 4 orders of magnitudeover SPICE.

208

I

I

AQ1 AQl=Cl(h[v2(o)l

-rh[o.yJ)

-cequ[v2(o)

-0.99~~~

I

da = kl (Ve- y2ss)

4ivs zss

4

I

,

=

=

=

-klVe+k,k3+k2k3Vcf

&I

(-2k,+k2k3)

Cl (VDD-

Vdr;r-Avl)lldss

AQ2 =

Idssta

2AQ3/ldrs

"cl3

=

einiriaf-

(AC+ +aQ2)

Functions

vl=h(v2)=-Av2/kg-E1fn(-v2+v2ssl)/k3Av2ss

I

I

 

+B21n (-

v2 + vzss2) Ik3AvzFs + Cte

=‘= iSd-hdfrom

“llv2=

vDD-avN

=

“DD

m (v2) =In(2klVek3+

2k1Vev2-

2klv2k3 - 2ktv;

C= (kfV;

+ 2eVek3

-2k2k3v2Vc

+ k2k&)

- 2k1Vck2k3Ve + kf4 + 2k1k;k2Vc + $k;V;

-

2kl Vegk2

) In

a=kfV;

+ 2<V,k3

-

2k1Vek2k3Vc

+

kf$

I g ( v2)

=

atanh

( (-kl

+ 2k, k;k2Vc

+ k2k3) v2 + kt V, -

Constants

b

is determined from

v2 1t =

o= VDD

-

aTN

+

k@,’

k1 kg -

-

2kl V&k2

k2k3Vc)

in EQ. 2

I

Ll

vc

=

=

I qn

(I= --

K”sa,Cox”‘l

vDD-

“VT,

;

;

C

k2=p

=

DD

C

cJJ

-yT.

ox

WIL

2

threshold linear reg. ; aVTnthreshold

C -P

Cl

-‘+2

k3

kl

; B1=-Vek3

-

;B2=-Vck3-Vv

e//z

k3

= EcLeffl

saturation ; a

factor

0.5 to 1 I

V

e

Y 2ss1+

k3v2.wl

+

“Ll

c

2.~2

+

‘3’2~~2

+

‘irs2

saturation ; a factor 0.5 to 1 I V e Y 2ss1+ k3v2.wl + “Ll c

References

[l]

currents in MOS IC logic circuits”

CAD, Vol. 9. NO. 6. June 90, pp. 642-654 [2] A. Chang. Y. Shiau, K. Lob. ‘Time Domain current waveform Simulation of CMOS Circuits”, IEEE Transactions on CAD, 88, pp. 208-211 [3] D.A. Haeusseler, K.F. Poole, “CURRANT: a current prediction software tool using a switch-level simulator”*, SOUTHEASTCON 89 Proceedings, ~01.3.89, pp. 946-948 [4] U. Jagau. K.P. Dyck. H. Grabinski, H.J. Iden, and M. Kuboschek. “Power distribution strategies Based on current Estimation and simulation of lossy transmission lines in conduction with power isolation circuits , IEEE Conference

WSI.1990,pp. 288-297

S. Chowdhmy,

J. S. Barkatullsh.”

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[5] S. M. Kang, H. Y. Chen, “A Global Delay Model for

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[6] T. Sakurai, A. Richard Newton, “Delay Analysis of Series-

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[8] Harry J. M. Veendrick, “Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer

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“SPIDER

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[12]

Current

J. H.

Wang,

J. T.

Fan, W.

S. Feng,

“A

Novel

Model for CMOS Gates”, IEEE International Symposiumon

Circuits and Systems,Vol. 5 pp. 2132-2133.1992 [ 131Maple, version 4.2, Watcom. University of Waterloo. [14] F. Rouatbi. B. Haroun, A.Alkhalili, “Supply Current Simulation for Sub-micron CMOS VLSI circuits”, submittedto

IEEE tramactions on CAD, Jul. 92.

Load capacitance(fF)

a- Averagecurrent

8

10.00

SM

6.00

4.00

6 2.00

$

2::

* -6.cQ

0.00

-s.oo

Eizl

Di~Xe~; transistors

Load capacitance(fP)

b- Peak curmt

Fig. 9 Corn araison with SPICE for a s-input nand gate

ENABIE

0.00

E\

o.su kchmlogy

‘*:

k

:

:

:

Lmd=lpF

,

Load=SpF

5.00

Time (ns)

10.00

PAD

,OAD

15.00

Fig. 10 A 4m-A I/O pad driver

Y x 10-3

3.50

3.00 1

3 2so

s

@

5

2.00-

1.50-

Ii

,

# ,

,

,

1

:

spice

Model

,

$l.oo-

3 0.50 -

1.50- Ii , # , , , 1 : spice Model , $l.oo- 3 0.50 -

20.M)

Tie

(ns)

Fig. 11A cl-bit carry look-ahead adder with I/O pad drivers

209

, , , 1 : spice Model , $l.oo- 3 0.50 - 20.M) Tie (ns) Fig.