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Abstract
1. Introduction
Different work has been done to develop fast current
simulators and keep an acceptableaccuracy.A peak current
estimator is developed in [l][lll. The simulator deal with
the problem at three levels of hierarchy, gate level, macro
level and power/ground distribution level. A gate is
collapsed into an equivalent inverter and simulated using
numerical analysis. A branch an bound algorithm is usedto
estimate the peakcurrent in a macro, which can be 50%
higher than SPICE estimates.Another technique to reduce
the simulation time is to usean event driven simulator such
as that used in [21 143.The current at the gate level is
estimatedfrom a database,but including all the factors that
affects the supply current i.e. input rise/fall time, output
capacitance, transistor sizes, input transitions etc., will
increase the database size and the computational
complexity. Also, the databasemethod does not handle
circuits with pass-gates,becausethe stagedecompositionis
static and corresponds to gates in the library. While in
circuits with pass-gates the stage decomposition is
dependenton the inputs [lo]. A current analysis tool that
interrogates a switch-level mode simulator and extracts
204
O-8186-3010-8/92 $03.00 0 1992 IEEE
Trigget
Trigger
+I Cl8
Supply current
High to low transition (similarly for L to H)
I
SUPPYHL(LH))
5 (4
=I shorf + ( cn + cp) Lp
CEQ.l)
205
Level :I
I&
fhirnFbe
s
Waveform l-a
WIfveform l-b
Collapsed
Gate 1 to estimate
capacitive
current
surg
-b.
time
Irm 2-b
Capacitive current
Waveform selection table
time
time
Collapsed
Gate 3 to estimate
short-circuit
current
Fig. 4 Collapsing
time
206
c/p node
time
Spice
Waveform
c cl
Fig. 6 Capacitive current model
Input ramp effects
We based our model strategy for a ramp input on the
model derived for a step input (Fig. 8). The capacitive
current waveform current-time points are affected by the
input rise time as shown in Fig. 8. The initial current
surgelinir and its timing t- are recalculated to include
the input rise time using the short channel model with an
approachsimilar to that in [7] for a long-channel inverter
with a ramp input. The output voltage of collapsed gate 3
(fig. 4) is derived analytically in the sameway and used
to estimate the short-circuit current, output rise/fall time
and delay. These complex equations are derived using
Maple and are numerical evaluated to estimate the shortcircuit current and the delay. Few time steps (3-30) are
usually required for practical rise and fall times. This
allows accurate short-circuit estimation especially for
circuits with large loads like I/O pad drivers.
_ _
node 1
c
4,
e9udl
>
Id1 - Id2
Idl = ~v,,,C,,W,
(DO - T -
pef,co*w2
node 2
I&=
2(t)
effr
c
&
dr
(I)
[DD
(t)
-"4~2(N*2(d
1+-
-IdI
E&efn
l-a
207
EC,
f = 1+
V
Saturation
voltage
_ y2 (,)
_ vT
DD
v d3a, =
(1 - 4
(,,
- 4
Tigger
input
-1
I
litit
r
I
Expression
IPar.
(00
init
Iinif
I
n
I*
Sameasstepinput
f (0.99~2~)
t,
I I
AQ1 AQl=Cl(h[v2(o)l
-rh[o.yJ)
-0.99~~~
da = kl (Ve- y2ss)
4ivs
-klVe+k,k3+k2k3Vcf
zss =
= Cl (VDD-
wtime
-cequ[v2(o)
&I
(-2k,+k2k3)
Vdr;r-Avl)lldss
AQ2 = Idssta
I
I I
, =
"cl3 = einiriaf-
2AQ3/ldrs
(AC+ +aQ2)
I
Functions
vl=h(v2)=-Av2/kg-E1fn(-v2+v2ssl)/k3Av2ss
+B21n (- v2 + vzss2) Ik3AvzFs + Cte
== iSd-hdfrom
llv2=
m (v2) =In(2klVek3+
vDD-avN
2k1Vev2-
DD
2klv2k3 - 2ktv;
-2k2k3v2Vc + k2k&)
+ 2<V,k3
- 2k1Vek2k3Vc
+ kf$
+ 2k, k;k2Vc
- 2kl Vegk2 ) In
+ k@,
- 2kl V&k2
+ k2k3) v2 + kt V, - k1 kg - k2k3Vc)
Constants
b is determined from v2 1t = o= VDD Ll
Ksa,Coxl
vc
vDD-
qn
VT,
C WIL
cJJ ox 2
DD
e//z
in EQ. 2
k3
= EcLeffl
-yT.
(I= --
k2=p
aTN
kl
-P
; B1=-Vek3
V Y
e 2ss1+
k3v2.wl
+ Ll
Cl
-+2
k3
208
;B2=-Vck3-Vv
c 2.~2 + 32~~2
+ irs2
References
10.00
SM
6.00
8 4.00
Di~Xe~; transistors
6 2.00
$ 0.00
2::
* -6.cQ
-s.oo
Eizl
Load capacitance(fP)
Load capacitance(fF)
a- Average current
b- Peak curmt
ENABIE
PAD
,OAD
E\ *:
k
:
.. ... ...........
Lmd=lpF
,
Load=SpF
10.00
5.00
Time (ns)
0.00
15.00
Ii
,
#,
3s 2so
2.00-
1 spice
:
Model
,.......
,,
@
5 1.50$l.oo3 0.50 -
20.M)
Tie (ns)
209