Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
Aula 5 - Reviso
Prof. Frank Sill Torres
DELT Escola de Engenharia
UFMG
Adaptado a partir dos Slides de Organizao de Computadores 2006/02 do professor Leandro Galvo
DCC/UFAM - galvao@dcc.ufam.edu.br e do Prof. Ricardo de Oliveira Duarte (DELT/UFMG)
1
1
Ponto fixo
:: Extenso de sinal :: Exemplo
-4dec (16 bits) para 32 bits:
1111 1111 1111 1100 bin
1111 1111 1111 1111
Multiplicando
32 bits
ALU 32 bits
Produto
Shift right
Escrever
Teste de
controle
64 bits
(-1)s m Be
s
m
B
e
sinal
significando (mantissa)
base
expoente
6
-231
overflow
negativo
underflow
negativo
underflow
positivo
nmeros
representados
- (2 - 2-23) 2128
231 - 1
- 2-127
nmeros
representados
2-127
overflow
positivo
(2 - 2-23) 2128
7
Processador
(ativo)
Controle
Via de
Dados
(Datapath)
Memria
(passiva)
Armazena
dados e
instrues de
programas
durante a
execuo
Dispositivos
Teclado,
Mouse
Entrada
Discos
Sada
Monitor,
Impressora
RE
CE
IT
AS
16
32
20
36
24
40
12
28
44
48
64
80
5
2
5
6
60
68
84
72
88
76
92
CONTROLE
S
TEE TO
MPE R
RO
S
VIA DE DADOS
0
1
2
3
4
SE
TO
BO L
R
OS
96
PROCESSADOR
10
0
10
4
10
8
ENTRADA
SE
CARTO R
NES
11
2
11
6
12
0
12
4
12
8
13
2
13
6
14
0
MEMRIA
SADA
10
de programa armazenado
Separao
Utilizao
de barramentos e registradores
Hardware
Processador
Barramento
Memria
11
Componentes do Processador
Controle
parte
12
Implementao de Instrues no
Processador
Ciclo nico
Tclock
Tadd
Tsrl
Tdiv
13
Implementao de Instrues no
Processador
Multi-ciclo
Tclock
Tadd
Tsrl
Tdiv
14
Implementao de Instrues no
Processador
Tclock
15
Ciclo nico
16
17
Add
4
PC
Read
address
Instruction
Instruction
memory
IR
Instrues do tipo R:
Leitura:
Escrita
5
5
Data
Read
register 1
Read
register 2
Write
register
Write
data
escrita
Read
data 1
Banco de
Registradores
Read
data 2
RegWrite
Data
rt
rs
op
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
rd shamt funct
IR
Banco de
Registradores
Dados de
escrita
RegWrite
Dados de
leitura
Campo
de offset de 16 bits
23
rt
rs
op
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
immediate
IR
Read
register 1
Read
register 2
Write
register
MemWrite
Read
data 1
Banco de
Registradores
Dados de
leitura
Read
data 2
Write
data
Address
Write
data
Read
data
Memria de
dados
RegWrite
16
Sign
extend
32
MemRead
Offset
Dois detalhes:
Offset
27
offset
Add Sum
rt
rs
Read
register 2
Write
register
Banco de
Registradores
ALU Zero
Read
data 2
Write
data
16
OpALU
Read
data 1
RegWrite
IR
Destino do
desvio
Shift
left 2
Read
register 1
op
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Sign
extend
32
Lgica de
controle do
desvio
Target << 2
op
target
2 bits
Novo PC
29
28
32
Left
shift 2
Add
PC+4[31:28]
Read
address
Instruction
Memria de
instrues
op
PC
target
30
IR
Combinando instrues
:: Tipo R + Load/Store
Tipo R: registrador
Tipo R: Rd
Load: Rt
Uso de multiplexadores
(MUX)
31
Combinando instrues
:: Tipo R + Load/Store
opALU
Rs
I
n
s
t
r
u
Rt
Rd
M
U
X
RegDst
MemWrite
Read
register 1
Read
register 2
Read
data 1
Write
register
Read
data 2
MemtoReg
OrigALU
Banco de
Write Registradores
data
Offset
ALU ALU
result
Address
Read
data
Memria de
dados
M
U
X
Write
data
RegWrite
16
M
U
X
Zero
Sign
extend
32
MemRead
32
Combinando instrues
:: Tipo R + Load/Store
add $t0, $s1, $s2
opALU
Rs
I
n
s
t
r
u
Rt
Rd
M
U
X
RegDst
MemWrite
Read
register 1
Read
register 2
Read
data 1
Write
register
Read
data 2
MemtoReg
OrigALU
Banco de
Write Registradores
data
Offset
ALU ALU
result
Address
Read
data
Memria de
dados
M
U
X
Write
data
RegWrite
16
M
U
X
Zero
Sign
extend
32
MemRead
33
Combinando instrues
:: Tipo R + Load/Store
sw $t0, 16($s2)
opALU
Rs
I
n
s
t
r
u
Rt
Rd
M
U
X
RegDst
MemWrite
Read
register 1
Read
register 2
Read
data 1
Write
register
Read
data 2
MemtoReg
OrigALU
Banco de
Write Registradores
data
ALU ALU
result
Address
Read
data
Memria de
dados
M
U
X
Write
data
RegWrite
16
Offset
M
U
X
Zero
Sign 32
extend
MemRead
34
Combinando instrues
:: Tipo R + Load/Store
lw $t0, 16($s2)
opALU
Rs
I
n
s
t
r
u
Rt
Rd
M
U
X
RegDst
MemWrite
Read
register 1
Read
register 2
Read
data 1
Write
register
Read
data 2
MemtoReg
OrigALU
Banco de
Write Registradores
data
Offset
ALU ALU
result
Address
Read
data
Memria de
dados
M
U
X
Write
data
RegWrite
16
M
U
X
Zero
Sign
extend
32
MemRead
35
Combinando instrues
:: Tipo R + Load/Store + Desvios
Endereo
36
Combinando instrues
:: Tipo R + Load/Store + Desvios
OrigPC
M
U
X
Add
Add ALU
result
4
Shift
left 2
Rs
PC
Read
address
Rt
Instruction
Rd
Memria de
instrues
Read
register 1
Read
Read
register 2 data 1
M
U
X
Write
register
Read
data 2
Banco de
Write
dataRegistradores
RegDst
RegWrite
16
$t0 = $t1
beq $t0,$t1,label
OrigALU 4
M
U
X
opALU
Zero
ALU ALU
result
MemWrite
MemtoReg
Address
Memria de
dados
Write
data
Sign
extend
Read
data
32
MemRead
M
U
X
Combinando instrues
:: Tipo R + Load/Store + Desvios
OrigPC
M
U
X
Add
Add ALU
result
4
Shift
left 2
Rs
PC
Read
address
Rt
Instruction
Rd
Memria de
instrues
Read
register 1
Read
Read
register 2 data 1
M
U
X
Write
register
Read
data 2
Banco de
Write
dataRegistradores
RegDst
RegWrite
16
$t0 $t1
beq $t0,$t1,label
OrigALU 4
M
U
X
opALU
Zero
ALU ALU
result
MemWrite
MemtoReg
Address
Memria de
dados
Write
data
Sign
extend
Read
data
32
MemRead
M
U
X
Implementando o Controle
:: Controle da ALU
Instrues do tipo R
ALU
Load / Store
ALU
Desvios
ALU
39
Implementando o Controle
:: Controle da ALU
Zero
ALU ALU
result
ALU
control
opALU
Instruo
Load/Store
Desvio
Tipo R
Entrada de controle
opALU
na ALU
00
01
10
add
sub
funct
Implementando o Controle
:: Controle da ALU
Implementando o Controle
:: Unidade de controle principal
RegDst
RegWrite
OrigALU
OrigPC
MemRead
MemWrite
MemtoReg
42
Implementando o Controle
:: Unidade de controle principal
Sinal de
Controle
RegDst
RegWrite
Nenhum
OrigALU
OrigPC
MemRead
Nenhum
MemWrite
Nenhum
MemtoReg
Implementando o Controle
:: Unidade de controle principal
Instruction [25 0]
26
Shift
left 2
M
u
x
M
u
x
ALU
Add result
Zero
ALU ALU
result
Address
Add
4
Instruction [31 26]
Control
Read
address
Instruction
memory
Read
register 1
Shift
left 2
RegDst
Jump
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
0
M
u
x
1
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
0
M
u
x
1
Write
data
Write
data
Instruction [15 0]
16
Instruction [5 0]
Sign
extend
32
ALU
control
Read
data
Data
memory
1
M
u
x
0
Implementando o Controle
:: Unidade de controle principal
45
Implementando o Controle
:: Unidade de controle principal
Entrada
opcode na
unidade de
controle
Sadas da
unidade de
controle
Opcode
Nome
Bit31
Bit30
Bit29
Bit28
Bit27
Bit26
RegDst
ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite
Branch
ALUop1
ALUop0
0h
R
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
23h
Lw
1
0
0
0
1
1
1
0
1
1
1
0
0
0
0
2Bh
Sw
1
0
1
0
1
1
X
0
X
0
0
1
0
0
0
4h
Beq
0
0
0
1
0
0
X
1
X
0
0
0
1
0
1
46
47
Atraso (ns)
Memria
ALU
Unidade de PF (+ / -)
Unidade de PF ( / )
16
Acesso a registradores
48
Load
31
Store
21
Tipo R
25
Branch
Jump
Operaes PF (+ / -)
Operaes PF ( / )
49
Compare o desempenho de
a) Uma implementao de ciclo nico usando clock de
perodo fixo
b) Uma implementao de clock com perodo varivel
50
Load word
Store word
R-format
Branch
Jump
FP mul/div
FP add/sub
2
2
2
2
2
2
2
1
1
1
1
1
1
2
2
2
2
Mem.
Dados
Escr .
Reg.
2
2
PF
add/
sub
PF
mul/
div
1
1
16
8
Tempo
Total
ns.
8
7
6
5
2
20
12
51
Portanto:
Desempenhociclo nico
Desempenhociclo varivel
20
2,9
7
52
Multi-ciclo
53
Multi-ciclo
Tclock
Tadd
Tsrl
Tdiv
54
Possveis estgios:
Instruction
Instruction
Execuo
MEM
Write
56
Ins truction
re gis te r
PC
Addre s s
Da ta
A
Re gis te r #
Ins truction
Me mory
or data
Da ta
ALU
Re gis te rs
Me mory
da ta
re gis te r
ALUOut
Re gis te r #
B
Re gis te r #
60
Incluir multiplexadores
61
Memria nica:
ALU nica:
63
1u
2
PC
0
M
u
x
1
Addres s
Me mory
MemDa ta
Write
da ta
Ins truction
[25 21]
Rea d
re gis te r 1
Ins truction
[20 16]
Re ad
Rea d
re gis te r 2 da ta 1
Re gis te rs
Write
Re ad
re gis te r da ta 2
Ins truction
[15 0]
Ins truction
re gis te r
Ins truction
[15 0]
Me mory
da ta
re gis te r
0
M
Ins truction u
x
[15 11]
1
B
4
Write
da ta
0
M
u
x
1
16
Sign
e xtend
0
M
u
x
1
32
Zero
ALU ALU
res ult
ALUOut
0
1 M
u
2 x
3
S hift
le ft 2
64
65
RegDst
RegWrite
Nenhum
MemRead
Nenhum
O contedo da posio de
memria endereada colocado
nas sadas
MemWrite
Nenhum
O contedo da posio de
memria endereada reescrito
OrigAALU
66
MemtoReg
IouD
IR Write
Nenhum
Nenhum
PC escrito; a origem
controlada por OrigPC
WritePC
WritePCCond Nenhum
OpALU
OrigBALU
Valor
(binrio)
Efeito
00
01
10
00
01
10
11
Valor
(binrio)
Efeito
00
01
10
OrigPC
69
PCSource
PCWrite
ALUOp
Outputs
IorD
ALUSrcB
MemRead
ALUSrcA
Control
MemWrite
RegWrite
MemtoReg
Op
RegDst
IRWrite
[5 0]
0
M
26
Instruction [25 0]
PC
0
M
u
x
1
Shift
left 2
Instruction
[31-26]
Address
Memory
MemData
Write
data
Instruction
[25 21]
Read
register 1
Instruction
[20 16]
Read
Read
register 2 data 1
Registers
Write
Read
register data 2
Instruction
[15 0]
Instruction
register
Instruction
[15 0]
Memory
data
register
0
M
Instruction u
x
[15 11]
1
B
4
Write
data
0
M
u
x
1
16
Sign
extend
32
Instruction [5 0]
Shift
left 2
1 u
Jump
address [31-0]
x
2
PC [31-28]
0
M
u
x
1
28
Zero
ALU ALU
result
ALUOut
0
1 M
u
2 x
3
ALU
control
70
Estgio 1
Instruction Fetch (IF)
= *PC;
PC
= PC + 4;
71
Estgio 1: IF
IR = *PC
PC = PC + 4
I
R
PC
MemWrite
ADDR
Memory
RD
PC + 4
WD
MemRead
M
D
R
Instruction I
5
RN1
RN2
WN
Registers
RD1
Operation
3
Zero
ALU
WD
RD2
ALU
OUT
RegWrite
Carga de Instruo
72
Estgio 2
Instruction Decode (ID)
A = Reg[IR[25-21]];
B = Reg[IR[20-16]];
73
Estgio 2
Instruction Decode (ID)
A = Reg[IR[25-21]];
(A = Reg[rs])
B = Reg[IR[20-15]];
(B = Reg[rt])
ALUOut = (PC + sign-extend(IR[15-0]) << 2)
I
R
PC
MemWrite
ADDR
Memory
RD
PC + 4
WD
MemRead
M
D
R
Instruction I
5
RN1
RN2
WN
Registers
RD1
Reg[rs]
Operation
3
Zero
Branch
Target
Address
ALU
WD
ALU
OUT
RD2
RegWrite
Reg[rt]
74
Estgio 3
Execution (EX)
75
Estgio 3:EX
Instrues de acesso memria
ALUOut = A + sign-extend(IR[15-0]);
I
R
Instruction I
5
PC
RN1
MemWrite
ADDR
Memory
RD
PC + 4
WD
MemRead
M
D
R
RN2
Reg[rs]
RD1
Mem.
Address
WN
Registers
Operation
Zero
ALU
WD
ALU
OUT
RD2
RegWrite
Reg[rt]
76
Estgio 3: EX
Instruces tipo R
ALUOut = A op B
I
R
PC
MemWrite
ADDR
Memory
RD
PC + 4
WD
MemRead
M
D
R
Instruction I
5
RN1
RN2
WN
Registers
RD1
Reg[rs]
Operation
3
Zero
R-Type
Result
ALU
WD
ALU
OUT
RD2
RegWrite
Reg[rt]
77
Estgio 3: EX
Branch
if (A == B) PC = ALUOut;
I
R
PC
MemWrite
ADDR
Memory
Branch
Target
Address
RD
WD
MemRead
M
D
R
Instruction I
5
RN1
RN2
WN
Registers
RD1
Reg[rs]
Operation
3
Zero
Branch
Target
Address
ALU
WD
ALU
OUT
RD2
RegWrite
Reg[rt]
78
Estgio 3: EX
Jump
PC = PC[31-28] concat (IR[25-0] << 2)
I
R
PC
MemWrite
ADDR
Memory
Jump
Address
RD
WD
MemRead
M
D
R
Instruction I
5
RN1
RN2
WN
Registers
RD1
Reg[rs]
Operation
3
Zero
Branch
Target
Address
ALU
WD
ALU
OUT
RD2
RegWrite
Reg[rt]
79
Estgio 4
Acesso memria (MEM)
Instrues do tipo R:
Estgio 4: MEM
Leitura de memria (lw)
MDR = Memory[ALUOut];
I
R
Instruction I
5
PC
RN1
MemWrite
ADDR
Memory
RD
PC + 4
WD
M
D
R
MemRead
RN2
Reg[rs]
WN
Registers
RD1
Mem.
Address
Operation
Zero
ALU
WD
ALU
OUT
RD2
RegWrite
Mem.
Data
Reg[rt]
81
Estgio 4: MEM
Escrita de memria (sw)
Memory[ALUOut] = B;
I
R
PC
MemWrite
ADDR
Memory
RD
PC + 4
WD
MemRead
M
D
R
Instruction I
5
RN1
RN2
WN
Registers
RD1
Reg[rs]
Operation
3
Zero
ALU
WD
ALU
OUT
RD2
RegWrite
Reg[rt]
82
Estgio 4: MEM
Instrues de Tipo R
Reg[IR[15:11]] = ALUOUT
I
R
PC
MemWrite
ADDR
Memory
RD
PC + 4
WD
MemRead
M
D
R
Instruction I
5
RN1
RN2
WN
Registers
RD1
Reg[rs]
Operation
3
Zero
R-Type
Result
ALU
WD
ALU
OUT
RD2
RegWrite
Reg[rt]
83
Estgio 5
Write Back (WB)
Reg[IR[20-16]]= MDR;
Estgio final
84
Estgio 5: WB
Finalizao de leitura de memria (lw)
Reg[IR[20-16]] = MDR;
I
R
PC
MemWrite
ADDR
Memory
RD
PC + 4
WD
M
D
R
MemRead
Instruction I
5
RN1
RN2
WN
Registers
RD1
Reg[rs]
Operation
3
Zero
Mem.
Address
ALU
WD
ALU
OUT
RD2
RegWrite
Mem.
Data
Reg[rt]
85
Resumo Multi-ciclo
Tipo de instruo
Estgio
Carga de Instruo
Ao Tipo R
(IF)
Decodificao Instruo
Carga de Registrador
(ID)
Execuo (EX)
Computo de Endereo
Finalizao branch/jump
Acesso memria
Finalizao tipo R
(MEM)
ALUOut = A op B
Reg [IR[15-11]] =
ALUOut
Action Memria
Ao Branch
IR = Memory[PC]
PC = PC + 4
A = Reg [IR[25-21]]
B = Reg [IR[20-16]]
ALUOut = PC + (sign-extend (IR[15-0]) << 2)
ALUOut = A + sign-extend
if (A ==B) then
(IR[15-0])
PC = ALUOut
Ao Jump
PC = PC [31-28] II
(IR[25-0]<<2)
(WB)
86
No. de ciclos
Load
22
Store
11
Tipo R
49
Branch
16
Jump
Soluo:
N
CPI total
instr , i
CPI i
i 1
N instr , total
N instr , i
N
i 1
CPI i
instr , total
4,04
Resumo Multi-ciclo
Controle
ALU
Implementao de multi-ciclo
Incluso
de multiplexadores
Estgios
Clculo do CPI
90
Questo
Definatodosospassosnecessriosparaasinstruesseguintesquando
elesforemexecutadosemumaarquiteturaMIPSmulticiclo:
jlabel3 lw $s3,12($t0), beq $t2,$t4,$t1,sub$s1,$s2,$s3.
j label3
IF, ID, EX
lw $s3, 12($t0)
IF, ID, EX
Implementao de multi-ciclo
Incluso
Linhas
de multiplexadores
de controle
Estgios
Controle
Mquinas
Implementao
Clculo do CPI