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I. INTRODUCTION
Multipliers play an important role in
computation and other advanced mechanism,
which makes them one of the key components of
every ALU.Multiplication, requires substantially
more hard-ware resources and processing time
than addition and subtraction. The need of high
speed multiplier is increasing as the need of high
speed processors are increasing. Higher
throughput arithmetic operations are important
to achieve the desired performance in many real
time signal and image processing applications.
Vedic mathematics is the name given to the
ancient system of mathematics, which was
rediscovered from the ancient Indian scriptures
between 1911 and 1918 by Jagadguru Swami Sri
Bharati Krisna Tirthaji (1884-1960), a scholar of
Sanskrit, mathematics, history and philosophy.
The whole of Vedic mathematics is based on 16
Vedic sutras, which are actually word formulae
describing natural ways of solving a whole range
of mathematical problems.The term adiabatic
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International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
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III.
VEDIC MULTIPLICATION
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MULTIPLIER
VII.
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International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
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International Journal of Scientific Research Engineering & Technology (IJSRET), ISSN 2278 0882
Volume 4, Issue 3, March 2015
VIII.
Multiplier
Circuit(8*8)
Adiabatic
EEAL
Adiabatic
ECRL
Adiabatic
PFAL
Power(W)
Delay(ns)
6.801
5.250
4.642
4.75
1.483
3.500
CONCLUSION
Jagadguru
Swami
Sri
Bharath,
KrsnaTirathji(1986), Vedic Mathematics or
Sixteen Simple Sutras From The Vedas,
MotilalBanarsidas ,Varanasi(India).
[8] Jian.X, W. Peng-jun, Z. Xiao-yang(2007),
Research of adiabatic multiplier based on
CTGAL, in 7th International Conference on
ASIC, China, pp. 138141, 22-25 Oct., 2009
[9] Kundu.P.P,
O.
Bandyopadhyay,
A.
Sinha(2008), "An efficient architecture of
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Knoxville, TN, pp. 221, 10-13
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and
R.S
Sabeenian(2010), An efficient bit reduction
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Computing Conference, Patiala, India, pp.
25, 19-20 Feb.
[11] Pushpangadan.R,
V. Sukumaran, R.
Innocent, D. Sasikumar, V. Sundar(2010),
High Speed Vedic Multiplier for Digital
Signal Processors, IETE journal of
research, vol. 55, issue 6, pp. 282-286.
[12] Rabaey.J.M , A. Chandrakasan, and B.
Nikolic(2003), Digital Integrated Circuits: A
Design Perspective (2nd edition). New
York: Prentice Hall.
[13] Seo Y.H , D. W. Kim(2010), A New VLSI
Architecture
of
Parallel
Multiplier
Accumulator Based on Radix-2 Modified
Booth Algorithm, IEEE Trans. on VLSI
Systems Circuits and Systems, vol. 18, no. 2,
pp. 201-208.
[14] Thapliyal.H (2005), VLSI implementation
of RSA encryption system using ancient
Indian Vedic mathematics, proc. of VLSi
circuit and system, vol. 5837, pp. 888-892.
[15] Thapliyal and M. B. Srinivas(2005), An
Efficient Method of Elliptic Curve
Encryption Using Ancient Indian Vedic
Mathematics, in Proc. IEEE MIDWEST
Symp. Circuits. Systems, Cincinnati, pp.
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[16] Takahashi.Y.,
T.
Sekine,
and
M.
Yokoyama(2008), Two-phase clocked
CMOS adiabatic logic, in Proc. IEEE Asia
pacifiic Conf. Circuits and Systems, Macao,
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[17] Zhao and K. Roy, Estimation of switching
noise on power supply lines in deep submicron CMOS circuits, 13th International
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