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Lecture 9
Page 1 of 8
Whites, EE 320
Lecture 9
Page 2 of 8
Then one would see this output voltage vO for this particular
input voltage vI:
vO
vI
-1
-3
Ideal
vI
5V
+
Ideal vO
Whites, EE 320
Lecture 9
Page 3 of 8
(Fig. 3.36b)
There are three important things to note about this circuit:
1. The ideal D keeps vO 0 .
2. C charges only when vI < 0 . Without a load, there is no
other path for current.
3. The vC polarity is positive as shown above.
With these insights, lets look at a specific example to illustrate
the operation of this circuit. Consider this input voltage:
(Fig. 3.36a)
C in Fig. 3.36b will eventually charge completely so that vC = +6
V. In that case, the lowest output voltage will be clamped to
zero. The output voltage will appear as:
Whites, EE 320
Lecture 9
Page 4 of 8
(Fig. 3.36c)
Hence, this is called a clamped capacitor circuit. Without the
diode present in this circuit, the capacitor would not retain any
net charge per period so it would never charge up to 6 V.
Note that here we are looking at the steady state response. It
may take a few periods for the capacitor to completely charge.
Were not looking at the transient response.
There are two applications of the clamped capacitor circuit
discussed in the text.
(a) Pulse width modulation detector. PWM is used for
motor speed control, for example. The width of the pulse
contains the information.
Whites, EE 320
Lecture 9
Page 5 of 8
C1
Vpcos( t)
D1
-
D2
+
vD1 C2
-
+
vO
-
Clamped
capacitor
Half-cycle peak
rectifier
vD1
Whites, EE 320
Lecture 9
Page 6 of 8
Whites, EE 320
Lecture 9
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Whites, EE 320
Lecture 9
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+
+
+
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+