P400 Series

Vishay High Power Products

Passivated Assembled Circuit Elements, 40 A

FEATURES
Glass passivated junctions for greater reliability
Electrically isolated base plate
Available up to 1200 VRRM/VDRM
High dynamic characteristics
Wide choice of circuit configurations
Simplified mechanical design and assembly
UL E78996 approved
PACE-PAK (D-19)

Compliant to RoHS directive 2002/95/EC

DESCRIPTION
PRODUCT SUMMARY
IO

40 A

The P400 series of integrated power circuits consists of

power thyristors and power diodes configured in a single
package. With its isolating base plate, mechanical designs
are greatly simplified giving advantages of cost reduction
and reduced size.
Applications include power supplies, control circuits and
battery chargers.

MAJOR RATINGS AND CHARACTERISTICS

SYMBOL

VALUES

UNITS

IO

80 C

40

ITSM,
IFSM

50 Hz

385

60 Hz

400

50 Hz

745

60 Hz

680

I2t

CHARACTERISTICS

I2t

A2s

7450

A2s

400 to 1200

2500

- 40 to 125

VRRM/VDRM, MAXIMUM
REPETITIVE PEAK REVERSE AND
PEAK OFF-STATE VOLTAGE
V

VRSM, MAXIMUM
NON-REPETITIVE PEAK
REVERSE VOLTAGE
V

IRRM MAXIMUM
AT TJ MAXIMUM
mA

P401, P421, P431

400

500

P402, P422, P432

600

700

P403, P423, P433

800

900

P404, P424, P434

1000

1100

P405, P425, P435

1200

1300

VRRM

Range

VISOL
TJ
TStg

ELECTRICAL SPECIFICATIONS
VOLTAGE RATINGS
TYPE
NUMBER

Document Number: 93755

Revision: 05-Nov-09

For technical questions, contact: indmodules@vishay.com

10

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P400 Series
Vishay High Power Products Passivated Assembled
Circuit Elements, 40 A
ON-STATE CONDUCTION
PARAMETER

SYMBOL

Maximum DC output current

at case temperature

IO

TEST CONDITIONS

ITSM,
IFSM

t = 8.3 ms

t = 10 ms
I2t

t = 8.3 ms
t = 10 ms
t = 8.3 ms

Maximum I2t for fusing

I2t

40

80

No voltage
reapplied

385

100 % VRRM
reapplied

325

400
A

t = 10 ms
t = 8.3 ms

Maximum I2t for fusing

UNITS

Full bridge circuits

t = 10 ms

Maximum peak, one-cycle

non-repetitive on-state or
forward current

VALUES

No voltage
reapplied

Sinusoidal half wave,

initial TJ = TJ maximum

340
745
680

480

t = 0.1 ms to 10 ms, no voltage reapplied

I2t for time tx = I2t tx

7450

Low level value of threshold voltage

VT(TO)1

(16.7 % x x IT(AV) < I < x IT(AV)), TJ = TJ maximum

0.83

High level value of threshold voltage

VT(TO)2

(I > x IT(AV)), TJ = TJ maximum

1.03

Low level value of on-state slope resistance

rt1

(16.7 % x x IT(AV) < I < x IT(AV)), TJ = TJ maximum

9.61

rt2

(I > x IT(AV)), TJ = TJ maximum

7.01

Maximum on-state voltage drop

VTM

ITM = x IT(AV)

Maximum forward voltage drop

VFM

IFM = x IF(AV)

Maximum non-repetitive rate of rise of

turned-on current

dI/dt

TJ = 125 C from 0.67 VDRM

ITM = x IT(AV), Ig = 500 mA, tr < 0.5 s, tp > 6 s

Maximum latching current

IH
IL

TJ = 25 C

A2s
V

High level value of on-state slope resistance

Maximum holding current

A2s

530

100 % VRRM
reapplied

1.4

200

A/s

130
TJ = 25 C anode supply = 6 V, resistive load

mA
250

BLOCKING
PARAMETER

SYMBOL

VALUES

UNITS

TJ = 125 C, exponential to 0.67 VDRM gate open

200

V/s

IRRM,
IDRM

TJ = 125 C, gate open circuit

10

mA

Maximum peak reverse leakage current

IRRM

TJ = 25 C

100

RMS isolation voltage

VISOL

50 Hz, circuit to base, all terminals shorted,

TJ = 25 C, t = 1 s

2500

Maximum critical rate of rise of

off-state voltage

dV/dt

Maximum peak reverse and off-state

leakage current at VRRM, VDRM

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TEST CONDITIONS

For technical questions, contact: indmodules@vishay.com

Document Number: 93755

Revision: 05-Nov-09

P400 Series
Passivated Assembled
Circuit Elements, 40 A

Vishay High Power Products

TRIGGERING
PARAMETER

SYMBOL

Maximum peak gate power

Maximum average gate power
Maximum peak gate current
Maximum peak negative gate voltage
Maximum gate voltage required to trigger

TEST CONDITIONS

PG(AV)

UNITS
W

IGM

-VGM

10

VGT

TJ = - 40 C

TJ = 25 C

TJ = 125 C
IGT

Maximum gate voltage that will not trigger

VGD

Maximum gate current that will not trigger

IGD

Anode supply =
6 V resistive load

TJ = - 40 C
Maximum gate current required to trigger

VALUES

PGM

90

TJ = 25 C

60

TJ = 125 C

35

TJ = 125 C, rated VDRM applied

mA

0.2

mA

VALUES

UNITS

- 40 to 125

THERMAL AND MECHANICAL SPECIFICATIONS

PARAMETER

SYMBOL

Maximum junction operating

and storage temperature range

TEST CONDITIONS

TJ, TStg

Maximum thermal resistance,

junction to case per junction

RthJC

DC operation

1.05

Maximum thermal resistance,

case to heatsink

RthCS

Mounting surface, smooth and greased

0.10

K/W

Mounting torque, base to heatsink (1)

Approximate weight

Nm

58

2.0

oz.

Note
(1) A mounting compund is recommended and the torque should be checked after a period of 3 hours to allow for the spread of the compound

CIRCUIT TYPE AND CODING

(1)

CIRCUIT 0

CIRCUIT 2

CIRCUIT 3
AC2 G2
G1 G4
AC1 G3 +

AC1 G1

AC1 G1

AC2 G2

AC2 G2

Terminal positions

G1

Schematic diagram

G1

G3

G2

G1

AC1

AC2

AC1

AC2

AC1

AC2

G2
(-)

(+)

G4
(-)

(+)

(-)

G2
(+)

Single phase hybrid bridge

common cathode

Single phase hybrid bridge doubler

Single phase all SCR bridge

P40.

P42.

P43.

With voltage suppression

P40.K

P42.K

P43.K

With freewheeling diode

P40.W

P40.KW

Basic series

With both voltage suppression

and freewheeling diode

Note
To complete code refer to Voltage Ratings table, i.e.: For 600 V P40.W complete code is P402W

(1)

Document Number: 93755

Revision: 05-Nov-09

For technical questions, contact: indmodules@vishay.com

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3

P400 Series
Vishay High Power Products Passivated Assembled
Circuit Elements, 40 A
120
+

Maximum Total Power Loss (W)

Maximum Total Power Loss (W)

120
~

100

80
180
(sine)

60
40

TJ = 125 C

20

100

/W

1.5

60

0.
7

K/

K/W

2K

-
R

/W

3 K/W

40

5 K/W

20

10 K/W

0
0

10

15

20

25

30

35

40

25

50

75

100

125

Maximum Allowable
Ambient Temperature (C)
Fig. 1 - Current Ratings Nomogram (1 Module Per Heatsink)

Total Output Current (A)

93755_01a

93755_01b

30

130

180
120
90
60
30

20
15

RMS limit

10

Conduction angle
TJ = 125 C
Per junction

Maximum Allowable Case

Temperature (C)

Fully turned-on
25

120
180
(Rect.)

110
100

180
(Sine)

90
80
Per module

70
0

10

15

20

Average On-State Current (A)

93755_02

DC
180
120
90
60
30

30
25
20

RMS limit

15

10

Conduction period
TJ = 125 C
Per junction

5
0
0

10

15

20

25

30

Fig. 3 - On-State Power Loss Characteristics

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15

20

25

30

35

40

45

Total Output Current (A)

1000
TJ = 25 C

TJ = 125 C

100

35

Average On-State Current (A)

93755_03

10

Fig. 4 - Current Ratings Characteristics

Instantaneous On-State Current (A)

40
35

93755_04

Fig. 2 - On-State Power Loss Characteristics

Maximum Average On-State

Power Loss (W)

th
SA

1K

80

Maximum Average On-State

Power Loss (W)

93755_05

10

Per junction
1
0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

Instantaneous On-State Voltage (V)

Fig. 5 - On-State Voltage Drop Characteristics

For technical questions, contact: indmodules@vishay.com

Document Number: 93755

Revision: 05-Nov-09

P400 Series
Passivated Assembled
Circuit Elements, 40 A
350

400

Peak Half Sine Wave

On-State Current (A)

300

Peak Half Sine Wave

On-State Current (A)

At any rated load condition and with

rated VRRM applied following surge.
Initial TJ = 125 C
at 60 Hz 0.0083 s
at 50 Hz 0.0100 s

325

275
250
225
200
175

Maximum non-repetitive surge current

versus pulse train duration. Control of
conduction may not be maintained.
Initial TJ = 125 C
No voltage reapplied
Rated VRRM reapplied

350

300

250

200

Per junction

Per junction

150
1
93755_06

Vishay High Power Products

10

150
0.01

100

Number of Equal Amplitude Half

Cycle Current Pulses (N)
Fig. 6 - Maximum Non-Repetitive Surge Current

0.1

Pulse Train Duration (s)

93755_07

Fig. 7 - Maximum Non-Repetitive Surge Current

ZthJC - Transient Thermal

Impedance (K/W)

10
Steady state value
RthJC = 1.05 K/W
(DC operation)
1

Per junction
0.1

0.01
0.0001

0.001

0.01

0.1

Square Wave Pulse Duration (s)

93755_08

Fig. 8 - Thermal Impedance ZthJC Characteristics

Instantaneous Gate Voltage (V)

100

10

(1) PGM = 10 W, tp = 5 ms
(2) PGM = 20 W, tp = 25 ms
(3) PGM = 50 W, tp = 1 ms
(4) PGM = 100 W, tp = 500 s

Rectangular gate pulse

(a) Recommended load line for
rated dI/dt: 10 V, 20 , tr 1 s
(b) Recommended load line for
rated dI/dt: 10 V, 65 , tr 1 s

(a)
(b)

0.1
0.001
93755_09

TJ = 40 C

VGD

TJ = 25 C

TJ = 125 C

(1)

(2)

(3)

(4)

Frequency limited by PG(AV)

IGD
0.01

0.1

10

100

Instantaneous Gate Current (A)

Fig. 9 - Gate Characteristics

LINKS TO RELATED DOCUMENTS

Dimensions
Document Number: 93755
Revision: 05-Nov-09

www.vishay.com/doc?95335
For technical questions, contact: indmodules@vishay.com

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Legal Disclaimer Notice

Vishay

Disclaimer
All product specifications and data are subject to change without notice.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf
(collectively, Vishay), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any
information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishays terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document or by any conduct of Vishay.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless
otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such
applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting
from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding
products designed for such applications.
Product names and markings noted herein may be trademarks of their respective owners.

Document Number: 91000

Revision: 18-Jul-08

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