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MIC
R
TECHNICAL FEATURE
AVE JOU
OW
OR
ED
IT
REVIEWED
IAL B O
Vds
Eds
Ids
Is
TIME (t)
8 Eds
,
Is
Zn = 0 for even n,
Zn = for odd n,
(1)
where
Eds = drain supply voltage
Is = peak drain current
n = harmonic component
These impedance conditions correspond to
the class F operating condition, the ideal voltage
and current shapes for which are shown in Figure 1. Here a sum of odd harmonics produces a
square voltage waveform and a sum of even harmonics approximates a half-sinusoidal current
shape. In reality, both extrinsic and intrinsic transistor parasitic elements have a substantial effect
on the efficiency, especially at high frequencies.
By using only the active device die it is possible
to reduce the influence of the parasitic elements
in the power amplifier module. However, in this
case it is necessary to take into account the main
influence of the device output capacitance Cout.
ANDREY V. GREBENNIKOV
Institute of Microelectronics
Singapore
Reprinted with permission of MICROWAVE JOURNAL from the July 2000 issue.
TECHNICAL FEATURE
( )
Im Yout = j Cout j
1 2L 2C 2
L 1 1 2L 2C 2 + L 2
(2)
Applying the previously mentioned three harmonic impedance conditions, open-circuited for the fundamental
and third harmonic and short-circuited for the second
harmonic, equation (2) can be rewritten in the form
)(
2
2
1 2L C
0 1 out 1 0 L 2 C 2 0 L 2 Cout = 0,
L 1 1 4 02L 2C 2 + L 2 = 0,
)(
(3)
2
in order to provide
a high impedance
TO OUTPUT
Rout
Cout
MATCHING
for odd harmonic
CIRCUIT
components.1
To
increase
maximum drain efficiency up to 88.4 Fig. 6 The microstrip impedance forming
percent, it is nec- circuits frequency response.
essary to provide a
0
short-circuit termination for all even10
harmonic voltages
and an open-cir20
cuit impedance for
third-harmonic
30
currents.3 Class F
40
operation mode is
0
0.5
1.0
1.5
2.0
2.5
easy to realize by
FREQUENCY (GHz)
using transmission
lines in the output circuit. For a microstrip amplifier, it is
enough to provide transmission lines with electrical
lengths at the fundamental frequency of
S21 (dB)
Cbypass
S21 (dB)
1 =
where
0 = 2 f0
f0 = fundamental frequency
1
6 02Cout
, L2 =
(5)
where
1
1
, 2 = tan 1
, 3 =
2
3
6
3Z0 0Cout
5
12
L1, C2 =
Cout
3
5
(4)
Linear analysis, which is sufficient to compute the response of a two-port passive circuit with lumped or distributed parameters, has been accomplished using the Serenade 7.5 CAD simulator. Simulations were performed according to the schematic shown in Figure 3 regarding the
drain of the device. The frequency-response characteristic
of a lumped impedance-peaking circuit (L1 = 7.7 nH, L2 =
TECHNICAL FEATURE
24 V
+
13.7 0.029 pF
100 pF
9.1
56.9 pH
0.73 pF
4.5 nH
10 pF
500
3.6 nH
0.31 pF
0.28 pF
0.87
2 pF
0.26 pF
Rds = 4.37 k
25 nH
15 nH
3.5 pF
Pout
1.0 pH
22
80
20
60
18
40
16
20
14
0
10.0
20.0
15.0
Pin (dBm)
EFFICIENCY (%)
100
100
22
80
20
60
18
40
16
20
14
0
10.0
12
25.0
20.0
15.0
Pin (dBm)
12
25.0
60
Vds (V)
60
40
40
20
20
0
0
2
TIME (ns)
2
TIME (ns)
EFFICIENCY (%)
1.1 pF
Vds (V)
Fig. 7
GAIN (dB)
6 pF
Pin
GAIN (dB)
1.2
= 14.1 ps
gm = 21.1mS
1.5 k
300
100
22
80
20
60
18
40
16
20
14
0
10.0
20.0
15.0
Pin (dBm)
GAIN (dB)
58.7 pH
12
25.0
EFFICIENCY (%)
28 V
+
2 pF
30
54
500
100 pF
30
65
30
58
50
63
Fig. 14
9 pF
50
46
30
54
500
Vds (V)
2 pF
100 pF
30
58
50
63
50
46
18 k
6 pF
10 15 20
Pin (dBm)
12
25 30
60
40
20
0
2
1
2
TIME (ns)
9 pF
Fig. 15 The equivalent circuit of the simulated 500 MHz one-stage microstrip high-power
amplifier using an LDMOS FET with a channel width of 28 1.44 mm.
adjacent to the drain, the value of
which becomes too small to provide
appropriate third harmonic peaking.
In this case, in order to realize both
high efficiency and high power operation, the output circuit must be simplified to only a T-section for impedance matching. The equivalent circuit of the simulated 500 MHz
one-stage microstrip high-power amplifier with a total LDMOS FET
channel width W = 28 1.44 mm is
shown in Figure 15. As it turned out,
a significant improvement of drain efficiency up to 78 percent for an output power of approximately 30 W can
be realized by using the specific electrical length (less than quarter-wave
length) of parallel microstrip line, as
shown in Figure 16. Furthermore,
the analysis of the drain voltage and
current waveforms, shown in Figure
17, demonstrates that the operating
mode obtained is close to class E operation mode.5 As seen in the data,
when the transistor is turned on,
there is practically no voltage when
the drain current achieves its maxi-
14
20
0
30
65
Pout
Pin
16
20
28 V
1.5 k
18
40
300
20
60
0
0
Pout
Pin
22
80
Ids (A)
300
1.5 k
100
GAIN (dB)
TECHNICAL FEATURE
50
35
0.1 F
1 k
0.1 F
+
50
45
10 F
50
35
9 pF
Pin
Pout
8.5 TO 40 pF
Fig. 18
4.5 TO 20 pF
100
22
80
20
60
18
40
16
20
14
0
0
10 15 20
Pin (dBm)
GAIN (dB)
EFFICIENCY (%)
TECHNICAL FEATURE
12
25 30
2.
3.
4.
5.