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1. General description
The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP),
an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to
Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears
all counter stages and forces all outputs LOW, independent of the state of CP. Each
counter stage is a static toggle flip-flop. Inputs include clamp diodes that enable the use of
current limiting resistors to interface inputs to voltages in excess of VCC.
3. Applications
Frequency dividing circuits
Time delay circuits
Control counters
4. Ordering information
Table 1.
Ordering information
Type number
74HC4040N
Package
Temperature range
Name
Description
Version
40 C to +125 C
DIP16
SOT38-1
40 C to +125 C
SO16
SOT109-1
40 C to +125 C
SSOP16
74HCT4040N
74HC4040D
74HCT4040D
74HC4040DB
74HCT4040DB
74HC4040; 74HCT4040
NXP Semiconductors
Table 1.
Type number
74HC4040PW
Package
Temperature range
Name
Description
Version
40 C to +125 C
TSSOP16
SOT403-1
40 C to +125 C
74HCT4040PW
74HC4040BQ
74HCT4040BQ
5. Functional diagram
CP
MR
10
11
T
12-STAGE COUNTER
CD
9
13
12
14
15
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11
001aad589
Fig 1.
Functional diagram
CTR12
10
11
CP
MR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
9
7
6
5
3
2
4
13
12
14
15
1
10
11
CT
11
001aad585
Fig 2.
Logic symbol
74HC_HCT4040
+
CT = 0
9
7
6
5
3
2
4
13
12
14
15
1
001aad586
Fig 3.
2 of 20
74HC4040; 74HCT4040
NXP Semiconductors
FF
T 1
CP
FF
T 2
FF
T 3
RD
FF
T 4
RD
FF
T 5
RD
FF
T 6
RD
RD
RD
MR
Q0
FF
T 7
Q1
FF
T 8
Q2
FF
T 9
RD
Q3
FF
T 10
RD
Q7
FF
T 11
RD
Q6
FF
T 12
RD
Q8
Q5
Q4
RD
Q9
RD
Q10
Q11
001aad588
Fig 4.
Logic diagram
6. Pinning information
terminal 1
index area
Q5
15 Q10
14 Q9
15 Q10
Q6
Q4
14 Q9
Q3
Q6
13 Q7
Q2
Q3
Q1
Q2
11 MR
Q1
10 CP
GND
12 Q8
Q0
13 Q7
4040
GND(1)
12 Q8
11 MR
10 CP
Q5
Q0
16 VCC
GND
Q11
Q4
4040
16 VCC
Q11
6.1 Pinning
001aad584
001aad583
Fig 5.
74HC_HCT4040
Fig 6.
3 of 20
74HC4040; 74HCT4040
NXP Semiconductors
Pin description
Symbol
Pin
Description
Q11
output 11
Q5
output 5
Q4
output 4
Q6
output 6
Q3
output 3
Q2
output 2
Q1
output 1
GND
ground (0 V)
Q0
output 0
CP
10
MR
11
Q8
12
output 8
Q7
13
output 7
Q9
14
output 9
Q10
15
output 10
VCC
16
7. Functional description
7.1 Function table
Table 3.
Function table
Input
Output
CP
MR
no change
count
[1]
Q0 to Q11
H = HIGH voltage level; L = LOW voltage level; X = dont care; = LOW-to-HIGH clock transition; = HIGH-to-LOW clock transition.
74HC_HCT4040
4 of 20
74HC4040; 74HCT4040
NXP Semiconductors
16
32
64
128
256
CP input
MR input
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
001aad587
Fig 7.
Timing diagram
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
IOK
IO
ICC
Min
Max
Unit
0.5
+7
20
mA
20
mA
output current
25
mA
supply current
50
mA
IGND
ground current
50
mA
Tstg
storage temperature
65
+150
Ptot
750
mW
500
mW
[1]
Conditions
Tamb = 40 C to +125 C
[1]
74HC_HCT4040
5 of 20
74HC4040; 74HCT4040
NXP Semiconductors
Conditions
74HC4040
Min
74HCT4040
Typ
Max
Min
Typ
Unit
Max
VCC
supply voltage
2.0
5.0
6.0
4.5
5.0
5.5
VI
input voltage
VCC
VCC
VO
output voltage
VCC
VCC
Tamb
ambient temperature
40
+25
+125
40
+25
+125
t/V
VCC = 2.0 V
625
ns/V
VCC = 4.5 V
1.67
139
1.67
139
ns/V
VCC = 6.0 V
83
ns/V
25 C
Conditions
Min
Typ
VCC = 2.0 V
1.5
VCC = 4.5 V
3.15
VCC = 6.0 V
4.2
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Min
Max
Min
Max
1.2
1.5
1.5
2.4
3.15
3.15
3.2
4.2
4.2
0.8
0.5
0.5
0.5
2.1
1.35
1.35
1.35
2.8
1.8
1.8
1.8
IO = 20 A; VCC = 2.0 V
1.9
2.0
1.9
1.9
IO = 20 A; VCC = 4.5 V
4.4
4.5
4.4
4.4
IO = 20 A; VCC = 6.0 V
5.9
6.0
5.9
5.9
3.98
4.32
3.84
3.7
5.48
5.81
5.34
5.2
IO = 20 A; VCC = 2.0 V
0.1
0.1
0.1
IO = 20 A; VCC = 4.5 V
0.1
0.1
0.1
IO = 20 A; VCC = 6.0 V
0.1
0.1
0.1
0.15
0.26
0.33
0.4
0.16
0.26
0.33
0.4
74HC4040
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
LOW-level
output voltage
VI = VIH or VIL
VI = VIH or VIL
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
0.1
1.0
1.0
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
8.0
80
160
74HC_HCT4040
6 of 20
74HC4040; 74HCT4040
NXP Semiconductors
Table 6.
Static characteristics continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
Min
CI
input
capacitance
Typ
3.5
Min
Max
Min
Max
pF
74HCT4040
VIH
HIGH-level
input voltage
2.0
1.6
2.0
2.0
VIL
LOW-level
input voltage
1.2
0.8
0.8
0.8
VOH
HIGH-level
output voltage
4.4
4.5
4.4
4.4
IO = 4 mA
3.98
4.32
3.84
3.7
LOW-level
output voltage
0.1
0.1
0.1
IO = 4.0 mA
0.15
0.26
0.33
0.4
VOL
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
0.1
1.0
1.0
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
8.0
80
160
ICC
additional
supply current
CI
input
capacitance
74HC_HCT4040
pin CP
85
306
383
417
pin MR
110
396
495
539
3.5
pF
7 of 20
74HC4040; 74HCT4040
NXP Semiconductors
25 C
Conditions
Min
Max
Min
Max
74HC4040
tpd
propagation
delay
[1]
47
150
190
225
ns
VCC = 4.5 V
17
30
38
45
ns
VCC = 5.0 V; CL = 15 pF
14
ns
VCC = 6.0 V
14
26
33
38
ns
VCC = 2.0 V
28
100
125
150
ns
VCC = 4.5 V
10
20
25
30
ns
VCC = 5.0 V; CL = 15 pF
ns
VCC = 6.0 V
17
21
26
ns
61
185
230
280
ns
22
37
46
56
ns
18
31
39
48
ns
tPHL
tt
tW
[2]
pulse width
VCC = 2.0 V
19
75
95
110
ns
VCC = 4.5 V
15
19
22
ns
VCC = 6.0 V
13
16
19
ns
VCC = 2.0 V
80
14
100
120
ns
VCC = 4.5 V
16
20
24
ns
VCC = 6.0 V
14
17
20
ns
VCC = 2.0 V
80
22
100
120
ns
VCC = 4.5 V
16
20
24
ns
VCC = 6.0 V
14
17
20
ns
VCC = 2.0 V
50
65
75
ns
VCC = 4.5 V
10
13
15
ns
VCC = 6.0 V
11
13
ns
VCC = 2.0 V
27
4.8
MHz
VCC = 4.5 V
30
82
24
20
MHz
MHz
MHz
MR input, HIGH;
see Figure 8
trec
fmax
recovery time
maximum
frequency
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
74HC_HCT4040
35
90
98
28
24
8 of 20
74HC4040; 74HCT4040
NXP Semiconductors
Table 7.
Dynamic characteristics continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 9.
Symbol Parameter
25 C
Conditions
power
dissipation
capacitance
VI = GND to VCC
[3]
[1]
20
Min
Max
Min
Max
pF
ns
30
ns
ns
74HCT4040
propagation
delay
tpd
VCC = 4.5 V
19
40
VCC = 5.0 V; CL = 15 pF
16
50
60
ns
VCC = 4.5 V
10
20
VCC = 5.0 V; CL = 15 pF
23
45
56
68
ns
15
19
22
ns
16
20
24
ns
16
20
24
ns
10
13
15
ns
30
72
24
20
MHz
79
tPHL
VCC = 4.5 V
pulse width
tW
[2]
tt
25
recovery time
trec
fmax
maximum
frequency
power
dissipation
capacitance
VI = GND to VCC
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
CPD
[1]
[2]
[3]
[3]
20
MHz
pF
74HC_HCT4040
9 of 20
74HC4040; 74HCT4040
NXP Semiconductors
MR input
1/fmax
tW
trec
VI
VM
CP input
tPHL
tPLH
tW
90 %
Q0 or Qn
output
tPHL
90 %
10 %
VM
10 %
tTLH
tTHL
001aad590
Fig 8.
Clock propagation delays, pulse width, transition times, maximum pulse frequency and master resets
74HC_HCT4040
10 of 20
74HC4040; 74HCT4040
NXP Semiconductors
VI
negative
pulse
tW
90 %
VM
VM
10 %
GND
tr
tf
tr
tf
VI
90 %
positive
pulse
GND
VM
VM
10 %
tW
VCC
G
VI
VO
DUT
RT
CL
001aah768
Fig 9.
Table 8.
Test data
Type
Input
Load
Test
VI
tr, tf
CL
74HC4040
VCC
6.0 ns
15 pF, 50 pF
tPLH, tPHL
74HCT4040
3.0 V
6.0 ns
15 pF, 50 pF
tPLH, tPHL
74HC_HCT4040
11 of 20
74HC4040; 74HCT4040
NXP Semiconductors
SOT38-1
ME
seating plane
A2
A1
c
e
b1
w M
(e 1)
b
MH
16
pin 1 index
E
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b1
D (1)
E (1)
e1
ME
MH
Z (1)
max.
mm
4.7
0.51
3.7
1.40
1.14
0.53
0.38
0.32
0.23
21.8
21.4
6.48
6.20
2.54
7.62
3.9
3.4
8.25
7.80
9.5
8.3
0.254
2.2
inches
0.19
0.02
0.15
0.055
0.045
0.021
0.015
0.013
0.009
0.86
0.84
0.26
0.24
0.1
0.3
0.15
0.13
0.32
0.31
0.37
0.33
0.01
0.087
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT38-1
050G09
MO-001
SC-503-16
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-13
12 of 20
74HC4040; 74HCT4040
NXP Semiconductors
SOT109-1
A
X
c
y
HE
v M A
Z
16
Q
A2
(A 3)
A1
pin 1 index
Lp
1
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
D (1)
E (1)
HE
Lp
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
13 of 20
74HC4040; 74HCT4040
NXP Semiconductors
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
A
X
c
y
HE
v M A
Z
9
16
Q
A2
(A 3)
A1
pin 1 index
Lp
L
8
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
D (1)
E (1)
HE
Lp
Z (1)
mm
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
1.00
0.55
8o
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT338-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-150
14 of 20
74HC4040; 74HCT4040
NXP Semiconductors
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
c
y
HE
v M A
16
Q
(A 3)
A2
A1
pin 1 index
Lp
L
8
e
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
D (1)
E (2)
HE
Lp
Z (1)
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
15 of 20
74HC4040; 74HCT4040
NXP Semiconductors
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT763-1
16 terminals; body 2.5 x 3.5 x 0.85 mm
A
A1
E
detail X
terminal 1
index area
terminal 1
index area
e1
e
2
y1 C
v M C A B
w M C
Eh
e
16
15
10
Dh
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A(1)
max.
A1
0.05
0.00
0.30
0.18
D (1)
Dh
E (1)
Eh
0.2
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
e
0.5
e1
y1
2.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT763-1
---
MO-241
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
16 of 20
74HC4040; 74HCT4040
NXP Semiconductors
14. Abbreviations
Table 9.
Abbreviations
Acronym
Description
CMOS
ESD
ElectroStatic Discharge
HBM
CDM
Charge-Device Model
TTL
Transistor-Transistor Logic
Revision history
Document ID
Release date
74HC_HCT4040 v.4
20140320
Modifications:
74HC_HCT4040 v.3
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
74HC_HCT4040 v.3
20050914
74HC_HCT4040_CNV v.2
74HC_HCT4040_CNV v.2
19901231
Product specification
74HC_HCT4040
17 of 20
74HC4040; 74HCT4040
NXP Semiconductors
Product status[3]
Definition
Development
This document contains data from the objective specification for product development.
Qualification
Production
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT4040
18 of 20
74HC4040; 74HCT4040
NXP Semiconductors
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
74HC_HCT4040
19 of 20
NXP Semiconductors
74HC4040; 74HCT4040
12-stage binary ripple counter
18. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
7.2
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 4
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveform and test circuit . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Contact information. . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section Legal information.