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Features
13
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Issue 5
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BT_RF
2.4GHz
Radio
+
Balun
SPI/ I2C
ROM
UART/USB
RAM
Baseband
Serial
Flash /
EEPROM
I /O
PIO
MCU
Audio In / Out
Kalimba
DSP
Debug SPI
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General Description
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CSR8635A04
BlueCore
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CSR's
CSR8635 QFN is a single-chip
Bluetooth ROM audio solution for rapid evaluation and
development of Bluetooth ROM stereo applications.
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Applications
Stereo speakers
Speakerphones
1-mic stereo headset or headphones
Handsfree car kits
The enhanced Kalimba DSP coprocessor with 80MIPS
supports enhanced audio and DSP applications.
The integrated audio codec supports stereo input and
output, as well as a variety of audio standards.
See CSR Glossary at www.csrsupport.com.
Production Information
Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
Page 1 of 105
CS-303725-DSP5
www.csr.com
in
Production Information
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Ordering Information
Package
Device
CSR8635 Stereo
ROM Solution
Type
Size
Shipment
Method
QFN68-lead
(Pb free)
8 x 8 x 0.9mm
0.4mm pitch
Order Number
CSR8635A04IQQFR
Note:
20
13
CSR8635 QFN is a ROM-based device where the product code has the form CSR8635Axx. Axx is the specific
ROM-variant, A04 is the ROM-variant for CSR8635 Stereo ROM Solution.
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Supply chain: CSR's manufacturing policy is to multisource volume products. For further details, contact your local
sales account manager or representative.
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General information
Information on this product
Customer support for this product
Details of compliance and standards
Help with this document
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www.csr.com
sales@csr.com
www.csrsupport.com
product.compliance@csr.com
comments@csr.com
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Description
DK8635101631A
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Order Number
Production Information
Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
Page 2 of 105
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Contacts
Device Details
Physical Interfaces
UART interface for debug
USB 2.0 (full-speed) interface, including charger
enumeration
Up to 22 general purpose PIOs with 3 extra opendrain PIOs available when LED not used
Internal ROM
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Production Information
Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
Page 3 of 105
CS-303725-DSP5
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Bluetooth Profiles
A2DP v1.2
AVRCP v1.4
HFP v1.6
HSP v1.2
DI v1.3
Music Enhancements
Volume Boost
Talk-time extension
CSR8600 ROM Series Configuration Tool
Configures the CSR8635 stereo ROM solution software
features:
Production Information
Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
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SPI
(Debug)
I C/SPI
Master
/Slave
UART
R G B
USB
Serial Flash
Interface
UART
4Mbps
LED PWM
Control and
Output
USB v2.0
Full-speed
XTAL
Clock
Generation
3.3V
PIO Port
DMA ports
AUX ADC
TX
ep
Bluetooth Modem
DMA ports
AIO[0]
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SPI_DEBUG
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Bluetooth
Baseband
ay
RX
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System
RAM
Bluetooth Radio
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LINE_BN
in
LINE_BP
SPKR_LN
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High-quality DAC
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DMA ports
SPKR_LP
SPKR_RN
High-quality DAC
SPKR_RP
-e
Audio
Interface
LINE/MIC_AP
High-quality ADC
t.c
Memory
Management
Unit
LINE/MIC_AN
High-quality ADC
VDD_AUDIO
ROM
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VDD_AUDIO_DRV
MIC Bias
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Voltage / Temperature
Monitor
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Switch
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80MHz DSP
PCM1 / I S
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DM1
80MHz MCU
PIO Port
in
PM
VM Accelerator
(MPU)
ed
DM2
MIC_BIAS
VBAT
PMU
Interface
and
BIST
Engine
0.85V to
1.2V
Low-voltage
VDD_DIG
Linear
Regulator
1.35V
Low-voltage
VDD_AUX
Linear
Regulator
SENSE
1.8V
Switchmode
Regulator
SENSE
1.35V
Switchmode
Regulator
SENSE
Bypass
LDO
Li-ion
Charger
VBAT_SENSE
CHG_EXT
VCHG
SENSE
G-TW-0012958.3.2
3V3_USB
SMPS_1V35_SENSE
LX_1V35
SMPS_1V8_SENSE
LXL_1V8
VDD_AUX
VDD_AUX_1V8
VDD_ANA
VDD_BT_RADIO
VDD_DIG
VREGIN_DIG
Production Information
Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
Digital Audio
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SENSE
1.35V
Low-voltage
VDD_ANA
Linear
Regulator
SENSE
Page 5 of 105
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Document History
Date
Change Reason
19 JUL 13
20 AUG 13
Updates include:
RF specification.
13 SEP 13
Updates include:
Package dimensions.
23 SEP 13
Updates include:
Ordering information.
RF specification.
Package information.
Power consumption.
24 SEP 13
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Revision
Production Information
Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
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Status Information
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Device Implementation
Important Note:
As the feature-set of the CSR8635 QFN is firmware build-specific, see the relevant software release note for the exact
implementation of features on the CSR8635 QFN.
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Unless otherwise stated, words and logos marked with or are trademarks registered or owned by CSR plc or its affiliates.
Bluetooth and the Bluetooth logos are trademarks owned by Bluetooth SIG, Inc. and licensed to CSR. Other products, services
and names used in this document may have been trademarked by their respective owners.
The publication of this information does not imply that any license is granted under any patent or other rights owned by CSR plc
and/or its affiliates.
CSR reserves the right to make technical changes to its products as part of its development programme.
While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept responsibility for any
errors.
Refer to www.csrsupport.com for compliance and conformance to standards information.
Production Information
Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
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The status of this Data Sheet is Production Information. CSR Product Data Sheets progress according to the following format:
Advance Information:
Information for designers concerning CSR product in development. All values specified are the target values of the design.
Minimum and maximum values specified are only given as guidance to the final specification limits and must not be
considered as the final values.
Engineering Sample:
Information about initial devices. Devices are untested or partially tested prototypes, their status is described in an
Engineering Sample Release Note. All values specified are the target values of the design. Minimum and maximum values
specified are only given as guidance to the final specification limits and must not be considered as the final values.
All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice.
Pre-production Information:
Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design. Minimum
and maximum values specified are only given as guidance to the final specification limits and must not be considered as
the final values.
Production Information:
Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications.
Contents
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6
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Production Information
Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
Page 8 of 105
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www.csr.com
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10
11
Production Information
Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
Page 9 of 105
CS-303725-DSP5
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14
15
16
16.2 6th Generation 1-mic CVC ENR Technology for Hands-free and Audio Enhancements ......................... 92
16.2.1 Acoustic Echo Cancellation ........................................................................................................ 92
16.2.2 Noise Suppression with Wind Noise Reduction ......................................................................... 93
16.2.3 Non-linear Processing (NLP) ...................................................................................................... 93
16.2.4 Howling Control (HC) .................................................................................................................. 93
16.2.5 Comfort Noise Generator ........................................................................................................... 93
16.2.6 Equalisation ................................................................................................................................ 93
16.2.7 Automatic Gain Control .............................................................................................................. 93
16.2.8 Packet Loss Concealment .......................................................................................................... 93
16.2.9 Adaptive Equalisation (AEQ) ...................................................................................................... 94
16.2.10 Auxiliary Stream Mix ................................................................................................................... 94
16.2.11 Clipper ........................................................................................................................................ 94
16.2.12 Noise Dependent Volume Control .............................................................................................. 94
Production Information
Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
Page 10 of 105
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12
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Production Information
Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
Page 11 of 105
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Figure 1.1
Figure 2.1
Figure 3.1
Figure 5.1
Figure 6.1
Figure 7.1
Figure 7.2
Figure 8.1
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
Figure 9.5
Figure 9.6
Figure 9.7
Figure 9.8
Figure 9.9
Figure 9.10
Figure 9.11
Figure 9.12
Figure 9.13
Figure 9.14
Figure 9.15
Figure 9.16
Figure 9.17
Figure 9.18
Figure 9.19
Figure 9.20
Figure 9.21
Figure 9.22
Figure 10.1
Figure 10.2
Figure 10.3
Figure 10.4
Figure 10.5
be
List of Figures
Figure 11.1
Figure 11.2
Figure 12.1
Figure 12.2
Figure 16.1
Figure 16.2
Figure 16.3
Figure 16.4
Figure 16.5
Figure 17.1
Figure 17.2
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List of Equations
Equation 3.1
Equation 3.2
Equation 7.1
Equation 8.1
Equation 8.2
Equation 9.1
Equation 9.2
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Cambridge Silicon Radio Limited 2013
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Table 3.1
Table 3.2
Table 3.3
Table 3.4
Table 7.1
Table 7.2
Table 7.3
Table 8.1
Table 9.1
Table 9.2
Table 9.3
Table 9.4
Table 9.5
Table 9.6
Table 9.7
Table 9.8
Table 9.9
Table 9.10
Table 9.11
Table 9.12
Table 10.1
Table 10.2
Table 11.1
Table 13.1
Table 13.2
13
List of Tables
Package Information
1.1
Pinout Diagram
Orientation from Top of Device
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
51
50
20
13
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12
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14
44
43
42
41
40
39
38
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17
45
36
16
46
37
ve
15
47
Pr
ep
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
G-TW-0012207.2.2
13
48
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49
Production Information
Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
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CS-303725-DSP5
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1.2
Radio
Lead
BT_RF
12
Oscillator
Lead
XTAL_IN
19
Supply Domain
Description
RF
VDD_BT_RADIO
Pad Type
Supply Domain
Description
Analogue
VDD_AUX
Pad Type
Supply Domain
18
Description
7,
Lead
r2
USB
20
13
XTAL_OUT
Pad Type
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29
Pad Type
Supply Domain
VDD_PADS_1
Description
SPI/PCM select input:
0 = PCM/PIO interface
1 = SPI
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SPI_PCM#
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Lead
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SPI/PCM Interface
VDD_USB
55
Bidirectional
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USB_DN
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56
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Note:
Lead
PIO[21]
64
PIO[18]
65
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PIO Port
Supply Domain
Description
VDD_PADS_2
VDD_PADS_2
VDD_PADS_1
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Pad Type
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SPI and PCM1 interfaces are mapped as alternative functions on the PIO port.
32
PIO[16]
27
VDD_PADS_1
PIO[15]
21
VDD_PADS_1
PIO[14]
23
VDD_PADS_1
Pr
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PIO[17]
Production Information
Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
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USB_DP
PIO Port
Lead
PIO[13]
31
Pad Type
Supply Domain
Description
VDD_PADS_1
VDD_PADS_1
VDD_PADS_1
VDD_PADS_1
22
26
25
58
PIO[8]
61
PIO[7]
57
PIO[6]
62
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VDD_PADS_2
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PIO[9]
VDD_PADS_2
VDD_PADS_2
VDD_PADS_1
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PIO[5]
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VDD_PADS_2
Production Information
Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
Page 15 of 105
CS-303725-DSP5
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PIO[10]
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PIO[11]
20
13
PIO[12]
PIO Port
Lead
PIO[4]
24
28
Supply Domain
Description
VDD_PADS_1
VDD_PADS_1
VDD_PADS_1
PIO[1]
60
VDD_PADS_2
PIO[0]
59
VDD_PADS_2
AIO[0]
20
Bidirectional
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Supply Domain
Description
VDD_PADS_1
Supply Domain
Description
Pad Type
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Lead
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VDD_AUX
35
Codec
Lead
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Pad Type
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AU_REF
Pr
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MIC_BIAS
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RST#
2
1
SPKR_RN
SPKR_RP
Microphone bias
Analogue in
VDD_AUDIO
Analogue out
VDD_AUDIO_DRV
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Cambridge Silicon Radio Limited 2013
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Page 16 of 105
CS-303725-DSP5
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PIO[2]
r2
7,
20
13
PIO[3]
Pad Type
Codec
Lead
Supply Domain
Description
Analogue out
VDD_AUDIO_DRV
SPKR_LP
10
LINE/MIC_AN
67
LINE/MIC_AP
68
LINE_BN
Analogue in
VDD_AUDIO
Analogue in
VDD_AUDIO
Pad Type
Supply Domain
Description
VDD_PADS_2
LED driver.
Alternative function: programmable
output PIO[31]
Note:
As output is open-drain, an external
pull-up is required when PIO[31] is
configured as a programmable
output.
20
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Bidirectional
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LED[2]
VDD_PADS_1
LED driver.
Alternative function: programmable
output PIO[29].
Note:
As output is open-drain, an external
pull-up is required when PIO[29] is
configured as a programmable
output.
Bidirectional
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LED[1]
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VDD_PADS_1
LED driver.
Alternative function: programmable
output PIO[30].
Note:
As output is open-drain, an external
pull-up is required when PIO[30] is
configured as a programmable
output.
37
Bidirectional
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LED[0]
Lead
Description
CHG_EXT
43
LX_1V35
50
LX_1V8
47
SMPS_1V35_SENSE
52
SMPS_1V8_SENSE
53
Production Information
Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
Page 17 of 105
CS-303725-DSP5
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LED Drivers
r2
7,
LINE_BP
13
SPKR_LN
Pad Type
Lead
Description
49
Supply via bypass regulator for 1.8V and 1.35V switchmode power
supply regulator inputs. Must be connected to the same potential as
VOUT_3V3.
SMP_VBAT
48
VSS_SMPS_1V35
51
VSS_SMPS_1V8
46
VBAT
45
VBAT_SENSE
44
VCHG
42
Charger input.
Typically connected to VBUS (USB supply) as Section 12 shows.
VDD_ANA
17
VDD_AUDIO
VDD_AUDIO_DRV
VDD_AUX
14
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Auxiliary supply.
Connect to 1.35V supply, see Section 12 for connections.
15, 16
n.
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VDD_AUX_1V8
11
38
33
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13
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VDD_BT_LO
VDD_PADS_1
Pr
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VDD_DIG
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VDD_BT_RADIO
Production Information
Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
Page 18 of 105
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20
13
SMP_BYP
Lead
Description
63
VDD_USB
54
VOUT_3V3
41
VREGENABLE
40
VREGIN_DIG
39
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Exposed pad
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VSS
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20
13
VDD_PADS_2
Production Information
Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
Page 19 of 105
CS-303725-DSP5
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Max
Description
Min
Typ
Max
A
A2
A3
A1
0.10
0.80
0.85
0.90
7.90
8.00
8.10
aaa C B
A1
0.00
0.035
0.05
E2
4.50
4.60
4.70
A2
0.65
0.67
0.35
0.40
0.45
0.203
aaa
0.10
0.15
0.20
0.25
bbb
0.10
7.90
8.00
8.10
ccc
0.08
4.50
4.60
4.70
ddd
0.10
0.40
eee
0.10
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Side View
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Notes
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1.
2.
3.
4.
n.
18
ou
1.30
17
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Seating
Plane
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Bottom View
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D2
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E2
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Pin 1 ID
52
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68
1.30
Pr
51
ar
0.30
1
ddd M C A B
Production Information
Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
G-TW-0012054.3.2
ed
fo
0.30
Description
QFN
Size
8 x 8 x 0.9mm
JEDEC
MO-220
Pitch
0.4mm pitch
Units
mm
Page 20 of 105
CS-303725-DSP5
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Typ
7,
2
aaa C A
Min
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Top View
A
Description
ccc C
Se
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em
bbb C
01
3
Package Dimensions
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,
1.3
1.4
This section lists recommendations to achieve maximum board-level reliability of the 8 x 8 x 0.9mm QFN 68-lead
package:
1.5
NSMD lands (lands smaller than the solder mask aperture) are preferred, because of the greater accuracy of
the metal definition process compared to the solder mask process. With solder mask defined pads, the overlap
of the solder mask on the land creates a step in the solder at the land interface, which can cause stress
concentration and act as a point for crack initiation.
CSR recommends that the PCB land pattern is in accordance with IPC standard IPC-7351.
Solder paste must be used during the assembly process.
Pr
ep
ar
ed
fo
rq
in
gb
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n.
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-e
xc
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po
in
t.c
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.c
-F
rid
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,S
ep
te
be
r2
7,
20
13
For information, see Typical Solder Reflow Profile for Lead-free Devices Information Note.
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Bluetooth Modem
2.1
RF Ports
2.1.1
BT_RF
CSR8635 QFN contains an on-chip balun which combines the balanced outputs of the PA on transmit and produces
the balanced input signals for the LNA required on receive. No matching components are needed as the receive mode
impedance is 50 and the transmitter has been optimised to deliver power into a 50 load.
13
VDD
20
On-chip Balun
BT_RF
VSS_BT_RF
ay
,S
G-TW-0005523.2.2
rid
-F
.c
om
po
in
t.c
LNA
-e
RF Receiver
ou
2.2
xc
el
gb
ke
ve
n.
zh
The receiver features a near-zero IF architecture that enables the channel filters to be integrated onto the die. Sufficient
out-of-band blocking specification at the LNA input enables the receiver to operate in close proximity to GSM and
WCDMA cellular phone transmitters without being desensitised. A digital FSK discriminator means that no
discriminator tank is needed and its excellent performance in the presence of noise enables CSR8635 QFN to exceed
the Bluetooth requirements for cochannel and adjacent channel rejection.
ar
ed
2.2.1
fo
rq
in
For EDR, the demodulator contains an ADC which digitises the IF received signal. This information is then passed to
the EDR modem.
2.2.2
Pr
ep
The LNA operates in differential mode and takes its input from the balanced port of the on-chip balun.
The ADC implements fast AGC. The ADC samples the RSSI voltage on a slot-by-slot basis. The front-end LNA gain
is changed according to the measured RSSI value, keeping the first mixer input signal within a limited range. This
improves the dynamic range of the receiver, improving performance in interference-limited environments.
2.3
RF Transmitter
2.3.1
IQ Modulator
The transmitter features a direct IQ modulator to minimise frequency drift during a transmit timeslot, which results in a
controlled modulation index. Digital baseband transmit circuitry provides the required spectral shaping.
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ep
te
be
r2
7,
PA
+
2.3.2
Power Amplifier
The internal PA output power is software controlled and configured through a PS Key. The internal PA on the CSR8635
QFN has a maximum output power that enables it to operate as a Class 1, Class 2 and Class 3 Bluetooth radio without
requiring an external RF PA.
2.4
Baseband
2.5.1
20
2.5
13
The Bluetooth radio synthesiser is fully integrated onto the die with no requirement for an external VCO screening can,
varactor tuning diodes, LC resonators or loop filter. The synthesiser is guaranteed to lock in sufficient time across the
guaranteed temperature range to meet the Bluetooth v4.0 specification.
ay
,S
ve
n.
zh
ou
-e
xc
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po
in
t.c
om
.c
-F
Encryption
Data whitening
Audio transcoding
Firmware performs the following voice data translations and operations:
Pr
ep
ar
ed
fo
rq
in
gb
ke
The hardware supports all optional and mandatory features of the Bluetooth v4.0 specification including AFH and
eSCO.
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ep
rid
2.5.2
te
be
r2
7,
During transmission the BMC constructs a packet from header information previously loaded into memory-mapped
registers by the software and payload data/voice taken from the appropriate ring buffer in the RAM. During reception,
the BMC stores the packet header in memory-mapped registers and the payload data in the appropriate ring buffer in
RAM. This architecture minimises the intervention required by the processor during transmission and reception.
Clock Generation
CSR8635 QFN accepts a reference clock input from either a crystal or an external clock source, e.g. a TCXO.
The external reference clock is required in active and deep sleep modes and must be present when CSR8635 QFN is
enabled.
3.1
Crystal
13
CSR8635 QFN contains a crystal driver circuit that acts as a transconductance amplifier that drives an external crystal
connected between XTAL_IN and XTAL_OUT. The crystal driver circuit forms a Pierce oscillator with the external
crystal. External capacitors are not required for standard crystals that require a load capacitance of around 9pF.
CSR recommends this option.
20
gm
be
r2
7,
ay
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-F
n
.c
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t.c
ou
-e
xc
el
po
G-TW-0011478.2.2
XTAL_OUT
in
XTAL_IN
n.
zh
External Crystal
ve
fo
rq
in
gb
ke
The on-chip capacitance is adjusted using PSKEY_XTAL_OSC_CONFIG, see Table 3.1. The default values suit a
typical crystal requiring a 9pF load capacitance. In deep sleep mode, the crystal oscillation is maintained, but at a lower
drive strength to reduce power consumption. The drive strength and load capacitance are configured with a PS Key.
Low Power Mode
PSKEY_XTAL_OSC_CONFIG [1:0]
Pr
ep
ar
ed
Normal Mode
PSKEY_XTAL_OSC_CONFIG [3:2]
00
01
10
11
00
01
10
11
XTAL_IN
(Typical)
15.6 pF
10.8 pF
6.0 pF
1.1 pF
15.6 pF
10.8 pF
6.0 pF
1.1 pF
XTAL_OUT
(Typical)
20.8 pF
16.0 pF
11.2 pF
6.4 pF
16.0 pF
11.2 pF
6.4 pF
1.5 pF
Value
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ep
te
Amplifier gm
Control LVL[3:0]
Note:
Excessive amplifier transconductance can lead to an increase in the oscillator phase noise if the oscillator amplifier
is excessively overdriven. Set the transconductance to the minimum level to give the desired oscillation ratio. Higher
values can increase power consumption. Also, insufficient drive strength can prevent the the crystal from starting
to oscillate.
3.1.1
The crystal and its load capacitor can be modelled as a frequency dependant resistive element. Consider the driver
amplifier as a circuit that provides negative resistance. For oscillation, the value of the negative resistance should be
greater than that of the crystal circuit equivalence resistance. Equation 3.1 shows how to calculate the equivalent
negative resistance.
13
gmCinCout
20
2f2(CoutCin+(C0+Cint)(Cout+Cin))2
7,
Rneg=
r2
te
ep
Min
Typ
Transconductance
Cint
Max
Unit
mS
pF
xc
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po
in
t.c
Parameter
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.c
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1.5
n.
ve
Crystal Specification
ke
3.1.2
zh
Parameter
Typ
Max
Unit
16
26
32
MHz
285
ppm
Frequency Stability
20
ppm
Crystal ESR
60
fo
rq
in
Min
Pr
ep
gb
ar
ed
Frequency
3.1.3
Crystal Calibration
The actual crystal frequency depends on the capacitance of XTAL_IN and XTAL_OUT on the PCB and the CSR8635
QFN, as well as the capacitance of the crystal.
The Bluetooth specification requires 20ppm clock accuracy. The actual frequency at which a crystal oscillates contains
two error terms, which are typically mentioned in the crystal device datasheets:
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-F
be
Where:
Initial Frequency Error: The difference between the desired frequency and the actual oscillating frequency
caused by the crystal itself and its PCB connections. It is also called as Calibration Tolerance or Frequency
Tolerance.
Frequency Stability: The total of how far the crystal can move off frequency with temperature, aging or other
effects. It is also called as Temperature Stability, Frequency Stability or Aging.
CSR8635 QFN has the capability to compensate for Initial Frequency errors by a simple per-device basis on the
production line, with the trim value stored in the non-volatile memory (PS Key). However, it is not possible to compensate
for frequency stability, therefore a crystal must be chosen with a Frequency Stability that is better than 20 ppm clock
accuracy.
13
Some crystal datasheets combine both these terms into one tolerance value. This causes a problem because only the
initial frequency error can be compensated for and CSR8635 QFN cannot compensate for the temperature or aging
performance. If frequency stability is not explicity stated, CSR cannot guarantee remaining within the Bluetooth's
20ppm frequency accuracy specification.
te
be
r2
7,
20
Crystal calibration uses a single measurement of RF output frequency and can be performed quickly as part of the
product final test. Typically, a TXSTART radio command is sent and then a measurement of the output RF frequency
is read . From this, the calibration factor to correct actual offset from the desired frequency can be calculated. This
offset value is stored in PSKEY_ANA_FTRIM_OFFSET. CSR8635 QFN then compensates for the initial frequency
offset of the crystal.
ep
ay
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rid
-F
For more information on TXSTART radio test see BlueTest User Guide.
.c
factual
fnominal
t.c
om
PSKEY_ANA_FTRIM_OFFSET = (
1) 220
xc
el
Non-crystal Oscillator
-e
3.2
po
in
ou
Apply the external reference clock to the CSR8635 QFN XTAL_IN input. Connect XTAL_OUT to ground.
Pr
ep
ar
ed
fo
rq
in
gb
ke
ve
n.
zh
The external clock is either a low-level sinusoid, or a digital-level square wave. The clock must meet the specification
in Table 3.4. The external reference clock is required in active and deep sleep modes, it must be present when CSR8635
QFN is enabled.
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The value in PSKEY_ANA_FTRIM_OFFSET is a 16-bit 2's complement signed integer which specifies the fractional
part of the ratio between the true crystal frequency, factual, and the value set in PSKEY_ANA_FREQ, fnominal. Equation
3.2 shows the value of PSKEY_ANA_FTRIM_OFFSET in parts per 220 rounded to the nearest integer.
Typ
Max
Unit
Frequency(a)
19.2
26
40
MHz
Duty cycle
40:60
50:50
60:40
10
ps
rms(b)
0.2
0.4
VDD_AUX(c)
DC coupled digital
extremes
VDD_AUX(c)
DC coupled digital
digital amplitude
0.4
30
r2
be
1.2
V pk-pk
pF
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-F
(b)
100Hz to 1MHz
(c)
t.c
in
po
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3.2.1
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.c
(a)
Pr
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ed
fo
rq
in
gb
ke
ve
n.
zh
ou
-e
The impedance of XTAL_IN does not change significantly between operating modes. When transitioning from deep
sleep to active states, the capacitive load can change. For this reason, CSR recommends using a buffered clock input.
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ep
te
Signal level
7,
AC coupled sinusoid
amplitude
20
13
Min
The CSR8635 QFN uses a 16-bit RISC 80MHz MCU for low power consumption and efficient use of memory. It contains
a single-cycle multiplier and a memory protection unit for the VM accelerator, see Section 4.1.
The MCU, interrupt controller and event timer run the Bluetooth software stack and control the Bluetooth radio and host
interfaces.
4.1
VM Accelerator
Pr
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ed
fo
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in
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t.c
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be
r2
7,
20
13
CSR8635 QFN contains a VM accelerator alongside the MCU. This hardware accelerator improves the performance
of VM applications.
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Kalimba DSP
The Kalimba DSP is an open platform DSP enabling signal processing functions to be performed on overair data or
codec data to enhance audio applications. Figure 5.1 shows the Kalimba DSP interfaces to other functional blocks
within CSR8635 QFN.
Kalimba DSP Core
13
Instruction Decode
Clock Select
PIO
ay
,S
ep
MMU Interface
Interrupt Controller
Timer
IRQ to Subsystem
IRQ from Subsystem
1s Timer Clock
rid
DSP RAMs
PIO In/Out
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DEBUG
r2
ALU
Program Flow
7,
20
Address
Generators
DM1
PM
Flash Window
G-TW-0005522.2.2
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in
t.c
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DM2
-F
MCU Window
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fo
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Pr
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n.
zh
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Data Memory
Inteface
Registers
6.1
The MMU provides dynamically allocated ring buffers that hold the data that is in transit between the host, the air or
the Kalimba DSP. The dynamic allocation of memory ensures efficient use of the available RAM and is performed by
a hardware MMU to minimise the overheads on the processor during data/voice transfers. The use of DMA ports also
helps with efficient transfer of data to other peripherals.
6.2
System RAM
20
7,
6.3
13
56KB of integrated RAM supports the RISC MCU and is shared between the ring buffers for holding voice/data for each
active connection and the general-purpose memory required by the Bluetooth stack.
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m
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,S
Internal ROM
.c
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6.5
-F
po
in
t.c
CSR8635 QFN supports external serial flash ICs. This enables additional data storage areas for device-specific data.
CSR8635 QFN supports serial single I/O devices with a 1-bit I/O flash-memory interface.
-e
xc
el
Figure 6.1 shows a typical connection between CSR8635 QFN and a serial flash IC.
ou
1.8V
n.
RESET#/HOLD#/IO3
ve
ke
WP#/IO2
QSPI_FLASH_CLK
QSPI_FLASH_CS#
QSPI_IO[0]
QSPI_IO[1]
Pr
ep
Kalimba DSP
ar
ed
Memory
Management
Unit
Serial Flash
Interface
fo
rq
in
gb
MCU Data
CLK
CS#
DI/IO0
DO/IO1
G-TW-0008502.1.2
MCU
zh
MCU Program
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6.4
rid
r2
7
7.1
Serial Interfaces
USB Interface
CSR8635 QFN has a full-speed (12Mbps) USB interface for communicating with other compatible digital devices. The
USB interface on CSR8635 QFN acts as a USB peripheral, responding to requests from a master host controller.
CSR8635 QFN contains internal USB termination resistors and requires no external resistor matching.
CSR8635 QFN supports the Universal Serial Bus Specification, Revision v2.0 (USB v2.0 Specification), supports
USB standard charger detection and fully supports the USB Battery Charging Specification, available from http://
www.usb.org. For more information on how to integrate the USB interface on CSR8635 QFN see the Bluetooth and
USB Design Considerations Application Note.
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-F
.c
om
t.c
in
po
xc
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-e
ou
UART Interface
zh
7.2
in
gb
ke
ve
n.
CSR8635 QFN has one optional standard UART serial interface that provides a simple mechanism for communicating
with other serial devices using the RS232 protocol, including for test and debug. The UART interface is multiplexed
with PIOs and other functions, and hardware flow control is optional. PS Keys configure this multiplexing, see Table
7.1.
PIO Location Option
PSKEY_UART_RX_PIO
PSKEY_UART_TX_PIO
PSKEY_UART_RTS_PIO
PSKEY_UART_CTS_PIO
Pr
ep
ar
ed
fo
rq
PS Key
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ep
te
be
r2
7,
20
13
As well as describing USB basics and architecture, the application note describes:
Power distribution for self-powered configuration, which includes USB VBUS monitoring
USB enumeration
Electrical design guidelines for the power supply and data lines, as well as PCB tracks and the effects of ferrite
beads
Global suspend
Wake on Bluetooth, includes permitted devices and set-up prior to selective suspend
Battery charging from USB, which describes dead battery provision, charge currents, charging in suspend
modes and USB VBUS voltage consideration
UART_TX
PIO[0] or PIO[14]
UART_RX
PIO[8] or PIO[16]
UART_RTS
PIO[9] or PIO[17]
UART_CTS
20
13
PIO[1] or PIO[15]
r2
7,
G-TW-0008555.2.2
Figure 7.1 shows the 4 signals that implement the UART function.
ay
,S
UART configuration parameters, such as baud rate and packet format, are set using CSR8635 QFN firmware.
rid
Note:
.c
-F
To communicate with the UART at its maximum data rate using a standard PC, the PC requires an accelerated
serial port adapter card.
in
t.c
om
zh
ou
Baud rate
-e
Minimum
xc
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po
Parameter
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ke
RTS/CTS or None
gb
Flow control
4Mbaud (1%Error)
n.
Maximum
Possible Values
rq
fo
1 or 2
Pr
ep
ar
ed
in
Parity
Table 7.3 lists common baud rates and their associated values for the PSKEY_UART_BAUDRATE. There is no
requirement to use these standard values. Any baud rate within the supported range is set in the PS Key according to
the formula in Equation 7.1.
Baud Rate =
PSKEY_UART_BAUDRATE
0.004096
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ep
te
be
When CSR8635 QFN is connected to another digital device, UART_RX and UART_TX transfer data between the 2
devices. The remaining 2 signals, UART_CTS and UART_RTS, implement optional RS232 hardware flow control where
both are active low indicators.
Error
Dec
1200
0x0005
1.73%
2400
0x000a
10
1.73%
4800
0x0014
20
1.73%
9600
0x0027
39
-0.82%
19200
0x004f
79
0.45%
38400
0x009d
157
57600
0x00ec
236
76800
0x013b
315
115200
0x01d8
472
230400
0x03b0
944
0.03%
460800
0x075f
1887
-0.02%
921600
0x0ebf
3775
0.00%
1382400
0x161e
5662
-0.01%
1843200
0x1d7e
7550
0.00%
2764800
0x2c3d
11325
0.00%
15099
0.00%
-0.18%
0.03%
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-F
n
.c
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t.c
in
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-e
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zh
n.
ve
3686400
0.03%
fo
7.3
rq
in
gb
ke
0x3afb
0.14%
Pr
ep
CSR8635 QFN provides a debug SPI interface for programming, configuring (PS Keys) and debugging the CSR8635
QFN. Access to this interface is required in production. Ensure the 4 SPI signals and the SPI_PCM# line are brought
out to either test points or a header. To use the SPI interface, the SPI_PCM# line requires the option of being pulled
high externally.
CSR provides development and production tools to communicate over the SPI from a PC, although a level translator
circuit is often required. All are available from CSR.
7.3.1
Multi-slave Operation
Avoid connecting CSR8635 QFN in a multi-slave arrangement by simple parallel connection of slave MISO lines. When
CSR8635 QFN is deselected (SPI_CS# = 1), the SPI_MISO line does not float. Instead, CSR8635 QFN outputs 0 if
the processor is running or 1 if it is stopped.
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ep
te
be
r2
7,
20
13
Hex
7.4
IC EEPROM Interface
CSR8635 QFN supports optional IC EEPROM for storage of PS Keys and voice prompt data if SPI flash is not used.
Figure 7.2 shows an example IC EEPROM connection where:
1.8V
R1
R2
R3
2.2k 2.2k 2.2k
C1
10nF
G-TW-0008557.1.1
20
r2
be
ay
,S
24AAxxx
rid
-F
Note:
t.c
om
.c
The IC EEPROM requires external pull-up resistors, see Figure 7.2. Ensure that external pull-up resistors are
suitably sized for the IC interface speed and PCB track capacitance.
xc
el
po
in
To minimise boot time, CSR recommends using 400kHz capable IC EEPROMs and I2C_CONFIG and
ANA_FREQ should be the first 2 keys in the EEPROM PS-store image.
Pr
ep
ar
ed
fo
rq
in
gb
ke
ve
n.
zh
ou
-e
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ep
te
1
A0
2
A1
3
A2
4
VSS
7,
8
VCC
7
WP
6
SCL
5
SDA
PIO[12]/QSPI_FLASH_CS#/I2C_WP
PIO[10]/QSPI_FLASH_CLK/I2C_SCL
PIO[11]/QSPI_IO[0]/I2C_SDA
13
U1
Interfaces
8.1
CSR8635 QFN provides 22 lines of programmable bidirectional I/O, PIO[21:0]. Some of the PIOs on the CSR8635
QFN have alternative functions, see Table 8.1.
Function
SPI Flash
(See Section 6.5)
UART
(See Section 7.2)
PCM
(See Section 9.3)
EEPROM
(See Section 7.4)
PIO[0]
UART_RX (default)
PIO[1]
UART_TX (default)
PIO[2]
SPI_MOSI
PCM1_IN
PIO[3]
SPI_MISO
PCM1_OUT
te
PIO[4]
SPI_CS#
PCM1_SYNC
PIO[5]
SPI_CLK
PIO[8]
UART_RTS (default)
PIO[9]
UART_CTS (default)
PIO[10]
QSPI_FLASH_CLK
PIO[11]
QSPI_IO[0]
PIO[12]
QSPI_FLASH_CS#
PIO[13]
QSPI_IO[1]
PIO[14]
PIO[15]
PIO[16]
PIO[17]
20
7,
r2
be
m
ep
rid
-
I2C_SCL
I2C_SDA
I2C_WP
UART_RX
UART_TX
UART_RTS
UART_CTS
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ve
n.
zh
ou
-e
po
in
t.c
om
.c
-F
xc
el
PCM1_CLK
gb
in
rq
fo
ar
ed
Note:
See the relevant software release note for the implementation of these PIO lines, as they are firmware buildspecific.
8.2
CSR8635 QFN has 1 general-purpose analogue interface pin, AIO[0]. Typically, this connects to a thermistor for battery
pack temperature measurements during charge control. See Section 12 for typical connections.
8.3
LED Drivers
CSR8635 QFN includes a 3-pad synchronised PWM LED driver for driving RGB LEDs for producing a wide range of
colours. All LEDs are controlled by firmware.
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Pr
ep
13
Debug SPI
(See Section 7.3)
ay
,S
PIO
The terminals are open-drain outputs, so the LED must be connected from a positive supply rail to the pad in series
with a current-limiting resistor.
LED Supply
ILED
RLED
RON = 20
ay
,S
rid
LED
in
t.c
VDD V
po
ILED =
om
.c
-F
From Figure 8.1 it is possible to derive Equation 8.1 to calculate ILED. If a known value of current is required through
the LED to give a specific luminous intensity, then the value of RLED is calculated.
+R
ON
xc
el
VDD = VF + VR + VPAD
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ve
n.
zh
ou
-e
For the LED pads to act as resistance, the external series resistor, RLED, needs to be such that the voltage drop across
it, VR, keeps VPAD below 0.5V. Equation 8.2 also applies.
in
gb
Note:
rq
The supply domain in Section 1.2 for LED[2:0] must remain powered for LED functions to operate.
Pr
ep
ar
ed
fo
The LED current adds to the overall current. Conservative LED selection extends battery life.
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ep
te
be
r2
G-TW-0005534.2.2
7,
20
13
LED[2, 1 or 0]
Audio Interface
Configurable PCM (PCM1) and IS interfaces, for configuration information contact CSR
Figure 9.1 shows the functional blocks of the interface. The codec supports stereo/dual-mono playback and recording
of audio signals at multiple sample rates with a 16-bit resolution. The ADC and the DAC of the codec each contain 2
independent high-quality channels. Any ADC or DAC channel runs at its own independent sample rate.
20
13
Digital
Audio
Voice Port
2 x Differential
ADC Inputs
t.c
om
.c
Registers
2 x Differential
DAC Outputs
G-TW-0012978.1.1
ay
,S
rid
-F
n
Register Interface
Stereo
Audio
Codec
Driver
po
in
-e
xc
el
The interface for the digital audio bus shares the same pins as the PCM1 codec interface described in Section 9.3.
Table 9.1 lists the alternative functions.
ou
Important Note:
ve
n.
zh
The term PCM in Section 9.3 and its subsections refers to the PCM1 interface.
IS Interface
gb
ke
PCM Interface
SD_OUT
PCM_IN
SD_IN
PCM_SYNC
WS
PCM_CLK
SCK
Pr
ep
ar
ed
fo
rq
in
PCM_OUT
Table 9.1: Alternative Functions of the Digital Audio Bus Interface on the PCM1 Interface
9.1
The audio input circuitry consists of 2 independent 16-bit high-quality ADC channels:
1 input programmable as either microphone or line input, the other as line input only
Each channel has an analogue and digital programmable gain stage, this also aids optimisation of different
microphones
The audio output circuitry consists of a dual differential class A-B output stage.
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ep
te
Memory
Management
Unit
be
r2
7,
PCM1 Interface
Note:
CSR8635 QFN is designed for a differential audio output. If a single-ended audio output is required, use an external
differential to single-ended converter.
9.2
Stereo and mono analogue input for voice band and audio band
Stereo and mono analogue output for voice band and audio band
Support for PCM interface including PCM master codecs that require an external system clock
13
Important Note:
be
ep
te
9.2.1
r2
7,
20
To avoid any confusion regarding stereo operation this data sheet explicitly states which is the left and right channel
for audio output. With respect to audio input, software and any registers, channel 0 or channel A represents the
left channel and channel 1 or channel B represents the right channel.
High-quality ADC
Digital Codec
16
Input B
Digital Codec
16
Input A
High-quality DAC
16
High-quality DAC
16
LINE/MIC_AP
High-quality ADC
t.c
om
LINE/MIC_AN
.c
-F
rid
LINE_BN
Digital Circuitry
po
SPKR_LN
xc
el
SPKR_LP
-e
Low-pass Filter
SPKR_RP
n.
zh
Low-pass Filter
ou
SPKR_RN
G-TW-0012979.2.2
in
ke
ve
fo
ADC
ar
ed
9.2.2
rq
in
gb
The CSR8635 QFN audio codec uses a fully differential architecture in the analogue signal path, which results in low
noise sensitivity and good power supply rejection while effectively doubling the signal amplitude. It operates from a
dual power supply, VDD_AUDIO for the audio circuits and VDD_AUDIO_DRV for the audio driver circuits.
Pr
ep
There are 2 gain stages for each channel, 1 of which is an analogue gain stage and the other is a digital gain
stage, see Section 9.2.4.
9.2.3
Each ADC supports the following pre-defined sample rates, although other rates are programmable, e.g. 40kHz:
8kHz
11.025kHz
16kHz
22.050kHz
24kHz
32kHz
44.1kHz
48kHz
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LINE_BP
ay
,S
9.2.4
To Digital Codec
20
13
Audio Input
r2
7,
System Gain = ADC Pre-amplifier + ADC Analogue Gain + ADC Digital Gain
be
te
po
xc
el
9.2.6
in
t.c
om
.c
-F
rid
ay
,S
CSR8635 QFN has an analogue gain stage based on an ADC pre-amplifier and ADC analogue amplifier:
The ADC pre-amplifier has 4 gain settings: 0dB, 9dB, 21dB and 30dB
The overall analogue gain for the pre-amplifier and analogue amplifier is -3dB to 42dB in 3dB steps, see Figure
9.3
At mid to high gain levels it acts as a microphone pre-amplifier, see Section 9.2.13
ou
-e
A digital gain stage inside the ADC varies from -24dB to 21.5dB, see Table 9.2. There is also a fine gain interface with
a 9-bit gain setting allowing gain changes in 1/32 steps, for more information contact CSR.
ve
n.
zh
-24
3.5
-20.5
10
-18
9.5
11
-14.5
12
12
-12
15.5
13
-8.5
18
14
-6
21.5
15
-2.5
gb
ke
rq
fo
Pr
ep
ar
ed
in
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ep
9.2.5
G-TW-0005535.4.3
ADC Pre-amplifier:
ADC Analogue Gain:
0dB, 9dB, 21dB and 30dB -3dB to 12dB in 3dB steps
9.2.7
G.722 filter is a digital IIR filter that improves the stop-band attenuation required for G.722 compliance (which
is the best selection for 8kHz / 16kHz / voice)
For more information contact CSR.
9.2.8
DAC
7,
r2
9.2.9
20
13
2 fourth-order Sigma-Delta converters enabling 2 separate channels that are identical in functionality, as Figure
9.2 shows.
2 gain stages for each channel, 1 of which is an analogue gain stage and the other is a digital gain stage.
ay
,S
rid
-F
n
.c
om
t.c
po
in
-e
xc
el
A digital gain stage inside the DAC varies from -24dB to 21.5dB, see Table 9.3. There is also a fine gain interface with
a 9-bit gain setting enabling gain changes in 1/32 steps, for more information contact CSR.
ve
n.
zh
ou
The overall gain control of the DAC is controlled by the firmware. Its setting is a combined function of the digital and
analogue amplifier settings.
Digital Gain Selection
Value
-24
3.5
-20.5
10
-18
9.5
11
-14.5
12
12
-12
15.5
13
-8.5
18
14
-6
21.5
15
-2.5
gb
rq
fo
ar
ed
Pr
ep
in
0
1
ke
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ep
te
be
8kHz
11.025kHz
16kHz
22.050kHz
32kHz
40kHz
44.1kHz
48kHz
96kHz
The firmware controls the overall gain control of the DAC. Its setting is a combined function of the digital and analogue
amplifier settings.
DAC Analogue Gain
Setting (dB)
-12
-3
-15
-6
-18
-9
-21
20
13
r2
7,
be
ay
,S
rid
-F
in
t.c
om
.c
CSR8635 QFN contains an independent low-noise microphone bias generator. The microphone bias generator is
recommended for biasing electret condensor microphones. Figure 9.4 shows a biasing circuit for microphones with a
sensitivity between about 40 to 60dB (0dB = 1V/Pa).
xc
el
ve
ke
gb
in
Microphone Bias
(MIC_BIAS)
C1
R1
C2
LINE/MIC_AP
LINE/MIC_AN
Input
Amplifier
MIC1
G-TW-0012980.1.1
Pr
ep
ar
ed
fo
rq
n.
zh
ou
The microphone bias generator derives its power from VBAT or 3V3_USB and requires no capacitor on its
output.
The microphone bias generator maintains regulation within the limits 70A to 2.8mA, supporting a 2mA source
typically required by 2 electret condensor microphones. If the microphone sits below these limits, then the
microphone output must be pre-loaded with a large value resistor to ground.
Biasing resistors R1 is 2.2k.
The input impedance at LINE/MIC_AN and LINE/MIC_AP is typically 6k.
C1 and C2 are 100/150nF if bass roll-off is required to limit wind noise on the microphone.
R1 sets the microphone load impedance and are normally around 2.2k.
-e
po
Where:
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ep
te
The DAC contains an integrated digital FIR filter with the following modes:
A narrow FIR (a very sharp roll-off at Nyquist) for G.722 compliance. Best for 8kHz / 16kHz.
13
Power supply:
Drop-out voltage:
300mV maximum
Output voltage:
1.8V or 2.6V
Output current:
70A to 2.8mA
7,
20
be
r2
Figure 9.5 and Figure 9.6 show 2 circuits for line input operation and show connections for either differential or singleended inputs.
ay
,S
C1
-F
rid
LINE/MIC_AN
.c
om
LINE_BN
-e
ou
LINE_BP
C1
LINE/MIC_AP
C2
Pr
ep
ar
ed
fo
rq
in
gb
ke
ve
n.
zh
C4
G-TW-0012981.1.1
in
t.c
LINE/MIC_AP
xc
el
po
C3
C2
LINE/MIC_AN
C3
C4
LINE_AN
G-TW-0012982.1.1
LINE_AP
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ep
te
In line input mode, the input impedance of the pins to ground varies from 6k to 34k depending on input gain setting.
The analogue output circuit comprises a DAC, a buffer with gain-setting, a low-pass filter and a class AB output stage
amplifier. Figure 9.7 shows that the output is available as a differential signal between SPKR_LN and SPKR_LP for the
left channel, and between SPKR_RN and SPKR_RP for the right channel.
SPKR_LP
SPKR_LN
G-TW-0005537.1.1
.c
-F
rid
ay
,S
SPKR_RN
po
in
t.c
om
Mono operation is a single-channel operation of the stereo codec. The left channel represents the single mono channel
for audio in and audio out. In mono operation, the right channel is the auxiliary mono channel for dual-mono channel
operation.
xc
el
In single channel mono operation, disable the other channel to reduce power consumption.
-e
Pr
ep
ar
ed
fo
rq
in
gb
ke
ve
n.
zh
ou
In some applications it is necessary to implement side tone. This side tone function involves feeding a properly gained
microphone signal in to the DAC stream, e.g. earpiece. The side tone routing selects the version of the microphone
signal from before or after the digital gain in the ADC interface and adds it to the output signal before or after the digital
gain of the DAC interface, see Figure 9.8.
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ep
te
be
r2
7,
20
13
SPKR_RP
DAC
DAC Interface
Digital Input
Digital Gain
Analogue Output
Demux
Side Tone
be
Mux
G-TW-0005375.1.1
ay
,S
Digital Gain
Analogue Input
-F
rid
Digital Output
om
.c
ADC
ADC Interface
in
t.c
-e
xc
el
po
The ADC provides simple gain to the side tone data. The gain values range from -32.6dB to 12.0dB in alternating steps
of 2.5dB and 3.5dB, see Table 9.5.
Side Tone Gain
Value
-32.6dB
-8.5dB
-30.1dB
-6.0dB
-26.6dB
10
-2.5dB
-24.1dB
11
0dB
-20.6dB
12
3.5dB
-18.1dB
13
6.0dB
-14.5dB
14
9.5dB
-12.0dB
15
12.0dB
ve
n.
zh
ou
Value
gb
ke
rq
in
ar
ed
Pr
ep
fo
The values of side tone are shown for information only. During standard operation, the application software controls
the side tone gain.
The following PS Keys configure the side tone hardware:
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ep
te
r2
7,
20
13
PSKEY_SIDE_TONE_ENABLE
PSKEY_SIDE_TONE_GAIN
PSKEY_SIDE_TONE_AFTER_ADC
PSKEY_SIDE_TONE_AFTER_DAC
13
20
The gain and coefficients are all 12-bit 2's complement signed integer with the format NN.NNNNNNNNNN.
r2
7,
Note:
te
be
The position of the binary point is between bit[10] and bit[9], where bit[11] is the most significant bit.
ay
,S
om
.c
-F
rid
=
=
=
=
=
in
t.c
01.1111111111
01.0000000000
00.0000000000
11.0000000000
10.0000000000
xc
el
po
Equation 9.1 shows the equation for the IIR filter. Equation 9.2 shows the equation for when the DC blocking is enabled.
n.
zh
ou
-e
The filter is configured, enabled and disabled from the VM via the CodecSetIIRFilterA and
CodecSetIIRFilterB traps. This requires firmware support. The configuration function takes 10 variables in the
following order:
Pr
ep
ar
ed
fo
rq
in
gb
ke
ve
0
1
2
3
4
5
6
7
8
9
:
:
:
:
:
:
:
:
:
:
Gain
b01
b02
a01
a02
b11
b12
a11
a12
DC Block (1 = enable, 0 = disable)
(1 +b
01
+b
02
2 )
1
2 )
(1 +a
+ a02 z
01 z
(1 +b
11
+b
12
2 )
1
2 )
(1 +a
+ a12 z
11 z
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ep
For example:
9.3
PCM1 Interface
Important Note:
The PCM1 interface is provided as a test interface and is only accessible when running the CSR8635 QFN in HCIonly mode.
Section 9 describes the various digital audio interfaces multiplexed on the the PCM1 interface. The PCM1 interface
also shares the same physical set of pins with the SPI interface, see Section 7.3 and Section 8.1. Either interface is
selected using SPI_PCM#:
20
13
ay
,S
rid
-F
.c
om
t.c
in
po
xc
el
-e
n.
ve
9.3.1
zh
ou
PCM_OUT
PCM_IN
PCM_CLK
PCM_SYNC
128/256/512/1536/2400kHz
8/48kHz
G-TW-0000217.3.4
Pr
ep
ar
ed
fo
rq
in
gb
ke
When configured as the master of the PCM interface, CSR8635 QFN generates PCM_CLK and PCM_SYNC.
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ep
te
be
r2
7,
Continuous transmission and reception of PCM encoded audio data over Bluetooth.
Processor overhead reduction through hardware support for continual transmission and reception of PCM
data.
A bidirectional digital audio interface that routes directly into the baseband layer of the firmware. It does not
pass through the HCI protocol layer.
Hardware on the CSR8635 QFN for sending data to and from a SCO connection.
Receives and transmits on any selection of 3 of the first 4 slots following PCM_SYNC.
PCM_OUT
PCM_IN
PCM_SYNC
G-TW-0000218.3.3
Up to 2400kHz
PCM_CLK
13
8/48kHz
7,
r2
9.3.2
20
ay
,S
rid
om
.c
-F
PCM_SYNC
G-TW-0000219.2.2
po
xc
el
-e
PCM_OUT
ou
in
t.c
PCM_CLK
PCM_IN
Undefined
ve
n.
zh
Undefined
ke
Figure 9.11: Long Frame Sync (Shown with 8-bit Companded Sample)
fo
ar
ed
9.3.3
rq
in
gb
CSR8635 QFN samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge.
PCM_OUT is configurable as high impedance on the falling edge of PCM_CLK in the LSB position or on the rising edge.
Pr
ep
In Short Frame Sync, the falling edge of PCM_SYNC indicates the start of the PCM word. PCM_SYNC is always 1
clock cycle long.
PCM_SYNC
PCM_OUT
PCM_IN
Undefined
10 11 12 13 14 15 16
10 11 12 13 14 15 16
Undefined
G-TW-0000220.2.3
PCM_CLK
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ep
te
be
Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or samples. In
Long Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When CSR8635 QFN is
configured as PCM master, generating PCM_SYNC and PCM_CLK, then PCM_SYNC is 8 bits long. When CSR8635
QFN is configured as PCM Slave, PCM_SYNC is from 1 cycle PCM_CLK to half the PCM_SYNC rate.
As with Long Frame Sync, CSR8635 QFN samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT
on the rising edge. PCM_OUT is configurable as high impedance on the falling edge of PCM_CLK in the LSB position
or on the rising edge.
9.3.4
Multi-slot Operation
More than 1 SCO connection over the PCM interface is supported using multiple slots. Up to 3 SCO connections are
carried over any of the first 4 slots.
LONG_PCM_SYNC
Or
20
13
SHORT_PCM_SYNC
7 8
PCM_IN
Do Not Care 1
7 8
ay
,S
rid
8 Do Not Care
-F
G-TW-0000221.3.2
te
ep
om
GCI Interface
t.c
9.3.5
.c
Figure 9.13: Multi-slot Operation with 2 Slots and 8-bit Companded Samples
xc
el
po
in
CSR8635 QFN is compatible with the GCI, a standard synchronous 2B+D ISDN timing interface. The 2 64kbps B
channels are accessed when this mode is configured.
zh
ou
-e
PCM_SYNC
in
rq
fo
Do Not
Care
Pr
ep
ar
ed
PCM_IN
B1 Channel
B2 Channel
Do Not
Care
G-TW-0000222.2.3
gb
PCM_OUT
ke
ve
n.
PCM_CLK
The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8kHz.
9.3.6
CSR8635 QFN receives and transmits on any selection of the first 4 slots following each sync pulse. Slot durations are
either 8 or 16 clock cycles:
13-bit linear, 16-bit linear and 8-bit -law or A-law sample formats.
For 16-bit slots, the 3 or 8 unused bits in each slot are filled with sign extension, padded with zeros or a
programmable 3-bit audio attenuation compatible with some codecs.
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PCM_OUT
be
r2
7,
PCM_CLK
Sign
Extension
PCM_OUT
10
11
12
13
14
15
16
8-bit
Sample
A 16-bit slot with 8-bit companded sample and sign extension selected.
8-bit
Sample
PCM_OUT
10
11
12
13
14
15
16
13
Zeros
Padding
r2
7,
20
A 16-bit slot with 8-bit companded sample and zeros padding selected.
10
11
12
13
14
15
16
15
16
-F
rid
A 16-bit slot with 13-bit linear sample and sign extension selected.
.c
8
10
11
12
13
14
G-TW-0000223.2.3
om
t.c
Audio
Gain
xc
el
po
in
PCM_OUT
13-bit
Sample
-e
A 16-bit slot with 13-bit linear sample and audio gain selected.
n.
Additional Features
ve
9.3.7
zh
ou
in
rq
fo
Parameter
Pr
ep
Symbol
fmclk
Min
ar
ed
9.3.8
gb
ke
CSR8635 QFN has a mute facility that forces PCM_OUT to be 0. In master mode, CSR8635 QFN is compatible with
some codecs which control power down by forcing PCM_SYNC to 0 while keeping PCM_CLK running.
Typ
Max
Unit
kHz
128
48MHz DDS
generation. Selection of
frequency is
programmable. See
Section 9.3.10.
2.9
kHz
kHz
980
ns
512
PCM_CLK frequency
tmclkh (a)
PCM_CLK high
256
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13-bit
Sample
te
ep
ay
,S
PCM_OUT
be
Sign
Extension
Typ
Max
Unit
730
ns
PCM_CLK jitter
21
ns pk-pk
tdmclksynch
20
ns
tdmclkpout
20
ns
tdmclklsyncl
20
tdmclkhsyncl
tdmclklpoutz
tdmclkhpoutz
tsupinclkl
thpinclkl
20
ns
7,
PCM_CLK low
r2
tmclkl (a)
13
Min
20
ns
20
ns
20
ns
20
ns
ns
be
Parameter
ay
,S
rid
-F
n
.c
om
t.c
in
xc
el
po
ep
te
Symbol
-e
ou
(a)
n.
zh
t dmclklsyncl
t dmclkhsyncl
ke
ve
t dmclksynch
rq
in
gb
PCM_SYNC
t mclkh
t mclkl
Pr
ep
ar
ed
fo
f mlk
PCM_CLK
t dmclklpoutz
PCM_OUT
MSB (LSB)
t supinclkl
PCM_IN
tr ,t f
t dmclkhpoutz
LSB (MSB)
t hpinclkl
MSB (LSB)
LSB (MSB)
G-TW-0000224.2.3
t dmclkpout
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t dmclksynch
t dmclkhsyncl
PCM_SYNC
f mlk
t mclkh
t mclkl
PCM_CLK
20
t dmclkhpoutz
LSB (MSB)
be
m
te
ep
LSB (MSB)
-F
rid
MSB (LSB)
Pr
ep
ar
ed
fo
rq
in
gb
ke
ve
n.
zh
ou
-e
xc
el
po
in
t.c
om
.c
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PCM_IN
t hpinclkl
ay
,S
t supinclkl
G-TW-0000225.3.3
MSB (LSB)
r2
PCM_OUT
tr ,t f
7,
t dmclkpout
13
t dmclklpoutz
Parameter
Min
Typ
Max
Unit
fsclk
64
(a)
kHz
fsclk
128
(b)
kHz
tsclkl
200
ns
tsclkh
200
ns
thsclksynch
ns
tsusclksynch
20
tdpout
tdsclkhpout
tdpoutz
tsupinsclkl
thpinsclkl
ns
20
ns
15
ns
15
ns
20
ns
ns
ay
,S
rid
-F
xc
el
po
in
t.c
om
.c
ep
te
be
r2
7,
20
13
Symbol
-e
(b)
t sclkh
f sclk
t tsclkl
in
gb
ke
ve
n.
zh
ou
(a)
Pr
ep
ar
ed
fo
rq
PCM_CLK
t hsclksynch
t susclksynch
PCM_SYNC
t dpoutz
PCM_OUT
MSB (LSB)
t supinsclkl
PCM_IN
t dsclkhpout
tr ,t f
t dpoutz
LSB (MSB)
t hpinsclkl
MSB (LSB)
LSB (MSB)
G-TW-0000226.3.2
t dpout
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f sclk
t sclkh
t tsclkl
PCM_CLK
t susclksynch
t hsclksynch
PCM_SYNC
ay
,S
LSB (MSB)
13
.c
9.3.9
-F
rid
in
po
n.
zh
ou
-e
Generating these signals by DDS from CSR8635 QFN internal 4MHz clock. Using this mode limits PCM_CLK
to 128, 256 or 512kHz and PCM_SYNC to 8kHz.
Generating these signals by DDS from an internal 48MHz clock, which enables a greater range of frequencies
to be generated with low jitter but consumes more power. To select this second method set bit
48M_PCM_CLK_GEN_EN in PSKEY_PCM_CONFIG32. When in this mode and with long frame sync, the
length of PCM_SYNC is either 8 or 16 cycles of PCM_CLK, determined by LONG_LENGTH_SYNC_EN in
PSKEY_PCM_CONFIG32.
xc
el
t.c
om
CSR8635 QFN has 2 methods of generating PCM_CLK and PCM_SYNC in master mode:
ke
ve
PSKEY_PCM_USE_LOW_JITTER_MODE sets the low jitter mode when the sync rate is 8kHz and the PCM clock is
set either by PSKEY_PCM_CLOCK_RATE or through the audio API, see BlueCore Audio API Specification.
in
gb
fo
rq
Configure the PCM by using the PS Key PSKEY_PCM_CONFIG32 or through the audio API, see BlueCore Audio API
Specification. The default for PSKEY_PCM_CONFIG32 is 0x00800000, i.e. first slot following sync is active, 13-bit
9.4
Pr
ep
ar
ed
linear voice format, long frame sync and interface master generating 256kHz PCM_CLK from 4MHz internal clock with
no tristate of PCM_OUT.
Important Note:
The IS interface is provided as a test interface and is only accessible when running the CSR8635 QFN in HCIonly mode.
The digital audio interface supports the industry standard formats for IS, left-justified or right-justified. The interface
shares the same pins as the PCM interface, which means each audio bus is mutually exclusive in its usage. Table
9.8 lists these alternative functions. Figure 9.20 shows the timing diagram.
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MSB (LSB)
PCM_IN
G-TW-0000227.3.2
be
m
te
t hpinsclkl
ep
t supinsclkl
t dpoutz
20
LSB (MSB)
MSB (LSB)
7,
PCM_OUT
tr ,t f
r2
t dsclkhpout
t dpoutz
PCM Interface
IS Interface
PCM_OUT
SD_OUT
PCM_IN
SD_IN
PCM_SYNC
WS
PCM_CLK
SCK
Table 9.8: Alternative Functions of the Digital Audio Bus Interface on the PCM Interface
Right Channel
be
r2
Left Channel
7,
WS
20
13
Configure the digital audio interface using PSKEY_DIGITAL_AUDIO_CONFIG, see and the PS Key file.
LSB
MSB
LSB
rid
MSB
ay
,S
SD_IN/OUT
ep
te
SCK
WS
om
.c
-F
Right Channel
po
in
t.c
Left Channel
SD_IN/OUT
ou
-e
xc
el
SCK
LSB
n.
zh
MSB
MSB
LSB
ke
ve
gb
WS
Right Channel
SD_IN/OUT
MSB
LSB
MSB
I2 S Mode
LSB
G-TW-0000230.3.2
Pr
ep
ar
ed
SCK
fo
rq
in
Left Channel
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Symbol
Parameter
Min
Typ
Max
Unit
SCK Frequency
6.2
MHz
WS Frequency
96
kHz
tch
80
ns
tcl
80
ns
Typ
Max
tssu
20
tsh
2.5
topd
tisu
20
tih
2.5
20
Min
Unit
ns
ns
20
ns
ns
ns
be
r2
7,
Parameter
ay
,S
rid
xc
el
po
in
t.c
om
.c
-F
ep
te
Symbol
13
ou
-e
ke
ve
n.
zh
WS(Input)
t cl
fo
topd
SD_OUT
t isu
SD_IN
t ih
G-TW-0000231.2.2
Pr
ep
ar
ed
SCK(Input)
t ch
t sh
rq
in
gb
t ssu
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Symbol
Parameter
Min
Typ
Max
Unit
SCK Frequency
6.2
MHz
WS Frequency
96
kHz
Parameter
Min
Typ
Max
Unit
ns
39.27
topd
18.44
tisu
18.44
tih
ns
ns
ns
ay
,S
rid
ep
te
be
r2
7,
20
13
tspd
om
.c
-F
in
xc
el
po
t spd
t.c
WS(Output)
t opd
t isu
ar
ed
fo
rq
in
gb
SD_OUT
Pr
ep
SD_IN
t ih
G-TW-0000232.2.2
ke
ve
n.
zh
ou
-e
SCK(Output)
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ay
,S
rid
-F
.c
om
Supply
Configuration
Regulators
1.8V
1.35V
OFF
OFF
SMPS
SMPS
ON
ON
SMPS
LDO
ON
ON
ON
SMPS
LDO
OFF
ON
ON
External
LDO
ON
ON
Single-supply
SMPS
ON
OFF
Parallelsupply SMPS
ON
Linear supply
OFF
xc
el
Dual-supply
SMPS
-e
1.35V
ar
ed
fo
rq
in
gb
ke
ve
zh
ou
1.8V
in
t.c
po
VDD_AUX
Linear
Regulator
Supply Rail
VDD_ANA
Linear
Regulator
n.
Switch-mode
Pr
ep
For more information on CSR8635 QFN power supply configuration see the Configuring the Power Supplies on
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ep
te
be
r2
7,
20
13
For greater power efficiency the CSR8635 QFN contains 2 switch-mode regulators:
1 generates a 1.80V supply rail with an output current of 185mA, see Section 10.1.
1 generates a 1.35V supply rail with an output current of 160mA, see Section 10.2.
Combining the 2 switch-mode regulators in parallel generates a single 1.80V supply rail with an output current
of 340mA, see Section 10.3.
CSR8635 QFN contains 4 LDO linear regulators:
3 switch-mode configurations:
A 1.80V and 1.35V dual-supply rail system using the 1.80V and 1.35V switch-mode regulators, see Figure
10.1. This is the default power control and regulation configuration for the CSR8635 QFN.
A 1.80V parallel-supply rail system for higher currents using the 1.80V and 1.35V switch-mode regulators
with combined outputs, see Figure 10.2.
VCHG
VBAT_SENSE
EN
Charger
50 to 200mA
VBAT
Charge
Reference
OUT
VOUT_3V3
Bypass Linear
Regulator
SMP_BYP
SMP_VBAT
IN
1.35V OUT
Switch-mode
RegulatorSENSE
EN
LX_1V35
SMPS_1V35_SENSE
IN
OUT
1.8V
Switch-mode
RegulatorSENSE
EN
20
13
Reference
r2
7,
LX_1V8
VREGENABLE
be
SMPS_1V8_SENSE
ep
te
ay
,S
EN
VDD_AUX_1V8
OUT
VDD_AUX
-F
rid
SENSE
Auxiliary Circuits
VDD_AUX
Regulator
IN
om
.c
VDD_ANA
Regulator
SENSE
Bluetooth
VDD_BT_RADIO
VDD_BT_LO
-e
ou
VDD_ANA
VDD_BT_RADIO
xc
el
po
in
t.c
EN
OUT
VDD_PADS_1
I/O
ve
n.
zh
VDD_PADS_2
fo
rq
in
gb
ke
Audio Circuits
ar
ed
Audio Driver
VDD_AUDIO_DRV
Pr
ep
Audio Core
VDD_AUDIO
EN
IN
VDD_DIG
Regulator
OUT
SENSE
VREGIN_DIG
VDD_DIG
G-TW-0012182.2.2
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VCHG
VBAT_SENSE
EN
Charger
50 to 200mA
VBAT
Charge
Reference
OUT
VOUT_3V3
Bypass Linear
Regulator
SMP_BYP
SMP_VBAT
IN
1.35V SENSE
Switch-mode
Regulator OUT
EN
SMPS_1V35_SENSE
LX_1V35
IN
OUT
1.8V
Switch-mode
RegulatorSENSE
EN
20
13
Reference
r2
7,
LX_1V8
VREGENABLE
be
SMPS_1V8_SENSE
ep
te
VDD_AUX_1V8
ay
,S
OUT
VDD_AUX
-F
Auxiliary Circuits
rid
SENSE
EN
VDD_AUX
Regulator
IN
om
.c
VDD_ANA
Regulator
SENSE
Bluetooth
VDD_BT_RADIO
VDD_BT_LO
-e
ou
VDD_ANA
VDD_BT_RADIO
xc
el
po
in
t.c
EN
OUT
VDD_PADS_1
I/O
ve
n.
zh
VDD_PADS_2
fo
rq
in
gb
ke
Audio Circuits
Pr
ep
ar
ed
Audio Driver
VDD_AUDIO_DRV
Audio Core
VDD_AUDIO
VDD_DIG
Regulator
OUT
SENSE
VREGIN_DIG
VDD_DIG
G-TW-0012183.2.2
EN
10.1
CSR recommends using the integrated switch-mode regulator to power the 1.80V supply rail.
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Figure 10.3 shows that an external LC filter circuit of a low-resistance series inductor, L1 (4.7H), followed by a low
ESR shunt capacitor, C3 (2.2F), is required between the LX_1V8 terminal and the 1.80V supply rail. Connect the
1.80V supply rail and the VDD_AUX_1V8 pin.
VBAT
3V3_USB
C1
2.2F
LX_1V8
LX
1.8V Switch-mode
Regulator
SENSE
C2
2.2F
SMPS_1V8_SENSE
VSS_SMPS_1V8
20
13
To 1.35V Switch-mode
Regulator Input
G-TW-0008945.1.2
L1
4.7H
r2
7,
ay
,S
-F
rid
Also minimise the collective parasitic capacitance on the track between LX_1V8 and the inductor L1, to maximise
efficiency.
ve
n.
zh
ou
-e
xc
el
po
in
t.c
om
.c
For the regulator to meet the specifications in Section 13.3.1.1 requires a total resistance of <1.0 (<0.5
recommended) for the following:
The track between the inductor, L1, and the sense point on the 1.80V supply rail.
The following enable the 1.80V switch-mode regulator:
VREGENABLE pin
VCHG pin
gb
ke
The switching frequency is adjustable by setting an offset from 4.00MHz using PSKEY_SMPS_FREQ_OFFSET, which
also affects the 1.35V switch-mode regulator.
10.2
ar
ed
fo
rq
in
CSR recommends using the integrated switch-mode regulator to power the 1.35V supply rail.
Figure 10.4 shows that an external LC filter circuit of a low-resistance series inductor L1 (4.7H), followed by a low
ESR shunt capacitor, C3 (4.7F), is required between the LX_1V35 terminal and the 1.35V supply rail. Connect the
1.35V supply rail and the SMPS_1V35_SENSE pin.
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ep
te
be
Minimise the series resistance of the tracks between the regulator input, VBAT and 3V3_USB, ground terminals, the
filter and decoupling components, and the external voltage source to maintain high-efficiency power conversion and
low supply ripple.
VBAT
LX
1.35V Switchmode Regulator
SENSE
3V3_USB
C1
2.2F
C2
2.2F
LX_1V35
SMPS_1V35_SENSE
VSS_SMPS_1V35
To 1.8V Switch-mode
Regulator Input
G-TW-0008946.1.2
L1
4.7H
r2
7,
20
13
Minimise the series resistance of the tracks between the regulator input, VBAT and 3V3_USB, ground terminals, the
filter and decoupling components, and the external voltage source to maintain high-efficiency power conversion and
low supply ripple.
be
-e
xc
el
po
in
t.c
om
.c
-F
rid
ay
,S
For the regulator to meet the specifications in Section 13.3.2.1 requires a total resistance of <1.0 (<0.5
recommended) for the following:
The track between the inductor, L1, and the sense point on the 1.35V supply rail.
The following enable the 1.35V switch-mode regulator:
VREGENABLE pin
VCHG pin
zh
ou
The switching frequency is adjustable by setting an offset from 4.00MHz using PSKEY_SMPS_FREQ_OFFSET, which
also affects the 1.80V switch-mode regulator.
in
10.3
gb
ke
ve
n.
Pr
ep
ar
ed
fo
For applications that require a single 1.80V supply rail with higher currents CSR recommends combining the outputs
of the integrated 1.80V and 1.35V switch-mode regulators in parallel to power a single 1.80V supply rail, see Figure
10.5.
Figure 10.5 shows that an external LC filter circuit of a low-resistance series inductor L1 (4.7H), followed by a low
ESR shunt capacitor, C3 (2.2F), is required between the LX_1V8 terminal and the 1.80V supply rail. Connect the
1.80V supply rail and the VDD_AUX_1V8 pin and ground the SMPS_1V35_SENSE pin.
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ep
te
Also minimise the collective parasitic capacitance on the track between LX_1V35 and the inductor L1, to maximise
efficiency.
VBAT
C1
2.2F
LX_1V35
LX
1.35V Switchmode Regulator
SENSE
3V3_USB
C2
2.2F
SMPS_1V35_SENSE
VSS_SMPS_1V35
L1
4.7H
1.8V Supply Rail
13
C3
2.2F
20
SMPS_1V8_SENSE
te
be
r2
7,
VSS_SMPS_1V8
G-TW-0008947.1.2
LX_1V8
LX
1.8V Switch-mode
Regulator
SENSE
ay
,S
-F
rid
Minimise the series resistance of the tracks between the regulator input VBAT and 3V3_USB, ground terminals, the
filter and decoupling components, and the external voltage source to maintain high-efficiency power conversion and
low supply ripple.
om
.c
Ensure a solid ground plane between C1, C2, C3, VSS_SMPS_1V8 and VSS_SMPS_1V35.
in
t.c
Also minimise the collective parasitic capacitance on the track between LX_1V8, LX_1V35 and the inductor L1, to
maximise efficiency.
rq
in
gb
ke
ve
n.
zh
ou
-e
xc
el
po
For the regulator to meet the specifications in Section 13.3.1.2 requires a total resistance of <1.0 (<0.5
recommended) for the following:
The track between the inductor, L1, and the sense point on the 1.80V supply rail.
The following enable the 1.80V switch-mode regulator:
VREGENABLE pin
VCHG pin
ar
ed
fo
The switching frequency is adjustable by setting an offset from 4.00MHz using PSKEY_SMPS_FREQ_OFFSET.
Pr
ep
10.4
The integrated bypass LDO linear regulator is available as a 3.30V supply rail and is an alternative supply rail to the
battery supply. This is especially useful when the battery has no charge and the CSR8635 QFN needs to power up.
The input voltage should be between 4.25V to 6.50V.
Note:
The integrated bypass LDO linear regulator can operate down to 3.1V with a reduced performance.
Externally decouple the output of this regulator using a low ESR MLC capacitor of a minimum 2.2F to the 3V3_USB
pin.
The output voltage is switched on when VCHG gets above 3.0V.
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ep
Figure 10.5: 1.8V and 1.35V Switch-mode Regulators Outputs Parallel Configuration
10.5
The integrated low-voltage VDD_DIG linear regulator powers the digital circuits on CSR8635 QFN. Externally decouple
the output of this regulator using a low ESR MLC capacitor of 470nF.
10.6
The integrated low-voltage VDD_AUX linear regulator is optionally available to provide a 1.35V auxiliary supply rail
when the 1.35V switch-mode regulator is not used. When using the integrated low-voltage VDD_AUX linear regulator,
externally decouple the output of this regulator using a low ESR MLC capacitor of a minimum 470nF to the VDD_AUX
pin.
10.7
be
10.8
r2
7,
20
13
The integrated low-voltage VDD_ANA linear regulator is optionally available to power the 1.35V analogue supply rail
when the 1.35V switch-mode regulator is not used. When using the integrated low-voltage VDD_ANA linear regulator,
externally decouple the output of this regulator using a 2.2F low ESR MLC capacitor to the VDD_ANA pin.
ay
,S
rid
-F
.c
t.c
om
The VREGENABLE pin is active high, with a pull-down, typical 100k, which is disabled by
PSKEY_VREG_ENABLE_STRONG_PULL.
xc
el
po
in
CSR8635 QFN boots-up when the voltage regulator enable pin is pulled high typically for 10 to 15ms, enabling the
regulators. The firmware then latches the regulators on. The voltage regulator enable pin can then be released.
ou
-e
The status of the VREGENABLE pin is available to firmware through an internal connection. VREGENABLE also works
as an input line.
n.
zh
Note:
ke
10.9
ve
VREGENABLE should be asserted after the VBAT supply when VREGENABLE is not used as a power-on button.
fo
rq
in
CSR recommends that the integrated regulators supply the CSR8635 QFN and it is configured based on the information
in this data sheet.
Note:
Pr
ep
ar
ed
If any of the supply rails for the CSR8635 QFN are supplied from an external regulator, then it should match or be better
than the internal regulator available on CSR8635 QFN. For more information see regulator characteristics in Section
13.
The internal regulators described in Section 10.1 to Section 10.7 are not recommended for external circuitry other
than that shown in Section 12.
For information about power sequencing of external regulators to supply the CSR8635 QFN contact CSR.
RST# pin
Power-on reset
USB charger attach reset
Software configured watchdog timer
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ep
te
When using the integrated regulators the voltage regulator enable pin, VREGENABLE, enables the CSR8635 QFN
and the following regulators:
The RST# pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. CSR
recommends applying RST# for a period >5ms.
At reset the digital I/O pins are set to inputs for bidirectional pins and outputs are set to tristate.
I/O Type
N/A
PIO[9]
Digital bidirectional
PDS
Digital bidirectional
N/A
PIO[10]
Digital bidirectional
PDS
PIO[0]
Digital bidirectional
PUS
PIO[11]
Digital bidirectional
PIO[1]
Digital bidirectional
PUS
PIO[12]
Digital bidirectional
PIO[2]
Digital bidirectional
PDW
PIO[13]
Digital bidirectional
PIO[3]
Digital bidirectional
PDW
PIO[14]
Digital bidirectional
PUS
PIO[4]
Digital bidirectional
PDW
PIO[15]
Digital bidirectional
PUS
PIO[5]
Digital bidirectional
PDW
PIO[16]
Digital bidirectional
PUS
PIO[6]
Digital bidirectional
PDS
PIO[17]
Digital bidirectional
PDS
PIO[7]
Digital bidirectional
PDS
PIO[18]
Digital bidirectional
PDW
PIO[8]
Digital bidirectional
PUS
PIO[21]
Digital bidirectional
PDW
20
USB_DN
7,
Digital bidirectional
r2
USB_DP
be
I/O Type
PDS
PUS
PDS
ay
,S
rid
-F
n
.c
om
in
po
xc
el
-e
ou
n.
zh
Note:
ke
ve
gb
rq
in
fo
ar
ed
Pr
ep
The reset protection is cleared after typically 2s (1.6s min to 2.4s max).
If RST# is held low for >2.4s CSR8635 QFN turns off. A rising edge on VREGENABLE or VCHG is required to
power on CSR8635 QFN.
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ep
te
Pin Name
13
Pin Name
t.c
11 Battery Charger
11.1
The battery charger hardware is controlled by the VM, see Section 11.3.The battery charger has 5 modes:
Disabled
Trickle charge
Fast charge
13
The battery charger operating mode is determined by the battery voltage and current, see Table 11.1 and Figure
11.1.
Disabled
No
Trickle charge
Yes
Fast charge
Yes
Standby
Yes
Error
Yes
VBAT_SENSE
ay
,S
t.c
om
.c
-F
rid
xc
el
po
in
>(VCHG - 50mV)
-e
Table 11.1: Battery Charger Operating Modes Determined by Battery Voltage and Current
Iterm is approximately 10% of Ifast for a given Ifast setting
ou
(a)
Ifast
Pr
ep
ar
ed
fo
rq
in
gb
Charge Current
ke
ve
n.
zh
Figure 11.1 shows the mode-to-mode transition voltages. These voltages are fixed and calibrated by CSR, see Section
11.2. The transition between modes can occur at any time.
Itrickle
Iterm
Vhyst
Battery Voltage
Vfast
Vfloat
G-TW-0005583.3.2
Standby Mode
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ep
te
Mode
be
r2
7,
20
The internal charger circuit can provide up to 200mA of charge current, for currents higher than this the CSR8635 QFN
can control an external pass transistor, see Section 11.5.
Note:
The battery voltage remains constant in Fast Charge Constant Voltage Mode, the curved line on Figure 11.1 is for
clarity only.
13
The Vfast threshold detection has hysteresis to prevent the charger from oscillating between modes.
20
te
be
r2
7,
When the voltage on VBAT_SENSE is greater than Vfast, the current sourced from the VBAT pin increases to Ifast.
Ifast is between 10mA and 200mA set by PS Key or a VM trap. In addition, Ifast is calibrated in production test to correct
for process variation in the charger circuit.
ep
ay
,S
-F
rid
When the current sourced is below the termination current, Iterm, the charging stops and the charger enters standby
mode. Iterm is typically 10% of the fast charge current.
om
.c
xc
el
po
in
t.c
When the battery is fully charged, the charger enters standby mode, and battery charging stops. The battery voltage
on the VBAT_SENSE pin is monitored, and when it drops below a threshold set at Vhyst below the final charging voltage,
Vfloat, the charger re-enters fast charge mode.
-e
n.
zh
ou
The charger enters the error mode if the voltage on the VCHG pin is too low to operate the charger correctly
(VBAT_SENSE is greater than VCHG - 50mV (typical)).
11.2
ke
ve
In this mode, charging is stopped. The battery charger does not require a reset to resume normal operation.
11.3
fo
rq
in
The battery charger default trim values are written by CSR into non-volatile memory when each IC is characterised.
CSR provides various PS Keys for overriding the default trims, see Section 11.4.
Pr
ep
The VM charger code has overall supervisory control of the battery charger and is responsible for:
11.4
The battery charger firmware sets up the charger hardware based on the PS Key settings and traps called from the
VM charger code. It also performs the initial analogue trimming. Settings for the charger current depend on the battery
capacity and type, which are set by the user in the PS Keys.
For more information on the CSR8635 QFN, including details on setting up, calibrating, trimming and the PS Keys, see
Lithium Polymer Battery Charger Calibration and Operation for CSR8670 application note.
Production Information
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Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
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www.csr.com
The current is held constant at Ifast until the voltage at VBAT_SENSE reaches Vfloat, then the charger reduces the current
sourced to maintain a constant voltage on the VBAT_SENSE pin.
11.5
External Mode
The external mode is for charging higher capacity batteries using an external pass device. The current is controlled by
sinking a varying current into the CHG_EXT pin, and the current is determined by measuring the voltage drop across
a resistor, Rsense, connected in series with the external pass device, see Figure 11.2. The voltage drop is determined
by looking at the difference between the VBAT_SENSE and VBAT pins. The voltage drop across Rsense is typically
200mV. The value of the external series resistor determines the charger current. This current can be trimmed with a
PS Key.
In Figure 11.2, R1 (220m) and C1 (4.7F) form an RC snubber that is required to maintain stability across all battery
ESRs. The battery ESR must be <1.0.
ay
,S
rid
VBAT_SENSE
-F
Rsense
po
in
t.c
R1
220m
ou
-e
xc
el
C1
4.7F
BAT 1
Li+ Cell
G-TW-0005585.2.3
om
.c
VBAT
Pr
ep
ar
ed
fo
rq
in
gb
ke
ve
n.
zh
Production Information
Cambridge Silicon Radio Limited 2013
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ep
te
TR 1
External Pass Device
CHG_EXT
be
r2
7,
20
13
VCHG
C7
4u7
C8
15p
C9
2u2
C10
470n
LINE/MIC_AP
VBAT
BYPASS REG
MIC_BIAS
VDD_BT_LO
39
VREGIN_DIG
11
17
13
1V8 SMPS
1V35 SMPS
3V3
AUX LDO
1V35
ANA LDO
1V35
GND GND
,S
12
BT_RF
ay
PIO[0] / UART_RX
PIO[1] / UART_TX
PIO[6]
PIO[7]
PIO[8] / UART_RTS#
PIO[9] / UART_CTS#
PIO[18]
PIO[21]
2.45GHz
-F
CSR8635 QFN
om
.c
t.c
SPI_PCM#
in
po
PIO[14] / UART_RX
PIO[15] / UART_TX
PIO[16] / UART_RTS#
PIO[17] / UART_CTS#
6
SPKR_RN
7
SPKR_RP
SPKR_RN
SPKR_RP
4
LINE_BN
9
SPKR_LN
10
SPKR_LP
5
LINE_BP
SPKR_LN
SPKR_LP
LINE_BN
2
MIC_BIAS
USB_P
USB_N
RST#
26MHz
19
18
37
36
66
LED_0
LED_1
LED_2
59
60
62
57
61
58
65
64
PIO_0
PIO_1
PIO_6
PIO_7
PIO_8
PIO_9
PIO_18
PIO_21
30
28
24
34
PIO_2
PIO_3
PIO_4
PIO_5
29
SPI_PCM#
22
25
26
31
PIO_12
PIO_10
PIO_11
PIO_13
23
21
27
32
JACK_DET_PIO
LINE/MIC_PIO
PIO_16
PIO_17
20
AIO_0
56
55
USB_P
USB_N
35
RSTB
LED outputs
PIO / UART
ke
68
LINE_BP
MIC_BIAS
AIO[0]
LINE/MIC_AP
ve
LINE/MIC_AP
LINE/MIC_AN
C12
2u2
n.
Ensure good low impedance ground return path through GND plane for SMPSU
AU_REF
-e
VSS_SMPS_1V35
STAR
MIC BIAS
67
VDD_DIG to Ground
SP100
zh
o
69
51
C7 to VSS_SMPS_1V35
46
GND PADDLE
C4 to VSS_SMPS_1V8
VSS_SMPS_1V8
L1 to C4 track
L2 to C7 track
xc
el
LX_1V8 to Inductor
LX_1V35 to Inductor
XT1
rid
IN
LINE/MIC_AN
Bluetooth RF
50R
i
BT_RF
PIO[29] / LED[0]
PIO[30] / LED[1]
PIO[31] / LED[2]
DIG LDO
1V35
50R
U2
i
2
A NT
OUT
XTAL_IN
XTAL_OUT
ep
CHARGER
LINE/MIC_PIO
C19
2u2
VDD_ANA
52
50
LX_1V35
14
VDD_AUDIO
VDD_AUX
53
47
LX_1V8
54
41
49
VDD_USB
SMP_BYP
VOUT_3V3
48
45
VBAT
SMP_VBAT
43
44
LINE/MIC_AN
C16 MIC_P
100n
VDD_BT_RADIO
C15 MIC_N
100n
SMPS_1V35_SENSE
R2
2k2
GND
C17
15p
VDD_AUDIO_DRV
15nH
15
VDD_AUX_1V8
16
VDD_AUX_1V8
L4
C11
100n
63
L2
4u7
C6
10n
33
C5
10n
VDD_PADS_2
C4
2u2
VDD_PADS_1
L1
4u7
1V8_SMPS
38
C3
2u2
SMPS_1V8_SENSE
Mic1
V+
U1
CHG_EXT
LINE_BN
C18
2u2
VBAT_SENSE
LINE_BP
1V8
STX-3100-9N
VCHG
2
R
1
SHIELD
40
C13 LINE_L
2u2
C14
2u2
C2
2u2
1V35_SMPS
JACK_DET_PIO
42
9
10
11
VREGENABLE
UNMATED
MATED
C1
2u2
1V8_SMPS
VDD_DIG
S1
MFB
3V3_USB
te
m
be
r2
7,
20
13
CHG_EXT
Line Jack
CON1
UNMATED
MATED
VBAT
VBAT_SENSE
VBAT VBUS
CSR recommend low Rdc inductors (<0.5R) for L1 & L2 for optimum power efficiency
Left
Right
Speakers (16-32 Ohm)
in
gb
RED
R101
220R
R102
330R
1V8
1V8
1V8
D103
S100
F4
S101
F3
S102
F2
S103
VOL+
S104
VOL-
R103
330R
10n
U101
8
VCC
A0
7
WP
A1
6
SCL
A2
5
SDA VSS
24AAxxx
1
2
3
4
PIO_n
Q1
D102
1V8
C100
U100
8
PIO_11
PIO_13
1V8_SMPS
VDD
5
1
SI/SIO0
CE
2
6
SO/SIO1 SCK
3
WP/SIO2
7
HOLD/SIO3
4
VSS
SPI Flash
PIO_12
PIO_10
G-TW-0012957.3.3
D101
GREEN
CON101
3.7V
C102
10n
BLUE
1V8
VBAT
PIO_n
ep
1V8_SMPS
BAT54C
THERM
10k
PIO_n
PIO_n
R108
220mR
VBUS
9k1
PIO_n
1%
400mR
VBAT
R100
LED_0
R104
VBAT
Li+ CELL
AIO_0
LED_1
VBAT_SENSE
USB_N
USB_P
LED_2
C105
4u7
VBUS
GND
BCX51
GND
1
2
CHG_EXT
Q100
CON100
USB MINI-B
1
VBUS
2
D3
D+
4
ID
5
GND
VBUS
Pr
ar
PIO_n
ed
fo
rq
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Cambridge Silicon Radio Limited 2013
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1V35 SMPS
AUX LDO
ANA LDO
1V35
12
BT_RF
2.45GHz
33
63
VDD_PADS_2
VDD_PADS_1
VDD_DIG
rid
SPI_PCM#
om
.c
C2 and C3
Ensure the following tracks have good low impedance connections
(no via share and short thick tracks)
po
6
SPKR_RN
7
SPKR_RP
C16
2u2
SPKR_RN
SPKR_RP
C15
2u2
9
SPKR_LN
10
SPKR_LP
LINE_BN
4
LINE_2N
5
LINE_2P
2
C14
2u2
SPKR_LN
SPKR_LP
C13
2u2
LINE_BP
MIC_BIAS
LINE/MIC_AP
LINE_1P 68
AU_REF
u
zh
o
C12
2u2
RST#
35
PIO / UART
AIO_0
USB_P
USB_N
USB (12Mbps)
RSTB
Reset
n.
LINE/MIC_AN
xc
el
VSS_SMPS_1V35
STAR
Ensure good low impedance ground return path through GND plane for SMPSU
20
SPI_PCM#
PIO_14
PIO_15
PIO_16
PIO_17
56
USB_P
55
USB_N
PIO / UART
PIO_2
PIO_3
PIO_4
PIO_5
23
PIO[14] / UART_RX
21
PIO[15] / UART_TX
27
PIO[16] / UART_RTS#
32
PIO[17] / UART_CTS#
AIO[0]
LINE_1N 67
VDD_DIG to Ground
SP100
-e
69
51
VSS_SMPS_1V8
C7 to VSS_SMPS_1V35
46
GND PADDLE
C4 to VSS_SMPS_1V8
29
LED outputs
PIO_0
PIO_1
PIO_6
PIO_7
PIO_8
PIO_9
PIO_18
PIO_21
PIO_12
PIO_10
PIO_11
PIO_13
in
LX_1V8 to Inductor
LX_1V35 to Inductor
59
60
62
57
61
58
65
64
LED_0
LED_1
LED_2
22
PIO[12] / QSPI_FLASH_CS# / I2C_WP
25
PIO[10] / QSPI_FLASH_CLK / I2C_SCL
26
PIO[11] / QSPI_IO[0] / I2C_SDA
31
PIO[13] / QSPI_IO[1]
t.c
18
30
PIO[2] / PCM1_IN / SPI_MOSI
28
PIO[3] / PCM1_OUT / SPI_MISO
24
PIO[4] / PCM1_SYNC / SPI_CS#
34
PIO[5] / PCM1_CLK / SPI_CLK
-F
L1 to C4 track
L2 to C7 track
XTAL_IN
19
CSR8635 QFN
ay
GND GND
26MHz
PIO[0] / UART_RX
PIO[1] / UART_TX
PIO[6]
PIO[7]
PIO[8] / UART_RTS#
PIO[9] / UART_CTS#
PIO[18]
PIO[21]
,S
Bluetooth RF
3
XT1
37
PIO[29] / LED[0]
36
PIO[30] / LED[1]
66
PIO[31] / LED[2]
DIG LDO
ep
IN
50R
i
BT_RF
C11
100n
XTAL_OUT
1V35
1V35
50R
U2
i
A NT
2
OUT
38
39
11
1V8 SMPS
3V3
C10
470n
VREGIN_DIG
17
13
C9
2u2
VDD_BT_LO
LX_1V35
VDD_AUX
C8
15p
52
SMPS_1V35_SENSE
50
14
C7
4u7
VDD_BT_RADIO
L2
4u7
C6
10n
VDD_AUDIO
LX_1V8
53
SMPS_1V8_SENSE
15
VDD_AUX_1V8
16
VDD_AUX_1V8
C5
10n
1V8_SMPS
te
m
be
r2
7,
20
13
BYPASS REG
C4
2u2
47
49
54
VBAT
CHARGER
L1
4u7
VDD_USB
SMP_BYP
48
41
C3
2u2
VOUT_3V3
VBAT
45
C2
2u2
1V35_SMPS
VDD_ANA
1V8_SMPS
VDD_AUDIO_DRV
3V3_USB
SMP_VBAT
43
CHG_EXT
42
VCHG
VREGENABLE
40
C1
2u2
44
S1
MFB
VBAT_SENSE
CHG_EXT
VBAT
VBAT_SENSE
VBAT VBUS
Ensure routing from L2 to pin 39 and from L2 to C8/9 & pins 11 & 13 are kept separate
ve
CSR recommend low Rdc inductors (<0.5R) for L1 & L2 for optimum power efficiency
Line Inputs
ke
Left
Right
Speakers (16-32 Ohm)
gb
R101
220R
GREEN
D102
R102
330R
1V8
1V8
D103
S100
F4
S101
F3
S102
F2
S103
VOL+
S104
VOL-
R103
330R
10n
U101
8
VCC
A0
7
WP
A1
6
SCL
A2
5
SDA VSS
PIO_n
1
2
3
4
24AAxxx
PIO_n
Q1
D101
1V8
C100
U100
8
PIO_11
PIO_13
1V8_SMPS
VDD
5
1
SI/SIO0
CE
2
6
SO/SIO1 SCK
3
WP/SIO2
7
HOLD/SIO3
4
VSS
SPI Flash
PIO_12
PIO_10
G-TW-0012977.2.3
RED
ar
ep
CON101
3.7V
1V8
PIO_n
R108
220mR
1V8
C102
10n
PIO_n
1%
400mR
1V8_SMPS
BAT54C
THERM
10k
PIO_n
VBAT
Li+ CELL
VBUS
9k1
PIO_n
R104
VBAT
VBAT
R100
LED_0
VBAT_SENSE
AIO_0
LED_1
C105
4u7
USB_N
USB_P
BLUE
BCX51
VBUS
GND
Q100
GND
1
2
CHG_EXT
CON100
USB MINI-B
1
VBUS
2
D3
D+
4
ID
5
GND
VBUS
Pr
ed
LED_2
fo
rq
in
Production Information
Cambridge Silicon Radio Limited 2013
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13 Electrical Characteristics
13.1
Rating
Min
Max
Unit
Storage temperature
-40
105
Supply Voltage
VCHG
-0.4
5.75 / 6.50(a)
LEDs
LED[2:0]
-0.4
4.40
VBAT_SENSE
-0.4
4.40
VREGENABLE
-0.4
4.40
VDD_AUDIO_DRV
-0.4
1.95
VDD_AUX_1V8
-0.4
1.95
VDD_PADS_1
-0.4
3.60
-0.4
3.60
-0.4
1.45
-0.4
1.45
-0.4
1.95
VSS - 0.4
VDD + 0.4
VDD_AUDIO
xc
el
1.35V
po
20
7,
r2
be
in
t.c
SMPS_1V35_SENSE
m
te
ep
ay
,S
rid
-F
om
.c
VDD_PADS_2
ou
-e
VREGIN_DIG
Standard maximum input voltage is 5.75V, a 6.50V maximum requires a correct patch bundle, for more information contact CSR
Pr
ep
ar
ed
fo
rq
in
gb
ke
(a)
ve
n.
zh
Production Information
Cambridge Silicon Radio Limited 2013
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1.8V
Battery
13
Charger
13.2
Rating
Min
Typ
Max
Unit
-40
20
85
4.75 / 3.10(a)
5.00
5.75 / 6.50(b)
1.10
3.70
4.30
VBAT_SENSE
3.70
4.25
VREGENABLE
3.70
4.25
VDD_AUDIO_DRV
1.70
1.80
1.95
VDD_AUX_1V8
1.70
1.80
VDD_PADS_1
1.70
1.80
VDD_PADS_2
1.70
1.80
SMPS_1V35_SENSE
1.30
VDD_AUDIO
1.30
VREGIN_DIG
1.30
VCHG
LEDs
LED[2:0]
be
3.60
3.60
1.35
1.45
1.35
1.45
1.35 or 1.80(c)
1.95
-F
rid
ay
,S
ep
te
om
t.c
in
po
xc
el
1.35V
Minimum input voltage of 4.75 V is required for full specification, regulator operates at reduced load current from 3.1 V
(b)
Standard maximum input voltage is 5.75 V, a 6.50 V maximum requires a correct patch bundle, for more information contact CSR
(c)
Typical value depends on output required by the low-voltage VDD_DIG linear regulator, see Section 13.3.2.2
Pr
ep
ar
ed
fo
rq
in
gb
ke
ve
n.
zh
ou
-e
(a)
Production Information
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1.95
.c
1.8V
r2
7,
Battery
20
Charger
13
Supply Voltage
13.3
Note:
Current drawn into a pin is defined as positive; current supplied out of a pin is defined as negative.
Typ
Max
Unit
Input voltage
2.80
3.70
4.25
Output voltage
1.70
1.80
1.90
30
Load current
7,
20
13
be
r2
Normal Operation
185
mA
25
mA
90
3.63
4.00
4.00
MHz
250
mA
0.1
0.3
0.8
200
0.005
mA
mA
85
100
200
kHz
om
.c
-F
rid
ay
,S
ep
te
t.c
Switching frequency
xc
el
po
in
-e
Inductor ESR
zh
ou
ve
n.
ar
ed
fo
rq
in
gb
ke
Load current
Pr
ep
Switching frequency
(a)
(b)
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Min
Typ
Max
Unit
Input voltage
2.80
3.60
4.25
Output voltage
1.70
1.80
1.90
30
Load current
340
mA
25
90
Switching frequency
3.63
4.00
400
ep
Inductor ESR
0.1
7,
20
13
Normal Operation
mA
4.00
MHz
mA
0.3
0.8
200
0.005
mA
mA
85
100
200
kHz
-F
rid
ay
,S
te
be
r2
.c
t.c
om
po
in
Load current
-e
xc
el
zh
ou
ve
n.
Switching frequency
(b)
Pr
ep
ar
ed
fo
rq
in
gb
ke
(a)
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Min
Typ
Max
Unit
4.25 / 3.10(a)
5.00
5.75 / 6.50(b)
3.00
3.30
3.60
250
mA
Input voltage
(a)
Minimum input voltage of 4.25V is required for full specification, regulator operates at reduced load current from 3.1V
(b)
Standard maximum input voltage is 5.75V, a 6.50V maximum requires a correct patch bundle, for more information contact CSR
20
13
Max
Unit
Input voltage
2.80
3.60
4.25
Output voltage
1.30
1.35
1.40
30
160
mA
mA
88
3.63
4.00
4.00
MHz
220
mA
Inductor ESR
0.1
0.3
0.8
200
0.005
mA
mA
85
100
200
kHz
Typ
rid
ay
,S
ep
te
Min
.c
-F
Normal Operation
t.c
om
po
in
Load current
xc
el
ou
-e
in
gb
ke
ve
n.
zh
Switching frequency
fo
rq
Pr
ep
Load current
ar
ed
Switching frequency
(a)
Production Information
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be
r2
7,
Normal Operation
Min
Typ
Max
Unit
Input voltage
1.30
1.35 or 1.80
1.95
Output voltage(a)
0.80
0.90 / 1.20
1.25
80
mA
Normal Operation
Min
Typ
20
Input voltage
1.70
1.80
Output voltage
1.30
1.35
13
r2
7,
Max
1.45
mA
Min
Typ
Max
Unit
1.70
1.80
1.95
1.30
1.35
1.45
60
mA
Min
Typ
Max
Unit
1.0
Min
Typ
Max
Unit
4.75 / 3.10(a)
5.00
5.75 / 6.50(b)
-F
rid
te
ep
ay
,S
be
om
.c
Normal Operation
po
in
t.c
Input voltage
xc
el
Output voltage
ou
-e
Load current
n.
ve
ke
gb
zh
rq
in
Rising threshold
Pr
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(b)
Standard maximum input voltage is 5.75V, a 6.50V maximum requires a correct patch bundle, for more information contact CSR.
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1.95
Typ
Max
Unit
10
12
2.9
0.1
2.8
Min
Typ
Max
Unit
194
200
206
10
50
20
r2
mA
7,
13
Min
ep
mA
100
10
mA
4.20
4.24
10
20
Min
Typ
Max
Unit
100
150
mV
Min
Typ
Max
Unit
50
mV
Min
Typ
Max
Unit
200
500
mA
20
mA
Voltage on CHG_EXT
5.75 / 6.50(b)
50
195
200
205
mV
4.16
rid
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.c
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t.c
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Standby Mode
zh
ou
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in
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(a)
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Pr
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In the external mode, the battery charger meets all the previous charger electrical characteristics and the additional or superseded electrical
characteristics are listed in this table.
(b)
Standard maximum input voltage is 5.75V, a 6.50V maximum requires a correct patch bundle, for more information contact CSR.
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ay
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13.3.5 USB
Min
Typ
Max
Unit
3.1
3.3
3.6
0.3 x
VDD_USB
0.7 x
VDD_USB
2.8
13
7,
20
VDD_USB
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r2
0.2
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Conditions
Min
Typ
Max
Unit
16
Bits
48
kHz
0dB = 1600mVpk-pk
13
2260
mVpk-pk
8kHz
94.4
16kHz
92.4
32kHz
44.1kHz
48kHz
13
Resolution
-e
48kHz
Analogue gain
dB
93.2
dB
91.9
dB
0.004
0.016
-24
21.5
dB
-3
42
dB
-89.9
dB
in
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-F
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ou
Digital gain
7,
92.5
r2
dB
t.c
xc
el
8kHz
in
B/W = 20HzFsample/2
(20kHz max)
1.6Vpk-pk input
THD+N
om
Fsample
fin = 1kHz
po
SNR
dB
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B/W = 20HzFsample/2
(20kHz max)
A-Weighted
THD+N < 0.1%
1.6Vpk-pk input
.c
fin = 1kHz
20
Fsample
Conditions
Resolution
Output Sample
Rate, Fsample
Typ
Max
Unit
16
Bits
96
kHz
dB
100k
95.4
48kHz
32
96.5
48kHz
16
95.8
Fsample
Load
8kHz
100k
8kHz
32
8kHz
16
48kHz
100k
48kHz
20
48kHz
dB
dB
0.0021
0.0031
0.0034
0.0037
32
0.0029
16
0.0042
-24
21.5
dB
-21
dB
778
mV rms
-90.5
dB
r2
7,
be
B/W = 20Hz20kHz
A-Weighted
THD+N < 0.1%
0dBFS input
Load
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n
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t.c
B/W = 20Hz20kHz
0dBFS input
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48kHz
xc
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in
THD+N
Analogue Gain
Output voltage
rq
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Digital Gain
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fin = 1kHz
te
SNR
Fsample
po
fin = 1kHz
13
Min
Min
Typ
Max
Unit
-0.4
0.4
0.7 x VDD
VDD + 0.4
25
ns
20
13.3.8 Digital
Digital Terminals
0.75 X VDD
Input Voltage
Tr/Tf
13
Output Voltage
0.4
ns
-40
-10
40
150
-5
-1.0
-0.33
0.33
1.0
5.0
1.0
5.0
pF
ve
Min
Typ
Max
Unit
gb
10
mA
IPAD = 10mA
0.55
40
0.8
0.8
m
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Tr/Tf
be
Strong pull-up
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10
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Strong pull-down
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-150
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t.c
Weak pull-up
xc
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po
Weak pull-down
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CI Input Capacitance
n.
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Current, IPAD
(a)
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Pr
ep
r2
7,
Max
Unit
Resolution
10
Bits
VDD_AUX
INL
-1
LSB
DNL
LSB
-1
LSB
-0.8
0.8
Input bandwidth
100
Conversion time
1.38
1.69
ay
,S
20
7,
r2
(b)
The auxiliary ADC is accessed through a VM function. The sample rate given is achieved as part of this function.
kHz
2.75
700
Samples/s
-F
rid
(a)
t.c
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.c
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in
Auxiliary DAC
-e
xc
el
Resolution
zh
ou
ve
n.
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Typ
Max
Unit
10
Bits
1.30
1.35
1.40
VDD_AUX
1.30
1.35
1.40
1.32
2.64
mV
-1.32
1.32
mV
-1
LSB
250
ns
rq
in
gb
LSB size
Min
ar
ed
fo
Offset
Pr
ep
Integral non-linearity
Settling time(a)
(a)
Important Note:
Access to the auxiliary DAC is firmware-dependent, for more information about its availability contact CSR.
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Sample rate(b)
be
Gain error
Offset
te
Accuracy
(Guaranteed monotonic)
13
Min
ep
Auxiliary ADC
13.4
ESD Protection
Class
Max Rating
III
20
13
7,
be
r2
te
CSR8635 QFN has integrated ESD protection on the USB_DP and USB_DN pins as detailed in IEC 6100042.
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-F
CSR can demonstrate normal performance up to level 2 (4kV contact discharge / 4kV air discharge) as per IEC 6100-4-2
classification 1. Above level 2, temporary degradation is seen (classification 2).
xc
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po
in
t.c
om
CSR8635 QFN contains a reset protection circuit and software, which will attempt to re-make any connections lost in
a ESD event. If the device at the far end permits this, self-recovery of the Bluetooth link is possible if CSR8635 QFN
resets on an ESD strike. This classes CSR8635 QFN as IEC 6100042 classification 2 to level 4 (8kV contact
discharge / 15kV air discharge). If self-recovery is not implemented, CSR8635 QFN is IEC 6100042 classification 3
to level 4.
ou
-e
Note:
zh
Any test detailed in the IEC-61000-4-2 level 4 test specification does not damage CSR8635 QFN.
ve
n.
The CSR8635 QFN USB VBUS pin is protected to level 4 using an external 2.2F decoupling capacitor on VCHG.
ke
Important Note:
in
gb
CSR recommends correct PCB routing and to route the VBUS track through a decoupling capacitor pad.
fo
rq
When the USB connector is a long way from CSR8635 QFN, place an extra 1F or 2.2F capacitor near the USB
connector.
Pr
ep
ar
ed
No components (including 22 series resistors) are required between CSR8635 QFN and the USB_DP and
USB_DN lines.
To recover from an unintended reset, e.g. a large ESD strike, the watchdog and reset protection feature can restart
CSR8635 QFN and signal the unintended reset to the VM.
Table 13.2 summarises the level of protection.
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CSR has tested CSR8635 QFN assembled in development kits to assess the Electrostatic Discharge Immunity. The
tests were based on IEC 6100042 requirements. Tests were performed up to level 4 (8kV contact discharge / 15kV
air discharge).
IEC 6100042
Classification
Comments
Class 1
Class 1
Class 2 or class 3
Class 2 or class 3
Pr
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r2
7,
20
13
IEC 6100042
Level
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Unit
30
11.0
mA
EV3
30
11.8
mA
3EV3
60
9.2
mA
1-mic CVC:
8kHz sampling
Narrowband
HV3
30
12.6
eSCO
1-mic CVC:
8kHz sampling
Narrowband
2EV3
60
Slave
eSCO
1-mic CVC:
16kHz sampling
Wideband
2EV3
60
Slave
eSCO
1-mic CVC:
16kHz sampling
FESI
2EV3
Slave
SCO
8kHz sampling
Narrowband
Slave
eSCO
8kHz sampling
Narrowband
Slave
eSCO
Slave
Connection
Packet Type
Packet Size
Slave
SCO
HV3
Slave
eSCO
Slave
eSCO
Slave
SCO
Slave
mA
11.4
mA
60
10.9
mA
HV3
30
12.2
mA
2EV3
60
10.4
mA
16kHz sampling
Wideband
2EV3
60
11.2
mA
16kHz sampling
FESI
2EV3
60
10.7
mA
13.3
mA
ar
ed
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t.c
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-F
ay
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te
mA
Slave
eSCO
48kHz sampling
No sniff
White noise
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10.8
rid
be
r2
7,
20
DUT Role
13
Average
Current
Pr
ep
14 Power Consumption
11.8
mA
213
142
SCO
HV3
30
10.8
mA
Master
eSCO
EV3
30
11.2
mA
Master
eSCO
3EV3
60
8.8
mA
Master
SCO
1-mic CVC:
8kHz sampling
Narrowband
HV3
30
rid
12.5
mA
Master
eSCO
1-mic CVC:
8kHz sampling
Narrowband
2EV3
t.c
60
10.5
mA
Master
eSCO
1-mic CVC:
16kHz sampling
Wideband
2EV3
60
11.0
mA
Master
eSCO
1-mic CVC:
16kHz sampling
FESI
2EV3
60
10.6
mA
Master
SCO
8kHz sampling
Narrowband
HV3
30
12.1
mA
Master
Pr
ep
8kHz sampling
Narrowband
2EV3
60
10.1
mA
Packet Size
Slave
48kHz sampling
No sniff
White noise
Slave
ACL
Sniff = 500ms
Slave
ACL
Sniff = 1280ms
Master
ar
ed
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te
be
r2
7,
20
Packet Type
13
Unit
Connection
eSCO
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Average
Current
DUT Role
Average
Current
Unit
60
10.8
mA
2EV3
60
10.2
mA
Master
48kHz sampling
No sniff
White noise
13.2
Master
48kHz sampling
No sniff
White noise
Master
ACL
Sniff = 500ms
Master
ACL
Sniff = 1280ms
13
16kHz sampling
FESI
20
eSCO
2EV3
7,
Master
16kHz sampling
Wideband
mA
r2
eSCO
Packet Size
be
Master
Packet Type
Connection
ay
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mA
197
142
-e
xc
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t.c
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-F
10.9
ou
Note:
Pr
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LEDs disconnected
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ep
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DUT Role
13
ay
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CSR has defined the "CSR Green" standard based on current regulatory and customer requirements including free
from bromine, chlorine and antimony trioxide.
in
t.c
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Products and shipment packaging are marked and labelled with applicable environmental marking symbols in
accordance with relevant regulatory requirements.
Pr
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This identifies the main environmental compliance regulatory restrictions CSR specify. For more information on the full
"CSR Green" standard, contact product.compliance@csr.com.
Including applicable amendments to EU law which are published in the EU Official Journal, or SVHC
Candidate List updates published by the European Chemicals Agency (ECHA).
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ep
te
20
7,
Restrictions on the manufacture, placing on the market and use of certain dangerous substances,
preparations and articles (Annex XVII). This Annex now includes requirements that were contained within
EU Directive, 76/769/EEC. There are many substance restrictions within this Annex, including, but not
limited to, the control of use of Perfluorooctane sulfonates (PFOS).
When requested by customers, notification of substances identified on the Candidate List as Substances
of Very High Concern (SVHC)1.
POP regulation (EC) No 850/20041
EU Packaging and Packaging Waste, Directive 94/62/EC1
Montreal Protocol on substances that deplete the ozone layer.
Conflict minerals, Section 1502, Dodd-Frank Wall Street Reform and Consumer Protection act, which affects
columbite-tantalite (coltan / tantalum), cassiterite (tin), gold, wolframite (tungsten) or their derivatives. CSR is
a fabless semiconductor company: all manufacturing is performed by key suppliers. CSR have mandated that
the suppliers shall not use materials that are sourced from "conflict zone mines" but understand that this
requires accurate data from the EICC programme. CSR shall provide a complete EICC / GeSI template upon
request.
r2
be
16 Software
CSR8635 QFN:
Includes integrated CSR8635 Stereo ROM Solution, with 6th generation 1-mic CVC audio enhancements and
a configurable EQ
Can be shipped with CSRs CSR8635 stereo ROM solution development kit for CSR8635 QFN, order code
DK8635101631A
The CSR8635 QFN software architecture enables Bluetooth processing and the application program to run on the
internal RISC MCU, and the audio enhancements on the Kalimba DSP.
13
16.1
7,
r2
be
te
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.c
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Pr
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xc
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po
in
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Button events: configuring button presses and durations for certain events, e.g. double press on PIO[1]
for last number redial
LED indications for states, e.g. device connected, and events, e.g. power on
Battery divider ratios and thresholds, e.g. thresholds for battery low indication, full battery etc.
t.c
20
r2
7,
20
13
Advanced Multipoint enables the connection of 2 devices to a CSR8635 QFN device at the same time, examples
include:
During multiple calls (1 on each device), as if there is a single AG with multiple calls in progress (threeway calling)
During multiple calls (more than 1 on each device), as if there are multiple calls on a single device enabling
the user to switch between the active and held calls
be
ay
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.c
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t.c
in
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xc
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ou
-e
n.
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CSR8635 QFN supports a wired audio mode for playing music over a wired connection.
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in
gb
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ve
If CSR8635 QFN is powered, the audio path is routed through CSR8635 QFN, including via the DSP, this enables the
CSR8635 QFN to:
Control the volume of the audio, i.e. volume up and volume down
Pr
ep
ar
ed
fo
In wired audio mode, if required, the CSR8635 QFN is still available for Bluetooth audio. This enables seamless
transition from wired audio mode to Bluetooth audio mode and back again. This transition is configurable to occur
automatically as the battery voltage of the device reduces to a point at which Bluetooth audio is no longer possible.
The carrier board features a stereo line-in with detect.
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ep
te
A2DP Multipoint support enables the connection of 2 A2DP source devices to CSR8635 QFN at the same time,
examples include:
Music streaming from either of the connected A2DP source devices where the music player is controlled on
the source device
Advanced HFP Multipoint functions to interrupt music streaming for calls, and resume music streaming on the
completion of the calls
AVRCP v1.4 connections to both connected devices, enabling the device to remotely control the primary
device, i.e. the device currently streaming audio
The USB audio mode operates at the same time as the wired audio mode and the USB audio interrupts the wired audio
mode if USB audio is attached. This enables a device to have both wired audio and USB modes connected at the same
time.
In USB audio mode, if required, the device is still available for Bluetooth audio.
be
r2
7,
20
13
CSR8635 QFN enables a user to configure and load pre-programmed audio prompts from:
An external EEPROM, in this implementation the prompts are stored in the same EEPROM as the PS Keys,
see Figure 16.2. A larger EEPROM is necessary for programmable audio prompts. This implementation
supports EEPROMs up to 512Kb. An EEPROM of 512Kb enables approximately 15 seconds of audio storage.
An external SPI flash, in this implementation the prompts are stored in the same SPI flash as the PS Keys,
see Figure 16.1.
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-F
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Programmable audio prompts contain either voice prompts to indicate that events have occurred or provide user-defined
higher quality ring tones/indications, e.g. custom power on/off tones.
om
.c
The Headset Configuration Tool can generate the content for the programmable audio prompts from standard WAV
audio files. The tool also enables the user to configure which prompts are assigned to which user events.
PS Keys
Configuration
Patches
SPI
Programmable
Audio Prompts
Pr
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CSR8635
SPI Flash
G-TW-0012961.1.1
n.
zh
ou
-e
xc
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po
in
t.c
Section 6.5 describes the SPI flash interface and Section 7.4 describes the IC interface to an external EEPROM.
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ep
te
The programmable audio prompts provide a mechanism for higher-quality audio indications to replace standard tone
indications. A programmable audio prompt is assigned to any user event in place of a standard tone.
EEPROM
PS Keys
Configuration
Patches
I2C
G-TW-0012962.1.1
CSR8635
13
Programmable
Audio Prompts
r2
7,
Note:
20
te
be
When using the SPI flash interface for programmable audio prompts, an EEPROM device is not required in the
CSR8635 stereo ROM solution.
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ay
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-F
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IPM extends the available talk time of a CSR8635 QFN-based device, by automatically reducing the audio processing
performed by CVC at a series of low battery capacity thresholds.
in
t.c
om
.c
IPM enable/disable
xc
el
po
If engaged, CVC processing reduces automatically on reaching the preset battery capacity. Once the audio is
terminated, the DSP shuts down to achieve maximum power savings before the next call.
ke
o
gb
ve
n.
zh
ou
-e
IPM resets when recharging the device. The talk time extension depends on:
fo
rq
in
Proximity pairing is device-initiated pairing and it simplifies the out-of-box pairing process. Proximity pairing enables
the device to find the closest discoverable phone. The device then initiates the pairing activity and the user simply has
to accept the incoming pairing invitation on the phone.
ar
ed
This means that the phone-user does not have to hunt through phone menus to pair with the new device.
Pr
ep
For a Bluetooth v2.0 phone the device pairing is with a PIN code
For a Bluetooth v2.1 (or above) phone the device pairing is without a PIN code
Proximity pairing is based on finding and pairing with the closest phone. To do this, the device finds the loudest phone
by carrying out RSSI power threshold measurements. The loudest phone is the one with the largest RSSI power
threshold measurement, and it is defined as the closest device. The device then attempts to pair with and connect to
this device.
Proximity pairing is configurable using the Headset Configuration Tool available from www.csrsupport.com.
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Proximity connection speeds up the device connection process. It requires the device to initiate a SLC connection to
the nearest device first and combines this with the device's storage of the last 8 paired/connected devices. Using
proximity connection means functions operate equally well for the most or least recently paired or connected device.
16.2
6th Generation 1-mic CVC ENR Technology for Hands-free and Audio
Enhancements
1-mic CVC full-duplex voice processing software is a fully integrated and highly optimised set of DSP algorithms
developed to ensure easy design and build of hands-free products.
20
7,
r2
be
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t.c
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1-mic CVC includes a tuning tool enabling the developer to easily adapt CVC with different audio configurations and
tuning parameters. The tool provides real-time system statistics with immediate feedback enabling designers to quickly
investigate the effect of changes.
Acoustic Echo
Canceller
Noise
Suppression
Nonlinear
Processing
Howling
Control
Comfort Noise
Send Equaliser
Send AGC
Receive
Equaliser
Adaptive
Equaliser
Noise
Suppression
Packet Loss
Concealment
Send
Out
ou
Mic
Gain
-e
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Figure 16.3 shows the functional block diagram of CSRs proprietary 1-mic CVC DSP solution for a hands-free product.
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Receive Out
Pr
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Speaker Gain
Clipper
Receive AGC
Receive
In
G-TW-0010188.1.1
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Auxiliary
Stream Mix
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Bluetooth Radio
NDVC
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Send In
Section 16.2.1 to Section 16.2.13 describe the audio processing functions provided within CVC.
A referenced sub-band adaptive linear filter that models the acoustic path from the receive reference point to
the microphone input
A non-linear processing function that applies narrowband and wideband attenuation adaptively as a result of
residual echo present after the linear filter.
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Full-duplex AEC
13
CVC enables greater acoustic design flexibility for a wide variety of environments and configurations as a result of
sophisticated noise and echo suppression technology. CVC reduces the affects of noise on both sides of the
conversation and smartly adjusts the receive volume levels and dynamically frequency shapes the voice to achieve
optimal intelligibility and comfort for the hands-free user.
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The non-linear processing module detects the presence of echo after the primary sub-band linear filter and adaptively
applies attenuation at frequencies where echo is identified. It is used to minimise echo due to non-linearity caused by
the system, i.e. the loudspeaker and microphone, amplifiers, electronics etc. CSR recommends minimal use of nonlinear processing due to the inherent distortion that it introduces.
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The Howling Control is a programmable coupling threshold that when triggered applies attenuation to the send path.
This control enables CVC to operate in car-to-car calls without experiencing echo events during very high volume
situations.
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The CNG:
Creates a spectrally and temporally consistent noise floor for the far-end listener.
Adaptively inserts noise modelled from the noise present at the microphone into gaps introduced when the
non-linear processing of the AEC applies attenuation. The noise level applied is user-controllable.
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16.2.6 Equalisation
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Compensate for the frequency response of transducers in the system, i.e. the microphone and loud speaker
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Normalise the amplitude of the incoming audio signal to a desired range to increase perceived loudness
Reduce amplitude variance observed from different users, phones and networks
Maintaining a consistent long-term loudness for the speech ensures it is more easily heard by the listener and it also
provides the subsequent processing block a larger amplitude signal to process. The behaviour of the AGC differs from
a dynamic range audio compressor. The convergence time for the AGC is much slower to reduce the non-linear
distortion.
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The PLC tries to re-synthesise the lost packet from the history buffer with the same pitch period. The PLC uses a highly
efficient 3-phase pitch estimator and performs cross-fading at the concatenation boundaries, i.e. the PLC attempts to
clean up the audio signal by removing the pops and clicks and smoothing out gaps. This improves the audio quality for
the user and the improved signal enables proceding processing blocks to perform better.
The PLC significantly improves dealing with bit errors, using the BFI output from the firmware. The DSP calculates an
average BER and selectively applies the PLC to the incoming data. This optimises audio quality for a variety of bit errors
and packet loss conditions. The PLC is enabled in all modes.
Note:
The PLC is enabled in all modes, HFK (full processing), pass-through and loopback by default.
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The Frequency Emphasis feature can be used with any standard narrow band call, when the DAC is operating at a
sample rate of 8kHz. To complement the AEQ, High Frequency Emphasis can be added to improve the intelligibility of
the far end caller. The emphasis feature repairs frequencies (3469Hz to 4000Hz) that were lost due to the filters of the
cellular network and Bluetooth link. Information contained in the original speech from 281Hz to 3469Hz is used to
reconstruct the lost high frequency content.
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The Frequency Expansion feature can be used with any standard narrow band call, but a special mode is invoked when
the DAC operate at a sample rate of 16kHz. The frequency expansion allows users to add in frequencies far beyond
the band limits caused by the cellular network and Bluetooth link. These expansion frequencies are added between
3469Hz and 6156Hz. As in frequency emphasis, it uses the information contained in the original speech from 281Hz
to 3469Hz to reconstruct the lost high frequency content.
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The auxiliary stream mixer enables the system to seamlessly mix audio signals such as tones, beeps and voice prompts
with the incoming SCO stream. This avoids any interruption to the SCO stream and as a result prevents any speech
from being lost.
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The clipper block intentionally distorts or clips the receive signal prior to the reference input of the AEC in order to more
accurately model the behaviour of the post reference input blocks such as the DAC, power amplifier and the
loudspeaker. The AEC attempts to correlate the signal received at the reference input and the microphone input. Any
non-linearities introduced that are not accounted for after the reference input will significantly degrade the AEC
performance. This processing block can significantly improve the echo performance in cheap non-linear system
designs.
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The adaptive equalisation block improves the intelligibility of the receive path voice signal in the presence of near end
noise by altering the spectral shape of the receive path signal while maintaining the overall power level. It has been
empirically observed that consonants, which are dominantly high frequency based and much lower in amplitude than
vowels, significantly contribute to the intelligibility of the voice signal. In the presence of noise, the lower amplitude
consonants become masked by this noise. Therefore, by increasing the frequency components that contribute to the
consonants while in the presence of noise, the intelligibility can be improved. In order to maintain a consistent amplitude
level, the adaptive equalization block will adaptively increase the high frequencies relative to the middle frequencies
and also reduce the low frequencies accordingly. The adaptive equalizer also has the capability to compensate for
variations in voice transmission channels, which include farend devices and telecommunication channels.
16.3
Music Enhancements
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SBC
MP3
AAC
Faststream codec:
Low-latency
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16.3.2 Configurable EQ
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Each EQ filter contains up to 5 fully tuneable stages of cascaded 2nd order IIR filters per bank
Enables compensation for imperfections in loudspeaker performance and frequency adjustments to the
received audio to enhance music brightness
Contains tiering for multiple customer presets, e.g. rock, pop, classical, jazz, dance etc.
Contains an easy to use GUI, with drag points, see Figure 16.4
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CSR's audio development kit for the CSR8635 QFN, order code DK8635101631A, includes a CSR8635 stereo ROM
solution demonstrator board and necessary interface adapters and cables are available. In conjunction with the
CSR8600 ROM Series Configuration Tool and other supporting utilities the development kit provides the best
environment for designing audio solutions with the CSR8635 QFN.
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Important Note:
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The CSR8635 Stereo ROM Solution audio development kit is subject to change and updates, for up-to-date
information see www.csrsupport.com.
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The volume boost feature on the CSR8635 QFN is a dynamic range compander and provides:
17.1
Tape Orientation
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G-TW-0002812.2.2
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Pin 1
17.2
Tape Dimensions
4.0
See Note 1
0.25
2.0
See Note 6
R0.25
1.75
0.30 0.05
R0.3 MAX
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7.5
See Note 6
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3.
4.
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6.
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Section A-A
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Reel Information
a(rim height)
ATTENTION
Electrostatic Sensitive Devices
Safe Handling Required
102.0
2.0
Detail "A"
13
17.3
88 REF
20.2
MIN
7,
20
330.0
2.0
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2.0 0.5
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Detail "B"
G-TW-0002797.5.2
16
W1
W2 Max
Units
4.5
98.0
16.4
(3.0/-0.2)
19.1
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QFN
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Package Type
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CSR8635 QFN is qualified to moisture sensitivity level MSL3 in accordance with JEDEC J-STD-020.
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"b" REF
13.0 +0.5
-0.2
18 Document References
Reference, Date
CS-209064-DD
CS-102736-UG
CS-101412-AN
CS-303738-SP
JESD22-A115C
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Document
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CS-112584-SP
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IEC 61000-4-2
Electromagnetic compatibility (EMC) Part 4-2: Testing
and measurement techniques Electrostatic discharge
immunity test
CS-204572-AN
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CS-202067-UG
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CS-116434-AN
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8DPSK
/4 DQPSK
-law
A-law
A2DP
AAC
AC
Alternating Current
ACL
Asynchronous Connection-oriented
ADC
AEC
AFC
AFH
AG
Audio Gateway
AGC
ALU
AVRCP
BCCMD
BlueCore CoMmanD
BCSP
BEC
BER
BFI
BlueCore
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Built-In Self-Test
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BIST
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Term
Bluetooth
Set of technologies providing audio and data transfer over short-range radio connections
BMC
CNG
codec
Coder decoder
CRC
CSR
CTS
Clear To Send
CVC
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Definition
CVSD
DAC
DC
Direct Current
DDS
DI
Device Id profile
DMA
DNL
DSP
DUT
e.g.
EDR
EEPROM
EIA
EMC
ElectroMagnetic Compatibility
EQ
EQualiser
eSCO
extended SCO
ESD
Electrostatic Discharge
ESR
etc
FIR
FSK
G.722
GCI
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GUI
GSM
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Term
H4DS
H4 Deep Sleep
HBM
HCI
HFP
Hands-Free Profile
HSP
HeadSet Profile
IC
IS
i.e.
Id est, that is
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Definition
I/O
Input/Output
IC
Integrated Circuit
IF
Intermediate Frequency
IIR
INL
IPC
See www.ipc.org
IPM
IQ
ISDN
JEDEC
Joint Electron Device Engineering Council (now the JEDEC Solid State Technology Association)
Kalimba
An open platform DSP co-processor, enabling support of enhanced audio applications, such as
echo and noise suppression and file compression / decompression
Kb
Kilobit
LC
LDO
LED
Light-Emitting Diode
LM
Link Manager
LNA
LSB
MAC
Mb
Megabit
MCU
MicroController Unit
MIPS
MISO
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MMU
MultiLayer Ceramic
Memory Management Unit
MP3
mSBC
N/A
Not Applicable
NDVC
NSMD
PA
Power Amplifier
PC
Personal Computer
PCB
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MLC
13
Term
Definition
PCM
PIN
PIO
Parallel Input/Output
PIO
PLC
plc
PS Key
PWM
QFN
Quad-Flat No-lead
RAM
RC
RF
Radio Frequency
RGB
RISC
RoHS
ROM
RSSI
RTS
Request To Send
RX
Receive or Receiver
SBC
Sub-Band Coding
SCL
SCMS
Serial Copy Management System (SCMS-T). A content protection scheme for secure transport
and use of compressed digital music
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SDA
Synchronous Connection-Oriented
Pr
ep
SCO
SIG
SLC
SMPS
SNR
Signal-to-Noise Ratio
SPI
TBD
To Be Defined
TCXO
THD+N
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Term
Definition
TX
Transmit or Transmitter
UART
UI
User Interface
USB
VCO
VM
Virtual Machine
VoIP
W-CDMA
Wi-Fi
WNR
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Term
Production Information
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