LABORATORY MANUAL

Electrical Devices
ENGG*3450
Fall semester 2015

Instructor:
Dr. Stefano Gregori

Laboratory 3
1

Purpose

The purpose of this laboratory is to study MOS field-effect transistors (MOSFETs). In

this laboratory we will examine the MOSFETs characteristics, regions of operation, biasing
conditions, and simple applications.

Equipment
Equipment
BK Precision 1672 DC Power Supply
BK Precision 1672 4017A 10 MHz Sweep Function Generator
Tektronix Mixed Signal Oscilloscope 2024B
Twin Industries TW-E41-102B Solderless Breadboard with Wire Kit
Amprobe 37XR-A True-rms Digital Multimeter

Components
Part
1 k resistor
100 k resistor
330 k resistor
4.7 k resistor
10 F capacitor
CD4007UB chip
Red LED
Green LED

4
4.1

Count
1
1
1
1
1

Count
2
1
1
1
1
1
1
1

Pre-laboratory theory
MOSFETs structure and operation

The MOSFET is a four-terminal device with gate terminal (G), source terminal (S), drain terminal (D), and body terminal (B). MOSFETs are n-channel (NMOS) or p-channel (PMOS).
The physical structure of the NMOS is shown in Fig. 1.
The gate terminal controls the current flow from the drain to the source. The body
terminal in most cases is connected to the source terminal making the MOSFET a threeterminal device.
1

(a)

(b)

Figure 1: Structure of the NMOS transistor: (a) perspective view; (b) cross-section [1].

Figure 2: The iD -vDS characteristics of an NMOS transistor [1].

Figure 3: The iD -vGS characteristic of an NMOS [1].

2

To understand how a MOSFET works and its regions of operation, we will use an NMOS
transistor as an example. When the voltage applied to the gate is zero or low (vGS Vt ),
the path between the drain and source has a large resistance and the drain current (iD ) is
zero. This is the cutoff region (the transistor is off). When a positive voltage larger than a
given threshold is applied to the gate terminal (vGS > Vt ), electrons start to gather under
the gate forming a channel connecting the drain and the source. When we apply a voltage
across the drain and source terminals (vDS ), a current iD starts to flow through the channel.
The channel acts as a resistance controlled by the voltage vGS and the MOSFET is in triode
region (also called linear region). The drain current is given by


2
vDS
,
(1)
iD = kn (vGS Vt ) vDS
2
where vGS is the gate-to-source voltage, and kn = n Cox W
is the transistor transconductance
L
parameter. When vDS exceeds the overdrive vGS Vt , the channel is pinched-off, and the
current does not increase anymore with vDS . The MOSFET is in the saturation region, and
the drain current is given by
kn
(vGS Vt )2 .
(2)
iD =
2
Fig. 2 shows the iD -vDS characteristics of the MOSFET illustrating the cutoff, triode, and
saturation regions. Fig. 3 shows the iD -vGS characteristic of the MOSFET.

4.2

Common-source amplifier

When MOSFETs are used in the design of amplifiers, they have to be biased in saturation
region, where vGS Vt < vDS . In the common-source amplifier in Fig. 4, the input voltage
vI = VI + vi is applied between gate and source and it is the sum of two components:
a constat bias voltage VI ,
a small variable voltage vi (e.g. a sinusoidal waveform).
Likewise, the output voltage vO = VO + vo and the drain current iD = ID + id are the sum
of a constant bias component and small variable component.

Figure 4: Common-source amplifier.

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When VI Vt , the transistor is in cutoff region, ID = 0 A, and VO = VDD .

When VI is increased above Vt , the transistor turns on in saturation region,
ID =

kn
(VI Vt )2 ,
2

(3)

and

kn
(VI Vt )2 .
(4)
2
If VI is increased further, VO decreases, and eventually the transistor enters triode region
when

2 kn VDD + 1 1
.
(5)
VI > Vt +
kn R
Under this condition,


VO2
ID = kn (VI Vt ) VO
,
(6)
2
VO = VDD R ID = VDD R

and


VO = VDD R ID = VDD R kn

V2
(VI Vt ) VO O
2


.

(7)

We can calculate the gain of the amplifier with the transistor in saturation region by
taking the differential of (4)
!


kn
d
vi = R kn (VI Vt )vi = R gm vi ,
(8)
VDD R
(vI Vt )2
vo =
d vI
2
vI =VI
where gm = kn (VI Vt ) is the MOSFETs transconductance. The voltage gain is then
Av =

4.3

vo
= gm R.
vi

(9)

Inverters and latches

The inverter is one of the most important elements in digital circuit design. It inverts the
logic value of its input signal (i.e. if the input is a logic 0, the output is a logic 1, and vice
versa). Fig. 5(a) shows a CMOS inverter that consists of two transistors, NMOS and PMOS.
Considering the two extreme cases, when vI = 0 V (logic 0), the NMOS transistor is off and
the PMOS transistor is on. Thus, the output voltage vO = VDD (logic 1), because it is
connected to VDD . When vI = VDD , the NMOS transistor is on and the PMOS transistor is
off. Thus, the output voltage vO = 0 V (logic 0), because it is connected to ground.
The latch shown in Fig. 5(b) consists of two cross-coupled logic inverters. These inverters
form a positive feedback loop. For example, if the input applied to vI is a logic 1, it will be
and then inverted back again
inverted by the first inverter to give a value of a logic 0 at Q
by the second inverter to latch logic 1 at Q. If this input is removed, the output retains its
becomes
value. In the other case when you apply a logic 0 to vI , the opposite happens, Q
a logic 1 and then it gets inverted back again to give a logic 0 at Q. Again when the input
is removed, the latch retains its value of logic 0 at Q. The positive feedback loop allows the
storage of the state when the input is not applied, and this implements the memory function.

(a)

(b)

Figure 5: (a) CMOS inverter, (b) latch.

Experiments

You will examine the characteristics of the transistors in the CD4007UB chip. The CD4007UB
chip has three NMOS transistors and three PMOS transistors. Fig. 6 shows the top view of
the CD4007UB chip and Fig. 7 shows the functional diagram of the CD4007UB chip. In the
first two experiments, you will use one NMOS transistor. In the third experiment, you will
use all three NMOS transistors and all three PMOS transistors.

VSS

1
2
3
4
5
6
7

VDD
VDD

P1

P2

P3
VSS

N2

VDD

VSS
N3
VSS

14 VDD
13
12
11
10
9
8

N1

Figure 6: Top view of the CD4007UB chip [2].

14

P1

N1

P3

P2

13 3
8

11

10

12

N2

N3

Figure 7: The functional diagram of the CD4007UB chip [2].

5.1

Experiment 1MOSFETs characteristics

In this experiment, you will examine the iD -vDS and the iD -vGS characteristics of the NMOS
transistor.
5.1.1

Preparation

Prepare these components: CD4007UB chip [2] and R = 1 k.

Using the digital multimeter, measure the resistance and write down the exact value
that you measured.
Use transistor N1 in your experiment (pins 6, 7, and 8).
5.1.2

Procedure

Set the supply voltages.

1. Construct the circuit shown in Fig. 8(a) on the breadboard. Connect the DC power
supply to generate VDD = 10 V. Caution: connect pin 7 (VSS ) to ground.
2. Use the DC power supply to generate vGS and set it to 0 V.
Measure the iD -vGS curve.
1. Set the multimeter as voltmeter to measure the voltage drop across vGS as shown
in Fig. 8(a) by connecting the negative probe (black) to the source terminal of the
transistor (ground) which is pin 7 and the positive probe (red) to the gate terminal of
the transistor which is pin 6 to measure vGS .
2. Keep the negative probe connected to the source terminal of the transistor (ground),
disconnect the positive probe from the gate terminal and connect it to the drain terminal which is pin 8 to measure vDS .
6

+
V

(a)

(b)

Figure 8: Circuits for measuring the characteristics of the NMOS (a) iD -vGS , (b) iD -vDS .
3. For a total of 11 voltage steps of vGS (from 0 V to 10 V), construct a table that
consists of eleven rows and three columns including the measurements of vGS , vDS ,
and the calculation of iD using iD = VDDRvDS .
4. Plot the iD -vGS curve and find the approximate threshold voltage Vt from the plot.
Measure the iD -vDS curve.
1. Use the circuit shown in Fig. 8(b) on the breadboard. Set the DC power supplies to
generate vGS = 2 V and VDD = 10 V.
2. Set the multimeter as voltmeter to measure the voltage drop across VDD as shown
in Fig. 8(b) by connecting the negative probe (black) to the source terminal of the
transistor (ground) and the positive probe (red) to VDD .
3. Keep the negative probe connected to the source terminal of the transistor (ground),
disconnect the positive probe from VDD , and connect it to the drain of the transistor
to measure vDS .
4. Sweep VDD from 0 to 10 V (total of 11 voltage steps), create a table that includes the
measurements of VDD , vDS , and iD .
5. Plot the iD -vDS curve for vGS = 2 V. Calculate the MOSFET transconductance pausing the plot (to detect the current in the saturation region)
rameter kn = n Cox W
L
and equation (2).
6. Repeat steps 1 to 6 with vGS = 4 V.

+
Figure 9: Common source amplifier circuit.

5.2

Experiment 2Common-source amplifier

In this experiment, you will test the operation of a common-source amplifier and measure
the gain of the amplifier.
5.2.1

Preparation

Prepare these components to carry out the experiment: CD4007UB chip [2], RD = 4.7
k, R1 = 330 k, R2 = 100 k, and C1 = 10 F.
Turn on the oscilloscope and test both probes following the steps on the Laboratory 1
manual.
Connect the function generator to channel one on the oscilloscope to produce a 300
mV peak-to-peak sine wave at 1 kHz.
Use transistor N1 (pins 6, 7 and 8).
5.2.2

Procedure

1. Build the circuit shown in Fig. 9 on the breadboard. Connect the DC power supply to
generate VDD = 10 V. Connect vi to the function generator set previously.
2. Connect channel 1 of the oscilloscope to vi and channel 2 to vo .
3. Capture the observed oscilloscopes waveforms.
4. Calculate the gain of the amplifier from the waveforms (magnitude and sign).
5. Calculate the approximate value of gm using equation (9).
6. For the same configuration change the frequency to 10 kHz, 100 kHz, and 1 MHz.
7. Capture the observed oscilloscopes waveforms at the three frequencies.
8. Describe the effect of changing frequency on the gain and the reason it happens.
8

Figure 10: Latch circuit.

5.3

Experiment 3The latch

In this experiment you will build the basic memory element, the latch, which is capable of
storing one bit of information, you will also be able to see how using only inverters, the
memory function is utilized. All three inverters on the CD4007UB [2] will be used in this
experiment.
5.3.1

Preparation

Prepare these components: CD4007UB chip [2], R1 = 1 k, R2 = 1 k, the red LED

[3], and the green LED [4].
Study Fig. 6 and 7, transistors N1, P1 are going to be used as inverter 1, N2, P2 as
inverter 2, N3, P3 as inverter 3.
5.3.2

Procedure

1. Use the CD4007UB chip to build the circuit in Fig. 10 on the breadboard.
2. Connect pins 7, 4, and 9 together to the ground rail (blue) of your breadboard (refer
to Figs. 6 and 7).
3. Connect pins 14, 2, and 11 together to the supply rail (red) of your breadboard (refer
to Figs. 6 and 7).
4. Connect the drains of transistors N1 and P1 together, pins 8 and 13, to form the first
inverter.
5. Connect the drains of transistors N2 and P2 together, pins 5 and 1, to form the second
inverter.
6. Connect the gates of N1 and P1, pin 6, to the drains of transistors N2 and P2, pins 5
and 1.
7. Connect the drains of transistors N1 and P1, pins 8 and 13, to the gates of transistors
N2, P2, pin 3.
9

8. Connect the drains of transistors N2 and P2, pins 5 and 1, to the gates of transistors
N3, P3, pin 10.
9. Connect a wire to the gates of N1 and P1, pin 6, and leave the other end of the wire
unconnected, this will be the input of your latch.
10. Connect the resistors and LEDs as shown in Fig. 10 (output).
11. Use the DC power supply to generate VDD and set it to 5 V.
12. Connect the input wire at pin 6 to the supply rail, observe which LED lights up and
report it.
13. Disconnect the input wire from the supply rail and observe what happens to the LED.
14. Connect the input wire at pin 6 to the ground rail, observe which LED lights up and
report it.
15. Disconnect the wire from the ground rail and observe what happens to the LED.
16. Repeat the experiment with different supply voltage (between 0 V and 5 V) and for
different time length in the input wire is connected and disconnected. Comment on
your observations.

Things to remember
The MOSFET is a voltage-controlled device, where the controlling gate terminal is
insulated from the channel between the drain and source terminals.
The MOSFET has three regions of operation (cut-off, triode, and saturation) described
by different non-linear characteristics.
A key step in the design of transistor amplifiers is to bias the transistor to operate at
an appropriate point in the saturation region.
The basic latch is a bistable 1-bit memory circuit that can be implemented using two
inverters connected in a positive feedback loop.

Writing the laboratory report

7.1

Report format

In a concise and professional manner please provide answers to the experiment questions.
Each group must have no more than two students, who will collaborate in performing the
experiments and writing a single report per group. The report must include the following
items:
A cover page titled Laboratory 3 Report with a colour picture of the circuit built
in experiment 3 (with a resolution of at least 1280 720 pixels). This page should
also report the course and instructor name, time of the laboratory session, as well as
the names of the group members, their identification numbers, and the assigned group
number. Your group number is not the locker number, it is the one that you see on
the course webpage (e.g. when you go to submit the report through the dropbox).
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 About a page for each experiment documenting your activity with the appropriate
graphs, measurements, and measurements conditions (three pages in total).
A final section with your your interpretations, observations, and comments on the
results. You should include a paragraph for each experiment describing what you
should remember from the activity you have completed (one page maximum in total).
Please label carefully all the graphs and use the correct units of measurement. Make sure
that the graphs are clearly visible, including the scales and the titles of the axes.
The guidelines to prepare your report are the following:
Use white paper, letter format (21.6 cm 27.9 cm), portrait orientation, single column,
margins at 2 cm minimum all around.
The text must be in black ink, single-spaced (no more than six lines per inch), in a
font not smaller than Times New Roman regular 12 pts.
Number each page at the top right corner outside the set margins.
The total maximum number of pages allowed is five, the required file format is pdf,
and the maximum file size is 1 MB.
The file name must be lab3group[number].pdf, where number are the three digits of
your group number (e.g. lab3group042.pdf).
Submissions that do not meet the requirements above or the deadline will not be marked
and will receive a grade of zero.

7.2

Timeline

You are asked to submit your report in pdf format using the dropbox Lab 3 report on the
course webpage by Friday, 16 October 2015 at 23:59.

7.3

Evaluation criteria

The following aspects will be considered:

Use of the equipment, experiment set up and correctness of your measurements and
answers.
Interpretation of results and relevance of your observations and remarks.
Quality of the report (clarity, accurate documentation of the results, appropriate labelling, correct use of the units of measurement).
Conciseness and meeting the deadline.

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7.4

Plagiarism

The report submitted by a group must be the result of the group members own work,
measurements, and self-expression. Students may discuss about components, tools, methods,
and requirements among themselves, with the instructor, the teaching assistants, and the
technician. However, each group is responsible for their own laboratory activity and the
report must be written by the group members alone. No exchange of graphs, measurements,
and other material related to the laboratory activity is allowed between groups.
Please remember that copying text, data, or figures is plagiarism, even if you received the
material from a friend or you found it on the Internet. Letting others use your work is also
not allowed, therefore please keep your reports, files, and measurement results in a secure
location. If you are in any doubt as to whether an action on your part could be construed as
an academic offence, you should consult with the instructor before submitting your report.
By submitting the report under your name (individually or as a member of a team),
you are acknowledging that the content of the report is entirely your own work, completed
this term and for this course. If you are a member of a team, you are indicating that each
member has provided approximately equal contribution to the work. You should note that
submitting work done by someone else, or submitting work for which credit has previously
been obtained are forms of academic misconduct.
Electronic means of detection, including Turnitin integrated with the dropbox, will be
used to identify possible plagiarism, unauthorized collaboration or copying as part of the
ongoing efforts to maintain academic integrity at the University of Guelph.
All submitted assignments will be included as source documents in the Turnitin.com
reference database solely for the purpose of detecting plagiarism of such papers. The use of
the Turnitin.com service is subject to the Usage Policy posted on the Turnitin.com site.

References
[1] A. S. Sedra, K. C. Smith. Microelectronic circuits, Oxford, 7th ed., 2014.
[2] CD4007UB chip data sheet:
http://www.ti.com/lit/ds/symlink/cd4007ub.pdf
[3] HLMP-Cx08 red LED data sheet:
http://www.farnell.com/datasheets/1922527.pdf
[4] HLMP-3507 green LED data sheet:
http://www.farnell.com/datasheets/1918235.pdf

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