Models:

LTA-15E302
LTA-20E302
LTA-20E303

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TABLE OF CONTENTS
INPUT IMAGE SIGNAL SAMPLING AREA .........................................................................................................4
OUTPUT IMAGE SIGNAL AND DISPLAY AREA................................................................................................6
OUTPUT MODE 800X600@60HZ ...............................................................................................................................7
OUTPUT MODE 1024X768@60HZ .............................................................................................................................7
OUTPUT MODE 1280X1024@60HZ ...........................................................................................................................8
DE-INTERLACE MODES........................................................................................................................................9
CALCULATION OF SCALING DOWN/UP FACTOR.........................................................................................13
SCALING DOWN FACTOR ........................................................................................................................................13
SCALING UP FACTOR..............................................................................................................................................15
Horizontal Scaling up factor Examples..............................................................................................................15
Vertical Scaling up factor Examples..................................................................................................................16
BUS TYPES .............................................................................................................................................................18
DIRECT BUS ...........................................................................................................................................................18
SERIAL BUS ...........................................................................................................................................................18
NOTICE OF USING OF SERIAL BUS ..................................................................................................................20
FLUSH FUNCTION ................................................................................................................................................21
LINE WRITE...........................................................................................................................................................22
LINE READ.............................................................................................................................................................24
GAMMA FUNCTION .............................................................................................................................................26
PROCEDURE OF MEMORY CLOCK AND OUTPUT DOT CLOCK PROGRAMMING. ...............................27
MEMORY CLOCK REQUIREMENTS AND MEMORY AND OUTPUT VIDEO CLOCK CALCULATION.28
MEMORY CLOCK REQUIREMENTS -- MINIMUM MCLK (MHZ) ................................................................................28
MEMORY CLOCK CALCULATION: ............................................................................................................................28
OUTPUT VIDEO CLOCK CALCULATION:....................................................................................................................29
PROCEDURE OF AUTO TRACKING..................................................................................................................30
AUTO POSITION PROCEDURE ..........................................................................................................................32

MX88L284-V
Revision: 1.0

PROCEDURE OF DRAM SELF-TEST..................................................................................................................34

HOW TO USE EDGE FILTER...............................................................................................................................35
EXTERNAL OSD CLOCK REGISTERS CONTROL PATH ...............................................................................39
CLAMPING SIGNAL POSITION AND BLOCK DIAGRAM ..............................................................................40
MEMORY CLOCK BLOCK DIAGRAM ..............................................................................................................41
SDRAM/SGRAM CONNECTION DIAGRAM......................................................................................................42
4M BYTE SDRAM (2 X 2M BYTE).........................................................................................................................42
32 bit mode for 1280 x 1024 @65Hz(with compression) and 1024 x 768 @85Hz modes.....................................42
2M BYTE SDRAM (1 X 2M BYTE).........................................................................................................................42
16 bit mode for 800x600 @85Hz mode..............................................................................................................42
4M BYTE SGRAM (2 X 2M BYTE).........................................................................................................................43
32 bit mode for 1280x1024 @60Hz(with compression) and 1024x768 @85Hz modes.........................................43
2M BYTE SGRAM (1 X 2M BYTE).........................................................................................................................43
32 bit mode for 800x600 @85Hz mode..............................................................................................................43
VIDEO DECODERS CONNECTION DIAGRAM ................................................................................................44
DOUBLE BUFFER REGISTER .............................................................................................................................45
MX88L284 DOUBLE BUFFER REGISTER LIST ................................................................................................46
INTERRUPT CONTROL .......................................................................................................................................50
SYSTEM NOTES ....................................................................................................................................................51

MX88L284-V
Revision: 1.0

Input Image Signal Sampling Area

HSYNC

VSYNC

ISSPV
Register
08h/09h
ISSPH
Register
0Ah/0Bh
(Reg. 11h D4=0)

Sampled image area

ISDCV
Register
0Ch/0Dh

ISSPH
Register
0Ah/0Bh
(Reg. 11h D4=1)
ISDCH
Register
0Eh/0Fh

Fig. 1 Input image signal sampling area

INPUT MODE

ISSPV REG.

ISDCV REG.

ISSPH REG.

ISDCH REG.

Register

0x08

0x09

0x0C

0x0D

0x0A

0x0B

0x0E

0x0F

720x400@70Hz

0x22

0x00

0x90

0x01

0x38

0x00

0xD0

0x02

640x350@85Hz

0x3B

0x00

0x5E

0x01

0x33

0x00

0x80

0x02

720x400@85Hz

0x2A

0x00

0x90

0x01

0x6C

0x00

0xD0

0x02

640x350@85Hz

0x3C

0x00

0x5E

0x01

0x60

0x00

0x80

0x02

640x480@85Hz

0x19

0x00

0xE0

0x01

0x50

0x00

0x80

0x02

640x480@75Hz

0x10

0x00

0xE0

0x01

0x78

0x00

0x80

0x02

640x480@72Hz

0x1C

0x00

0xE0

0x01

0x80

0x00

0x80

0x02

640x480@60Hz

0x21

0x00

0xE0

0x01

0x30

0x00

0x80

0x02

800x600@85Hz

0x1B

0x00

0x58

0x02

0x98

0x00

0x20

0x03

800x600@75Hz

0x15

0x00

0x58

0x02

0xA0

0x00

0x20

0x03

800x600@72Hz

0x17

0x00

0x58

0x02

0x40

0x00

0x20

0x03

800x600@60Hz

0x17

0x00

0x58

0x02

0x58

0x00

0x20

0x03

MX88L284-V
Revision: 1.0

INPUT MODE

ISSPV REG.

ISDCV REG.

ISSPH REG.

ISDCH REG.

Register

0x08

0x09

0x0C

0x0D

0x0A

0x0B

0x0E

0x0F

800x600@56Hz

0x16

0x00

0x58

0x02

0x80

0x00

0x20

0x03

1024x768@85Hz 0x24

0x00

0x00

0x03

0xD0

0x00

0x00

0x04

1024x768@75Hz 0x1C

0x00

0x00

0x03

0xB0

0x00

0x00

0x04

1024x768@70Hz 0x1D

0x00

0x00

0x03

0x90

0x00

0x00

0x04

1024x768@60Hz 0x1D

0x00

0x00

0x03

0xA0

0x00

0x00

0x04

1024x768@43i

0x14

0x00

0x00

0x03

0x38

0x00

0x00

0x04

1152x864@85Hz 0x2B

0x00

0x60

0x03

0xE0

0x00

0x80

0x04

1152x864@75Hz 0x20

0x00

0x60

0x03

0x00

0x01

0x80

0x04

1152x864@70Hz 0x2C

0x00

0x60

0x03

0xC8

0x00

0x80

0x04

1152x864@60Hz 0x25

0x00

0x60

0x03

0xC0

0x00

0x80

0x04

1280x960@60Hz 0x24

0x00

0xC0

0x03

0x38

0x01

0x00

0x05

1280x1024@85Hz 0x2C

0x00

0x00

0x04

0xE0

0x00

0x00

0x05

1280x1024@75Hz 0x26

0x00

0x00

0x04

0xF8

0x00

0x00

0x05

1280x1024@60Hz 0x26

0x00

0x00

0x04

0xF8

0x00

0x00

0x05

1280x1024@43i

0x00

0x00

0x04

0xB0

0x00

0x00

0x05

0x12

Remark: This table bases on VESA standard modes.

MX88L284-V
Revision: 1.0

Output Image Signal And Display Area

HDTOT
Register
2E h/2F h
HSEND
Register
32 h/33 h
HSYNC

FHDE

HFEND
Register
2Ah/2Bh

HFST
Register
26 h/27 h

HDEND
Register
3A h/3Bh

MVDE

HDST
Register
36 h/37 h

VDST
Register
34 h/35 h

MHDE

VFST
Register
24 h/25 h

VDEND
Register
38 h/39 h

Display Area
Frame Window

The below figure shows the timing diagram of output signal:

Fig. 2 Output image signal and display area

VSYNC

FVDE

VSEND
Register
30 h/31 h

VFEND
Register
28 h/29 h

VDTOT
Register
2Ch/2Dh

MX88L284-V
Revision: 1.0

Output mode 640x480@60Hz

Timing name

Value

Register = Value -1

VDTOT

525(20Dh)

2Ch=0Ch

2Dh=02h

HDTOT

800(320h)

2Eh=1Fh

2Fh=03h

VSEND

30h=01h

31h=00h

HSEND

96(60h)

32h=5Fh

33h=00h

VFST/VDST

35(23h)

24h/34h=22h

25h/35h=00h

HFST/HDST

144(90h)

26h/36h=8Fh

27h/37h=00h

VFEND/VDEND 515(203h)

28h/38h=02h

29h/39h=02h

HFEND/HDEND 784(310h)

2Ah/3Ah=0Fh

2Bh/3Bh=03h

DCLK

25.175

B0h=BCh

B1h=32h

H Sync Polarity

NEGATIVE

E4h bit 0 = 0

V Sync Polarity

NEGATIVE

E4h bit 1 = 0

Output mode 800x600@60Hz

Timing name

Value

Register = Value -1

VDTOT

628(274h)

2Ch=73h

2Dh=02h

HDTOT

1056(420h)

2Eh=1Fh

2Fh=04h

VSEND

30h=03h

31h=00h

HSEND

128(80h)

32h=7Fh

33h=00h

VFST/VDST

27(1Bh)

24h/34h=1Ah

25h/35h=00h

HFST/HDST

216(D8h)

26h/36h=D7h

27h/37h=00h

VFEND/VDEND 627(273h)

28h/38h=72h

29h/39h=02h

HFEND/HDEND 1016(3F8h)

2Ah/3Ah=F7h

2Bh/3Bh=03h

DCLK

40

B0h=B2h

B1h=34h

H Sync Polarity

POSITIVE

E4h bit 0 = 1

V Sync Polarity

POSITIVE

E4h bit 1 = 1

Output mode 1024x768@60Hz

Timing name

Value

Register = Value -1

VDTOT

806(326h)

2Ch=25h

2Dh=03h

HDTOT

1344(540h)

2Eh=3Fh

2Fh=05h

VSEND

30h=05h

31h=00h

HSEND

136(88h)

32h=87h

33h=00h

VFST/VDST

35(23h)

24h/34h=22h

25h/35h=00h

MX88L284-V
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HFST/HDST

296(128h)

26h/36h=27h

27h/37h=01h

VFEND/VDEND 803(323h)

28h/38h=22h

29h/39h=03h

HFEND/HDEND 1320(528h)

2Ah/3Ah=27h

2Bh/3Bh=05h

DCLK

65

B0h=ACh

B1h=BAh

H Sync Polarity

NEGATIVE

E4h bit 0 = 0

V Sync Polarity

NEGATIVE

E4h bit 1 = 0

Output mode 1280x1024@60Hz

Timing name

Value

Register = Value -1

VDTOT

1066(42Ah)

2Ch=29h

2Dh=04h

HDTOT

1688(698h)

2Eh=97h

2Fh=06h

VSEND

30h=02h

31h=00h

HSEND

112(70h)

32h=6Fh

33h=00h

VFST/VDST

41(29h)

24h/34h=28h

25h/35h=00h

HFST/HDST

360(168h)

26h/36h=67h

27h/37h=01h

VFEND/VDEND 1065(429h)

28h/38h=28h

29h/39h=04h

HFEND/HDEND 1640(668h)

2Ah/3Ah=67h

2Bh/3Bh=06h

DCLK

108

B0h=0Ch

B1h=B0h

H Sync Polarity

POSITIVE

E4h bit 0 = 1

V Sync Polarity

POSITIVE

E4h bit 1 = 1

MX88L284-V
Revision: 1.0

De-Interlace Modes

Register 0x13/D[2:0] defines de-interlace mode when input image data is interlace. If input data is noninterlace, all fields are written to frame memory and ignore these bits.
When odd de-interlace mode, only odd fields are written to frame memory.
When even de-interlace mode, only even fields are written to frame memory.
When odd/even de-interlace mode, odd and even fields are written to frame memory and composes to a
complete frame.
When toggle de-interlace mode, each fields are written to different frame memory. When reading from
frame memory, the source of display frame is toggled between two fields data which are in frame
memory.
When Motion-Adaptive de-interlace mode(0x13 D2=1), it only support YCbCr422 format data. The
maximum horizontal dot count of input is 768 dots, and please set register 0x14 as 10h. The VOP vertical
scaling factor is same as write frame model. And it doesnt support horizontal mirror.
Fig. 3 7 explains the relationship between input image and frame memory data.

MX88L284-V
Revision: 1.0

Lines saved to memory

VIP Base 2
VOP Base 1

A input frame

Field 1 (odd)

Field 2 (even)

Line 1
Line 3
Line 5
Line 7


Line 2
Line 4
Line 6
Line 8

Line 1
Line 3
Line 5
Line 7
Line 9
.
.
.
.
.
Last line in odd field

Fig. 3 Interlace input and uses odd de-interlace mode

Lines saved to memory

VIP Base 1
VOP Base 1

A input frame

Field 1 (odd)

Field 2 (even)

Line 1
Line 3
Line 5
Line 7


Line 2
Line 4
Line 6
Line 8

Line 2
Line 4
Line 6
Line 8
Line 10
.
.
.
.
.
Last line in even field

Fig. 4 Interlace input and uses even de-interlace mode

10

MX88L284-V
Revision: 1.0

A input frame

Field 1 (odd)

Field 2 (even)

Line 1
Line 3
Line 5
Line 7


Line 2
Line 4
Line 6
Line 8

Lines saved to memory

VIP/VOP Base 1 Line 1
VIP Base 2
Line 2
Line 3
Line 4
Line 5
.
.
.
.
Last line in odd field
Last line in even field

Fig. 5 Interlace input and uses odd/even (write frame) de-interlace mode
A input frame

Field 1 (odd)

Field 2 (even)

Lines saved to memory

Line 1
Line 3
Line 5
Line 7


Line 2
Line 4
Line 6
Line 8

VIP/VOP Base 1 Line 1

Line 3
Line 5

Last line in odd field

.
.
.
VIP/VOP Base 2 Line 2
Line 4
Line 6
.
Last line in even field

Fig. 6 Interlace input and uses toggle/motion adaptive de-interlace mode

11

MX88L284-V
Revision: 1.0

A input frame
Line 1
Line 2
Line 3
Line 4
Line 5
Line 6
Line 7

Lines saved to memory

VIP/VOP Base 1 Line 1
Line 2
Line 3
Line 4
Line 5
.
.
.
.
.
Last line in the frame

Fig. 7 Non-interlace input and image saved to memory

12

MX88L284-V
Revision: 1.0

Calculation Of Scaling Down/Up Factor

MX88L284 supports scaling down (Decimation) function in VIP (Video Input Processor: the data path
from input signal to memory) and scaling up function in VOP (Video Output Processor: the data path from
memory to panel) respectively.
Before use the scaling functions, you have to make sure the values of (Xi, Yi) and (Xo, Yo) first. For
example, if the input image resolution is 800x600 and the output resolution is 1024x768, then the Xi equal
800, Yi equal 600 and use 1024 as Xo and 768 as Yo. After that, choice the image size which saved to
memory (Xm, Ym) as your wishes. But there are some limitations: 1. The Xm must less or equal Xi and Ym
must less or equal YI 2. For the best quality, use the Xm = Xi and Ym = Yi. The horizontal decimation will
enable if the Xm is smaller than Xi. If Ym is smaller than Yi and Reg. 0x4C D7=1, the vertical decimation is
enabled.

Scaling Down Factor

The QI and QII in the memory write vertical ratio (MWRV) evaluate as following:
Let K1= ISDCV-1, K2=Ym-1
Riv = 2048 * (K1 % K2)
QI of MWRV = int(K1/K2)
If ((Riv % K2) <> 0) then QII of MWRV = int(Riv / K2 ) + 1
Else QII of MWRV = Riv / K2
The calculation of memory write horizontal ratio is similar to vertical ratio calculation. Assume input
image size is (Xi, Yi), data stored to memory is sized as (Xm, Ym), and output image size is (Xo, Yo):
Then ISDCH = Xi,
MWDCH = Xm,
MWRH = (ISDCH 1) / (MWDCH 1),

Let Rih = 2048 * ((ISDCH 1) % (MWDCH 1))

QI of MWRH = int((ISDCH 1) / (MWDCH 1))
If ((Rih % (MWDCH 1)) <> 0) then QII of MWRH = int(Rih / (MWDCH 1) ) + 1
Else QII of MWRH = Rih / (MWDCH 1)

Horizontal Scaling Down Factor Example

Input Xi

Output Xm

640

640

MWRH-H OFFSET 0x52 MWRH-L OFFSET 0x51

0x08

13

0x00

MX88L284-V
Revision: 1.0

720

640

0x09

0x01

800

640

0x0A

0x01

1024

640

0x0C

0xCF

1152

640

0x0E

0x69

1280

640

0x10

0x04

800

800

0x08

0x00

1024

800

0x0A

0x3F

1152

800

0x0B

0x87

1280

800

0x0C

0xCF

1024

1024

0x08

0x00

1152

1024

0x09

0x01

1280

1024

0x0A

0x01

Vertical Scaling Down Factor Example

Input Yi

Output Ym

MWRV-H OFFSET 0x50

MWRV-L OFFSET 0x4F

480

480

0x08

0x00

600

480

0x0A

0x02

768

480

0x0C

0xD0

864

480

0x0E

0x6A

1024

480

0x11

0x16

600

600

0x08

0x00

768

600

0x0A

0x3F

864

600

0x0B

0x87

1024

600

0x0D

0xAA

768

768

0x08

0x00

1024

768

0x0A

0xAC

14

MX88L284-V
Revision: 1.0

Scaling Up Factor
Scaling up factor calculation is easier than scaling downs.
Assume frame data in memory is (Xm, Ym) and will scale up to (Xo, Yo):
The horizontal factor is calculated as follow:
Let scaling up factor F = (Xm 1) / (Xo 1) = 0.ABCDE16, where ABCDE is the fraction part in the
scaling up factor and in hexadecimal. ABCD is the first 4 nibble (16 bits) of the factor F and E is the rest
part of the fraction.
If E = 0, then the ABCD16 is the value should write to MX88L284s scaling up registers.
If E <> 0, then the value (ABCDE16 + 1) should write to MX88L284s scaling up registers.
The same calculation is in vertical except use Ym and Yo.

Horizontal Scaling up factor Examples

When Factor = (Xm-1)/(Xo-1)

Input
Xm

Output
Xo

MRRH-H
Scaling Up
Factor
OFFSET 0x59
F=(Xm-1)/(Xo-1)

MRRH-L

640

800

0.CCBD

0xCC

0xBD

640

1024

0.9FE8

0x9F

0XE8

640

1280

0.7FE7

0x7F

0xE7

720

800

0.E65F

0xE6

0x5F

720

1024

0.B3ED

0xB3

0xED

720

1280

0.8FEA

0x8F

0xEA

800

1024

0.C7F2

0xC7

0xF2

1024

1280

0.CCC3

0xCC

0xC3

1152

1280

0.E662

0xE6

0x62

OFFSET 0x58

When Factor= Xm/Xo

Input
Xm

Output
Xo

Scaling Up
Factor
F=Xm/Xo

MRRH-H
OFFSET 0x59

MRRH-L
OFFSET 0x58

640

800

0.CCCD

0xCC

0xCD

640

1024

0.A000

0xA0

0x00

640

1280

0.8

0x80

0x00

720

800

0.E667

0xE6

0x67

15

MX88L284-V
Revision: 1.0

Input
Xm

Output
Xo

Scaling Up
Factor
F=Xm/Xo

MRRH-H
OFFSET 0x59

MRRH-L
OFFSET 0x58

720

1024

0.B400

0xB4

0x00

720

1280

0.9

0x90

0x00

800

1024

0.C800

0xC8

0x00

1024

1280

0.CCCD

0xCC

0xCD

1152

1280

0.E667

0xE6

0x67

Vertical Scaling up factor Examples

When Factor = (Ym-1)/(Yo-1)

Input
Ym

Output
Yo

MRRV-H
Scaling Up
Factor
OFFSET 0x57
F=(Ym-1)/(Yo-1)

MRRV-L

350

480

0.BA86

0xBA

0x86

350

600

0.9528

0x95

0x28

350

768

0.747D

0x74

0x7D

350

1024

0.5756

0x57

0x56

400

480

0.D53F

0xD5

0x3F

400

600

0.AA87

0xAA

0x87

400

768

0.852D

0x85

0x2D

400

1024

0.63D9

0x63

0xD9

480

600

0.CCB7

0xCC

0xB7

480

768

0.9FE0

0x9F

0xE0

480

1024

0.77DE

0x77

0xDE

600

768

0.C7EE

0xC7

0xEE

600

1024

0.95E6

0x95

0xE6

768

1024

0.BFF0

0xBF

0xF0

864

1024

0.D7F6

0xD7

0xF6

OFFSET 0x56

When Factor = Ym/Yo

Input
Ym

Output
Yo

Scaling Up
Factor
F=Ym/Yo

MRRV-H
OFFSET 0x57

MRRV-L
OFFSET 0x56

350

480

0.BAAB

0xBA

0xAB

16

MX88L284-V
Revision: 1.0

Input
Ym

Output
Yo

Scaling Up
Factor
F=Ym/Yo

MRRV-H
OFFSET 0x57

MRRV-L
OFFSET 0x56

350

600

0.9556

0x95

0x56

350

768

0.74AB

0x74

0xAB

350

1024

0.578

0x57

0x80

400

480

0.D556

0xD5

0x56

400

600

0.AAAB

0xAA

0xAB

400

768

0.8556

0x85

0x56

400

1024

0.64

0x64

0x00

480

600

0.CCCD

0xCC

0xCD

480

768

0.A0000

0xA0

0x00

480

1024

0.78

0x78

0x00

600

768

0.C800

0xC8

0x00

600

1024

0.96

0x96

0x00

768

1024

0.C000

0xC0

0x00

864

1024

0.D800

0xD8

0x00

17

MX88L284-V
Revision: 1.0

Bus Types
MX88L284 support two bus types interface the host CPU: direct and serial bus through Bustype(pin 1). It
can let us access I/O registers and memory described as follows.

Direct Bus
The direct bus use AD[7:0], ALE, RD#, WR# and BCS# to interface with host CPU. This bus use ALE to
latch address on AD bus, WR# / RD# to get data.
BCS#

enable signal for BUS access.

AD[7:0]

is address / data multiplex bus.

ALE = 1 latch I/O address from AD[7:0]

ALE = 0 AD[7:0] represents I/O data
WR# = 0 write data into assigned register
RD# = 0 read data from assigned register
LINE WRITE data port is located at I/O address 0x9F

Serial Bus
This bus type use SBCLK, SBDATA, SBCS# and BCS#.
BCS#

enable I/O function

SBCS#

low active bus enable signal

SBCLK

serial bus clock as valid data indicate

SBDATA

serial bus data

Each I/O access can divide into 3 phase:

Command phase: the first cycle is used to indicate read/write. SBDATA = 0 means WRITE, SBDATA =
1 means READ.
Address phase: the 2-9 cycle is used for sending address. Its LSB first.
Data phase: the following 8 cycles (10-17) contain data. Its LSB first too.
Auto increment: while SBCS# keep in 0 after cycle 17. The I/O address will increase by 1 and the state
will still keep at data phase.

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Fig. 10 CPU Interface Timing

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Notice of using of Serial Bus

Serial bus interface uses the pin 185-183, AD[7]-AD[5] of MX88L284. In MX88L284, there is no pull
high circuits in AD pads. AD[5] and AD[7] are the serial bus chip select and clock pins, they must be
GLITCH FREE !!! Any redundant pulse of these two pins will make error, so when not accessing these
two pins, they should be pulled high by outside circuits.

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Flush Function
Flush function is a speedy way to fill memory with a specified color value.
There are 5 steps to use this function as following:
1.

Switch to still mode (Register 0x11h/bit 5=1)

2.

Setup the color to be filled. ( Register 0x9Bh~0x9Dh)

3.

Setup the line count to be filled. (Register 0x99h/0x9Ah, note that the define in
this registers is different with they are used in line write function)

4.

Set the flush function( Register 0x9Eh/bit 3) and send a start command(Register
0x9Eh/bit 1 = 1)

5.

Wait the ready bit (Register 0x9Eh/bit0) set to 1. You can get the state by polling
this bit directly or waiting for interrupt

6.

Send a stop command.(Register 0x9Eh/bit 1 = 0)

Please note that flush line length is fixed to 1024 pixels and the starting address is decided by reg. 0x96,
0x97, 0x98.

Flush Function Sample Code

xdata unsigned char *io = (unsigned char xdata *)0xC000;
#define REGPORT(reg)
((*io)+reg)
#define CPUWRITEREADY() { while (!(REGPORT(0x9E) & 1)); }
void FlushColor(unsigned char color)
{
REGPORT(0x11) |= 0x20; /* switch to still mode */
REGPORT(0x9B) = colorR; /* setup flush color value */
REGPORT(0x9C) = colorG;
REGPORT(0x9D) = colorB;
/* set lines to write */
REGPORT(0x99) = 0x00;
REGPORT(0x9A) = 0x3;
REGPORT(0x9E) = 0x0A; /* start flush write */
CPUWRITEREADY();/* wait until flush finish */
REGPORT(0x9E) = 0; /* stop flush write */
}

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Line Write
Line writes function is similar to flush function. If you like to write a pattern or a picture to memory, use
the line write function.
Following steps show you the way to use line write function:
1.

Switch to still mode. (Register 0x11h/bit 5 = 1) This step prevent the input data destroy
the image just written to memory.

2.

Set the displayed data format. (Register 0xCEh/bit 7. Bit 7 = 0 means the format is RGB
24 bit data, bit 7 = 1 and means the format is YUV422)

3.

Set the line width in pixels. (Register 0x99h, 9Ah)

4.

Set the written data format (Register 0xCEh/bit 5), write mode to line write (Register
0x9Eh/bit 3 = 0), R/W mode to write (Register 0x9Eh/bit 2 = 0).

5.

Tell the chip to start line write! (Register 0x9Eh/bit 1 = 1)

6.

Write one line data to data port (Register 0x9Fh). Assume there is N pixels in a line, you
write N * 3 byte data in following sequence: R0, G0, B0, R1, G1, B1, RN-1, GN-1, BN-1. If
the data is in YUV422 format, the sequence in N * 2 bytes is as following: Y0, UV0, Y1,
UV0, Y2, UV2, Y3, UV2, Y4, UV4, Y5, UV4, ,Y N-2, UVN-2, YN-1, UVN-2.

7.

Wait ready signal. (Wait register 0x9Eh/bit 0 = 1)

8.

If there is another lines data left, go to step 6 to write next line.

9.

When all lines are written, stop the line write function. (Register 0x9Eh/bit 1 = 0)

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Line Write Function Sample Code

xdata unsigned char *io = (unsigned char xdata *)0xC000;
#define REGPORT(reg)
((*io)+reg)
#define CPUWRITEREADY() { while (!(REGPORT(0x9E) & 1)); }
void LineWriteRGB(void)
{
int i, j;
REGPORT(0x11) |= 0xE0; /* switch to force mode of still mode */
REGPORT(0xCE) &= ~0x80; /* set format to RGB */
/* set write length per scan line */
REGPORT(0x99) = 0; REGPORT(0x9A) = 4;
/* start CPU line write in RGB24 */
REGPORT(0x9E) = 0x02;
/* line write gray scale */
for (j=0; j<768; j++)
{
/* fill gray scale vertically */
for (i=0; i<1024; i++)
{
REGPORT(0x9F) = j; /* write red
*/
REGPORT(0x9F) = j; /* write green */
REGPORT(0x9F) = j; /* write blue */
}
CPUWRITEREADY(); /* wait until line write finish */
}
/* stop CPU line write */
REGPORT(0x9E) = 0x00;
}

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Line Read
The following steps show the way to use line read function:
1.

Switch to still mode. (Register 0x11h/bit 5 = 1) This step prevents the input data from
destroying the image to be read.

2.

Set the displayed data format. (Register 0xCEh/bit 7). Bit 7 = 0 means the format is
RGB 24 bit data, bit 7 = 1 means the format is YUV422.

3.

Set the line width in pixel. (Register 0x99h, 9Ah).

4.

Set the read data format (Register 0xCEh/bit 5), R/W mode to read (Register 0x9Eh/bit
2 = 1).

5.

Tell the chip to start line write! (Register 0x9Eh/bit 1 = 1).

6.

Read one line data from data port (Register 0x9Fh). Assume there are N pixels in a line,
you read N * 3 byte data in the following sequence: R0, G0, B0, R10, G1, B1, RN-1, GN-1,
BN-1. If the data is in YUV422 format, the sequence in N * 2 bytes is as following: Y0,
U0V0, Y1, U0V0, Y2, U2V2, Y3, U2V2, Y4, U4V4, Y5, U4V4, ,Y N-2, U N-2VN-2, YN-1, U N-2VN2.

7.

Wait ready signal. (Wait register 0x9Eh/bit 0 = 1).

8.

IF there is another line to be read, go to step 6 to read next line.

9.

When all lines are read, stop the line read function. (Register 0x9Eh/bit 1 = 0)

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Line Read Function Sample Code

Xdata unsigned char *io = (unsigned char xdata *)0xC000;
Xdata unsigned char databuf[768][1024][3];
#define REGPORT(reg) ((*io)+reg)
#define CPUREADREADY( ) { while (!(REGPORT(0x9E) & 1);
void LineReadRGB(void)
{
int i, j;
REGPORT(0x11) | = 0x20;
REGPORT(0xCE) & = ~0x80;
REGPORT(0x99) = 0;

// switch to still mode

// set format to RGB

REGPORT(0x9A) = 4;

REGPORT(0x9E) = 0x06;

// set read length per scan line

// start line read in RGB

for (j=0; j<768; j++)

{
CPUREADREADY( );
// wait until line read finish
for(i=0; i<1024; i++)
{
databuf[j][i][0] = REGPORT(0x9F);
// read red
databuf[j][i][1] = REGPORT(0x9F);

// read green

databuf[j][i] [2] = REGPORT(0x9F);

// read blue

}
}
REGPORT(0x9E) = 0x04;

// stop line read

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Gamma Function

There are 256 gamma entries in this chip. Following steps show the entries setup sequence:
1.

Reset the gamma I/O access. (Set register 0x3Dh/bit 3 to 0, bit 2 to 0)

2.

Set the gamma I/O accesses on. (Set register 0x3Dh/bit 3 to 1)

3.

Write gamma values (256 * 3 bytes) to register 0x4Ah. (Gamma table index 0 red color
value, then index 0 green value, then index 0 blue value, then index 1 red value, index 1
green value, index 1 blue value, to index 255 red value, index 255 green value, index
255 blue value.)

4.

Reset gamma I/O accesses again.

To turn on the gamma function, just set register 0x3Dh/bit 3 to 1.

Gamma Function Sample Code

xdata unsigned char *io = (unsigned char xdata *)0xC000;
#define REGPORT(reg)
((*io)+reg)
void SetupGammaTable(void)
{
unsigned char val;
REGPORT(0x3D) &= ~0x18; /* reset Gamma I/O */
REGPORT(0x3D) |= 0x10; /* enable Gamma I/O */
/* fill Gamma table */
for (i=0; i<256; i++)
{
val = power((i/255.0),(1/2.2))*255.0;
REGPORT(0x4A) = val; /* fill Gamma red
*/
REGPORT(0x4A) = val; /* fill Gamma green */
REGPORT(0x4A) = val; /* fill Gamma blue */
}
REGPORT(0x3D) &= ~0x18; /* reset Gamma I/O */
REGPORT(0x3D) |= 0x08; /* turn on Gamma function */
}

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Procedure of Memory clock and Output dot clock programming

1. Please follow the below procedure for memory clock and output dot clock programming when power
on.
1. Power On.
2. Program MN register -0xB0 and 0xB1 for output dot clock
0xB2 and 0xB3 for memory clock
3. Load Register Value by
0xB4 D1=1 for output dot clock
0xB4 D0=1 for memory clock
4. Power down enable
0xB1 D6=1 for output dot clock
0xB3 D6=1 for memory clock
5. Wait for over 1ms
6. Power down disable
0xB1 D6=0 for output dot clock
0xB3 D6=0 for memory clock
7. Resume clock load
0xB4 D1=0 for output dot clock
0xB4 D0=0 for memory clock.

2. Initialize MIU
1. Waiting for procedure 1 ready. That means memory clock is generated.
2. Initialize MIU by programming 0x90
read 0x90 D7
if D7=0 then program D7=1
else if D7=1 program D7=0, then program D7=1
3. Reset MIU
set 0xCD D3=1 then set 0xCD D3=0
4. Reset chip
set 0xCD D0=1 then set 0xCD D0=0

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Memory Clock Requirements and Memory and Output Video Clock Calculation
Memory Clock Requirements -- Minimum MCLK (MHz)

Output Mode (Bus Width)

Input Mode

640x480@60Hz 800x600@60Hz 1024x768@60Hz 1280x1024@60Hz

Bus Width(DRAM number) 16(1)

16(1)

32(2)

32(2)

640x480@85Hz

78

92

60

84

800x600@85Hz

101

119

73

97

1024x768@75Hz

126

147

89

111

1024x768@85Hz

133

157

97

119

1280x1024@60Hz

150

173

104

125

1280x1024@75Hz

170

199

121

147

Memory clock Calculation:

Memory clock = clock

clock

when R=00

= clock/2

when R=01 or 10

= clock/4

when R=11

= FREF * [(M+1)/(N+1)]

A.

FREF is the external x'tal frequency, it use 14.318MHz in Macronixs demo system.

B.

Limitation to avoid jitter: FIN>2.0 MHz, FIN=FREF/(N+1) and

100MHz<FVCO<400MHz , FVCO=clock* 2.

C.

To program this value, you have to set the M, N, and R in register 0xB2 and 0xB3.
Then toggle the bit0 of OxB4 (0 -> 1 ->0) to trigger the internal VCG to generate the
new frequency after this setting.

Memory Clock
64.4MHz
68.0MHz
70.2MHz
71.6MHz
75.2MHz
80.2MHz
84.5MHz
90.0MHz
94.9MHz
98.4MHz

Register 0xB2
0x21
0x21
0x24
0x21
0x21
0x04
0x24
0x06
0x023
0x023

Register 0xB3
0x11
0x12
0x30
0x13
0x14
0x1B
0x3A
0x2B
0x34
0x36

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Output video clock Calculation:

Output video clock

= clock

when R=00

= clock/2 when R=01 or 10

= clock/4 when R=11
clock = FREF * 2 * [(M+1)/(N+1)]

A.

FREF is the external x'tal frequency, it use 14.318MHz in Macronixs demo system.

B.

Limitation to avoid jitter: FIN>2.0 MHz, FIN=FREF/(N+1) and

100MHz<FVCO<400MHz , FVCO=clock* BD*2.

C.

BD=4

when B = 00

BD=2

when B = 01

BD=1

when B = 10

BD=1

when B = 11

To program these values, you have to set the M,N, R, and B in register 0xB0 and 0xB1.
Then toggle the bit1 of 0xB4 (0 -> 1 ->0) to trigger the internal VCG to generate the
new frequency after this setting.

Output Video Clock

Register 0xB0

Register 0xB1

Output Resolution

25.05MHz

0xE1

0x86

640x480 @60Hz

40.09MHz

0xE4

0x9B

800x600 @60Hz

49.5MHz

0x2A

0xA5

800x600 @75Hz

50.11MHz

0xA1

0x86

800x600 @72Hz

64.43MHz

0xA1

0x88

1024X768 @60Hz

75.16MHz

0xA3

0x94

1024X768 @70Hz

78.74MHz

0xA1

0x8A

1024X768 @75Hz

107.38MHz

0x83

0x8E

1280x1024 @60Hz

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Procedure of Auto Tracking

Auto tracking is used to detect the input image dot clock rate and phase for programming of external PLL.
We support single/burst mode for your application. Optional mask bit is added to reduce the system noise
from ADC.
Procedure of burst mode Auto Tracking is (0x87 D2=0)
1. set Freq and Phase parameter for first frame
2. set 0x87 D0 = 1 , Enable Tracking any time you wish
3. check 0x87 D1 until = 1 , Tracking result ready
*4. read tracking value 0x8C - 0x88
*5. tune Phase or Freq for next frame . Be sure that the parameter set by CPU must ready before next
frame display start. If not, incorrect input image may affect the tracking result.
*Freq and Phase parameter active to PLL must after ready bit 0x87 D1 = 1 and before
next frame display area reach. Because you have almost 1 input frame time to read
register 0x8C - 0x88, you can reorder procedure4/5 to match the requirement.

6. repeat 3-5
7. set 0x87 D0 = 0 , Tracking done !
8. The correct clock and phase has maximum tracking value.

Note: All CPU reading command must be finished between two adjacent ready pulse. If not, new
tracking result will be loaded when next ready pulse presented. If the reading command too long for
your CPU, you can reduce the input vertical auto tracking range 0x79~0x7C to enlarge the tracking
result ready time.

Suggestion:
1. Before auto tracking , you should do auto position first to make sure that the sample range cover
image source.
2. Set auto tracking horizontal range(0x75~0x78) to both 10 points of left and right side greater than
horizontal image sample range.
3. Make sure that vertical range is corrected by programming the register 0x79~0x7C.
4.Enable the auto tracking range definition in suggestion 2 and 3 by programming the register 0x74 D1.
5. Set register 0x11 D0=1.

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MX88L284-V
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Time slot of auto tracking procedure

Time ->
| FP |
VS
|
BP
|
DISP | FP
|
VS
|
BP
| DISP |
|ready bit
-|
|ready bit
-|
|- Next frame PLL parameter-|
|- Next frame PLL parameter -|
|-- read tracking result registers --|-read tracking result registers --|

FP : Front Porch
BP : Back Porch
VS : Vsync

Procedure of single mode Auto Tracking is (0x87 D2=1)

1. set Freq and Phase parameter for first frame
2. set 0x87 D0 = 1 , start tracking any time you wish
3. check 0x87 D0 until = 0 , tracking done
4. read tracking value 0x8C - 0x88, the tracking value will be hold until your next auto tracking done.
5. tune Phase or Freq for next frame .
6. repeat 2-5 until you finish your frequency and phase loop
7. The correct clock and phase has maximum tracking value.

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MX88L284-V
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Auto position procedure

(1) Description
HSYNC

VSYNC

VPSTACOMP
Register
65 h /66h

HPSTACOMP
Register
61h/62h

Scan area

VPENDCOMP
Register
67 h/68h

HPENDCOMP
Register
63 h /64h

If turn on scan area (0x61 ~ 0x68), the circuit will detect pixel value inside solid line, else it will detect inside
dotted line. About noise margin, if one of RGB value of incoming pixel is over the value among noise margin (0x71 ~
0x73), it will be considered as valid pixel. Therefore we must set the value of 0x71 ~ 0x73 to the smallest pixel value of
all over the frame(if image is clean) or plus one offset(if image has noise).

(2) Usage procedure

[1] Set scan area to proper value. We can turn on it by setting 0x60 D1=1.
[2] Set noise margin to proper value.
[3] Set 0x60 D0=1.
[4] Polling 0x60 D0, Detection will be finished when it becomes 0.
[5] Detect result: 0x69~0x70
0x69~0x6A: Horizontal starting position (STAPOSH)
0x6B~0x6C: Horizontal ending position (ENDPOSH)
0x6D~0x6E: Vertical starting position (STAPOSV)
0x6F~0x70: Vertical ending position (ENDPOSV)
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[6] Result usage :

a. ISSPH:

Data Compress OFF

VIP Low Power OFF

VIP Low Power ON

0x10 D5=0

0x10 D5=1

ISSPH=STAPOSH-1

ISSPH=STAPOSH-2

ISSPH=STAPOSH+2

ISSPH=STAPOSH+4

0xCE D4=0
Data Compress ON
0xCE D4=1

b. ISSPV = STAPOSV - 1.
c. ISDCH = ENDPOSH - STAPOSH + 1 (optional use).
d. ISDCV = ENDPOSV - STAPOSV + 1 (optional use).

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MX88L284-V
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Procedure of DRAM self-test

DRAM self-test is used to check the DRAM cell or connection for memory interface, the procedure is:
1.set 0x93 D2=1,self-testing mode
2.flush write with flush color register 0x9A, 0x9B, 0x9C and cover all memory location
3.wait flush finish
4.modify display area to fit memory size which you want to test
5.set 0x93 D0=1 self-testing start
6.read 0x93 D0 until D0=0 stop
7.read 0x93 D1= 1: test fail
0: test pass
8. 0x93 D2=0 normal mode

Flush Color (FC) fill DRAM in DRAM self-testing mode is

md[47:0] = { Flush Color Red, Flush Color Green, Flush Color Blue, Flush Color Red, Flush Color Green,
Flush Color Blue}
Suggestion : for toggle DRAM reason, you can repeat the procedure and a complement flush color is
applied
Ex. Loop1: Flush Color(0x9A,9B,9C) = 55h, AAh, CCh then md[47:0] = 55AACC 55AACC h
Loop2: Flush Color(0x9A,9B,9C) = AAh, 55h, 33h then md[47:0] = AA5533 AA5533 h
If the result of loop1, loop2 are all pass, then the memory interface of MX88L284 is fine.

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How to use Edge Filter

Function : Programmable edge filter when 0x4F D7=1 should work with
register
0x5A Coef-A
0x5B

Coef-B

0x5C Coef-C

Function = (Next_pixel) * Coef-A + (Current_pixel) * Coef-B +

(Previous_pixel) * Coef-C

1. sharpen

(high pass filter)

meet:
Coef-A + Coef-B + Coef-C = 1
Coef-A, Coef-C < 0

2. blur

(low pass filter)

meet:
Coef-A + Coef-B + Coef-C = 1
Coef-A, Coef-C > 0

3. Misc
no limitation, result depend on Coef-A/Coef-B/Coef-C

Example:
Coef-A/Coef-C

(0x5A / 0x5C)

=============================
D7
X

D6 D5 D4 D3 D2 D1 D0
. X

X
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MX88L284-V
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Sign

Fraction

0.125 (D)

.0

= 10 (H)

0.5

.1

= 40 (H)

.1

= C0 (H)

(D)

-0.5 (D)

(2'complement of 0.5) = inverse (40) + 1

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MX88L284-V
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Decimal meaning

1. positive value
= D7 + 1/2 * D6 + 1/4 * D5 + 1/8 * D4 + 1/16 * D3
+ 1/32 * D2 + 1/64 * D1 + 1/128 * D0

2. negative value
B[7:0] = ~D[7:0] + 1
= - (D7 + 1/2 * D6 + 1/4 * D5 + 1/8 * D4 + 1/16 * D3+ 1/32 * D2 + 1/64 * D1 +
1/128 * D0)

Ex.
40H

= ~(C0)

+1

value = - ( 0 + 1/2 * 1 + 1/4 * 0 + 1/8 *0 + 1/16 *0 + 1/32 * 0 + 1/64 * 0 + 1/128 *0 )

= - 0.5

Coef-B

(0x5B)

(positive value only )

=================================
D7

D6

D5

D4

D3

D2

D1

D0

Integer

1.5

Fraction

(D)

1.

= 60 (H)

3.125 (D)

1.

= C8 (H)

Decimal meaning =2 * D7 + D6 + 1/2 * D5 + 1/4 * D4 + 1/8 * D3

+ 1/16 * D2 + 1/32 * D1 + 1/64 * D0

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=>for Sharpen or blurred purpose , must set

Coef-A + Coef-B + Coef-C = 1

Some typical value (no limitation to Coef-A = Coef-C)

Decimal meaning
Function

Program value

Coef-A 0x5A

Coef-B 0x5B

Coef-C 0x5C

Coef-A 0x5A

Coef-B 0x5B

Coef-C 0x5C

-1

-1

80

C0

80

-0.5

-0.5

C0

80

C0

-0.25

1.5

-0.25

E0

60

E0

-0.125

1.25

-0.125

F0

50

F0

-0.0625

1.125

-0.0625

F8

48

F8

Strong

\|/

\|/

Weak

Strong

0.328125

0.34375

0.328125

2A

16

2A

0.171875

0.65625

0.171875

16

2A

16

\|/

0.125

0.75

0.125

10

30

10

\|/
0.09375

0.8125

0.09375

0C

34

0C

Weak

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External OSD Clock Registers Control Path

VOP 1X clock
GOUT1

00
01

0xA5 D1

0xA5 D3-2
OSD data in

Display data

1
OSDBLINK

0xA5 D0

Delay

0
1
1
VOP 1/2X clock

0xA6 D3-0

0xA6 D6

0xA6 D5

Register 0xA6 active only when 0xA5 D0=1

39

0xA6 D4

LCD

MX88L284-V
Revision: 1.0

Clamping Signal Position and Block Diagram

clamp
delay

Normalized
input HSYNC

clamp
pulse
w idth

Clamp source

Normalized
input HSYNC
clamp source
0

output
Dot clock

Normalized
HSYNC

0x15:D4-0
clamp delay
by output
dot clock

0x15:D5

0x16:D6
0x16:D5-0
clamp pulse w idth
by 4* (output
dot clock)

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MX88L284-V
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Memory Clock Block Diagram

PA D M C L K
MCLK
Delay

0 x91:D2-0

0 x91:D3

DRA M
on Demo Board

lat c h
CLK
MCLK

Delay

1
1

0 x91:D7

Internal
mclk

0 x91:D6-4
0 x92:D7

PAD feedback
MCLK
MCLK

0
1

0 x92:D6
MCLK: memory clock from internal VCG

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SDRAM/SGRAM Connection Diagram

4M Byte SDRAM (2 x 2M Byte)
32 bit mode for 1280 x 1024 @65Hz(with compression) and 1024 x 768 @85Hz modes

512KX16X2

512KX16X2

MD[15:0]

MD[15:0]

MD[31:16]

MD[15:0]

DQM[0]

DQM[1:0]

DQM[1]

DQM[1:0]

RAS

RAS

RAS

RAS

CAS

CAS

CAS

CAS

WE

WE

WE

MA[10:0]
DQM[2]
0

MA[10:0]
MA[11]

MA[10:0]
DQM[2]
0

CS

WE
MA[10:0]
MA[11]
CS

MCLK

CLK

MCLK

CLK

CKE

CKE

CKE

CKE

2M Byte SDRAM (1 x 2M Byte)

16 bit mode for 800x600 @85Hz mode

512KX16X2
MD[15:0]

MD[15:0]

DQM[1:0]

DQM[1:0]

RAS

RAS

CAS

CAS

WE
MA[10:0]
DQM[2]
0

WE
MA[10:0]
MA[11]
CS

MCLK

CLK

CKE

CKE

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MX88L284-V
Revision: 1.0

4M Byte SGRAM (2 x 2M Byte)

32 bit mode for 1280x1024 @60Hz(with compression) and 1024x768 @85Hz modes

256KX32X2

256KX32X2

MD[31:0]

MD[31:0]

MD[31:0]

DQM[0]

DQM[1:0]

DQM[2]

DQM[1:0]

DQM[1]

DQM[3:2]

DQM[3]

DQM[3:2]

MD[31:0]

RAS

RAS

RAS

RAS

CAS

CAS

CAS

CAS

WE

WE

WE

WE

MA[10:0]

MA[10:0]

MA[10:0]

CS

MA[10:0]
CS

MCLK

CLK

MCLK

CLK

CKE

CKE

CKE

CKE

DSF

DSF

2M Byte SGRAM (1 x 2M Byte)

32 bit mode for 800x600 @85Hz mode

256KX32X2
MD[31:0]

MD[31:0]

DQM[0]

DQM[1:0]

DQM[1]

DQM[3:2]

RAS

RAS

CAS

CAS

WE

WE

MA[10:0]
0

MA[10:0]
CS

MCLK

CLK

CKE

CKE
DSF

43

MX88L284-V
Revision: 1.0

Video Decoders Connection Diagram

Brooktree
Bt829
VD[15:8]

Samsung
KSO122/
KS0127

Philips
SAA7111A

Y[7:0]

UV [7:0]

C[7:0]

VPO[7:0]

CLKX2

CK2

LLC2

~VRESET
~FIELD
(H)ACTIVE

PIXINA[7:0]

VPO[15:8]

VD[7:0]

~HRESET

MX88L284
Y[7:0]

PIXINA[15:8]
Video clock

PIXINA23 (MPLLC2)
Video H sync

HS1

PIXINA22 (MPHS)

HS
Video V sync

VS

PIXINA21 (MPVS)

VS
Video odd/even field

ODD

PIXINA20 (MPODD)

RTSO
Video horizontal active flag

HAV

PIXINA19 (MPHREF)

HREF
Video clock x 2 (optional)

CK

LLC

VAV

CREF
VREF

PIXINA18 (MPLLC)
Video clock reference (optional)
Video vertical reference (optional)

PIXINA17 (MPCREF)
PIXINA16 (MPVREF)

Remark: When data valid signal of Brooktree Bt829 become active will make MX88L284 malfunction.

For Video Decoder (e.g. VDP3132Y) which has RGB analog output should be treated as one
special mode of RGB input to ADC. In this case, motion adaptive should not be used for
de-interlace. Toggle mode is recommended.

44

MX88L284-V
Revision: 1.0

Double buffer register

Double buffer is used only when CPU write MX88L284 registers. The programmed value in registers will
not be active until you give a double buffer load signal. When you want to use the double buffer function,
some procedure must be care :

1. program 0x95 D0 =1 enable double buffer function

2. program the registers you want to change.
3. If the registers not in the double buffer register list, they will active right after you program. But if the
registers is a double buffer register, they will not be active until you do procedure 4.
4. give a double buffer load signal, that is
program 0x95 D1=1
5. If the registers in the list of double buffer register are not changed this time by CPU, the double buffer
load signal will not affect the previous stored value in these registers.
6. The double buffer load signal will be tie low automatically when MX88L284 finish this double buffer
load job.

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MX88L284-V
Revision: 1.0

MX88L284 Double buffer register list

1. VIP part
(1) VIP base address 1
0x00
0x01
0x02
(2) VIP base address 2
0x03
0x04
0x05
(3) Memory Write Line Offset
0x06
0x07
(4) Memory Write Horizontal Dot Count
0x4D
0x4E
(5) Memory Write Vertical Ratio
0x4F
0x50
(6) Memory Write Horizontal Ratio
0x51
0x52
(7) Image Vertical Sample Start Point
0x08
0x09
(8) Image Horizontal Sample Start Point
0x0A
0x0B
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MX88L284-V
Revision: 1.0

(9) Image Vertical sample Dot Count

0x0C
0x0D
(10)Image Horizontal Sample Dot Count
0x0E
0x0F
2. VOP part
(1) VOP base address 1
0x1C
0x1D
0x1E
(2) VOP base address 2
0x1F
0x20
0x21
(3) Memory Read Line Offset
0x22
0x23
(4) Memory Read Horizontal Dot Count
0x54
0x55
(5) Edge Filter Coef-A/B/C
0x5A
0x5B
0x5C
(6) Scaling Up Vertical Factor
0x56
0x57

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MX88L284-V
Revision: 1.0

(7) Scaling Up Horizontal Factor

0x58
0x59
(8) Frame Window Vertical Start
0x24
0x25
(9) Frame Window Horizontal Start
0x26
0x27
(10)Frame Window Vertical End
0x28
0x29
(11)Frame Window Horizontal End
0x2A
0x2B
(12)Vertical Total
0x2C
0x2D
(13)Horizontal Total
0x2E
0x2F
(14)Display Vertical SYNC End
0x30
0x31
(15)Display Horizontal SYNC End
0x32
0x33
(16)Display Window vertical Start (frame buffer) / Vsync Start (frame buffer less)
0x34
0x35
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MX88L284-V
Revision: 1.0

(17)Display Window Horizontal Start

0x36
0x37
(18)Display Window Vertical End
0x38
0x39
(19)Display Window Horizontal End
0x3A
0x3B
(20)Brightness Coefficient-RED/GREEN/BLUE
0x3E
0x3F
0x40
(21)Contrast Coefficient-RED/GREEN/BLUE
0x41
0x42
0x43

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MX88L284-V
Revision: 1.0

Interrupt control
1. MX88L284 support an IRQ pin, it generates interrupt request.
2. IRQ could be active high/low when using level triggered, also could be rising/falling edge triggered when
using edge triggered.
3. Each interrupt function could enable or disable independently.
4. In level triggered mode, IRQ will active when any status bit of enabled interrupt function is set, until user
clears this bit.
5. In edge triggered mode, IRQ will generate a pulse when any enabled interrupt event happens. The interrupt
pulse width could be set by register 0xC5.

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MX88L284-V
Revision: 1.0

System Notes
1. POWER
All VDD/VDDP(Pin 2,20,36,37,38,48,65,88,89,105,113,125,138,154,167,168,188) switch to 3.3V
-> Analog core power Pin 36,37 had better separate with another power
-> Digital core power Pin 20,88,113,168 had better separate with VDDP
2. CLOCK
-> Use crystal (14.318 MHz) with R (1 MOhm) /C (22 pF) added circuit or Oscillator to pin XI/XO.
XI
XO
|
|
|
1 MOhm
|
----^^^^^^^^----|
|
|
|
___
___
___22pF
___ 22pF
|
|
|
|
----3. SIGNAL Pin
3.3/5 tolerant Pin : Input signal level can be either 3.3 or 5 V, but output signal level only 3.3V
. Pixin (I)
Pin 3-10
Pin 12-19
Pin 21-28
. CPU Interface (I/O)
Pin 185 - 178 AD[7:0]
Pin 1,187,189,190,191,193,200

BUSTYPE, CPUA15/BCS, ALE, WRZ, RDZ, RSTZ, IRQ

. OSD & MISC (I/O)

Pin 102,104,106,107,108,109,110,111,112
4. General I/O Pin : all input signal pin except 3.3/5 tolerant Pin. 3.3V input level only, had better modify these
signal input level.
GPIOA[5:0] : 199-194

51